CN114927556A - 一种半导体器件及其制备方法 - Google Patents

一种半导体器件及其制备方法 Download PDF

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CN114927556A
CN114927556A CN202210339903.7A CN202210339903A CN114927556A CN 114927556 A CN114927556 A CN 114927556A CN 202210339903 A CN202210339903 A CN 202210339903A CN 114927556 A CN114927556 A CN 114927556A
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semiconductor
semiconductor device
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殷华湘
张青竹
姚佳欣
曹磊
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Institute of Microelectronics of CAS
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Abstract

本发明涉及一种半导体器件及其制备方法，半导体器件的纳米片堆栈部包括：衬底；纳米片堆栈部，其设置在所述衬底上；其中，所述纳米片堆栈部包括：多个纳米片形成的叠层，所述纳米片由半导体材料形成；所述纳米片形成的叠层构成多个导电沟道；环绕式栅极，其环绕于所述纳米堆栈部周围；源漏区；多个所述纳米片之间、靠近源漏区的部分被高应变内侧墙绝缘介质层间隔。本发明通过生长高应变的内侧墙绝缘介质，然后在外延生长和源漏退火工艺之后通过相邻紧密接触的应变传导形成更强的纳米片沟道应变，由此增强载流子迁移率，提升器件与电路性能。

Description

一种半导体器件及其制备方法
技术领域
本发明涉及半导体领域，尤其涉及一种半导体器件及其制备方法。
背景技术
随着晶体管特征尺寸的不断微缩，传统的MOSFET器件经历了由平面结构到三维结构的转变，提升器件性能的同时降低短沟道效应带来的影响。目前主流的三维结构晶体管是FinFET。但是FinFET在5nm以下技术代面临巨大的挑战，而在最新发布的InternationalRoadmap for Devices and Systems(IRDS)中，纳米片环栅晶体管(Nanosheet-GAAFET)是3nm节点之后可以有效替代FinFET的关键器件，并且可以显著抑制短沟效应，提升器件的电流驱动性能。
目前，GAA stacked nanosheet FET的研究进展受到了学术界和产业界的广泛关注。不断更新的制备流程和关键工艺，以及优化后的器件结构是新型CMOS器件的热门研究方向。
GAA stacked nanosheet FET是在FinFET和Nanowire-FET的基础上发展而来的一种具有环栅结构和水平纳米片(NS)作为导电沟道的新型器件。在栅极控制方面，环栅结构具有比FinFET器件结构更好的栅控能力，可以有效抑制器件的短沟道效应；在电流驱动方面，Nanosheet-GAAFET具有有效栅可调和垂直水平方向的堆叠设计也可显著增强器件的电流驱动性能。
但是，常规堆叠纳米片GAA-FET的CMOS集成工艺中,通常在PMOS和NMOS源漏外延中生长压应力的SiGe和张应力的Si，然后通过退火分别形成压应变和张应变的纳米片沟道，从而分别提升空穴和电子迁移率，增加器件与电路性能。但是随着器件尺寸缩小，源漏外延体积受限，且源漏外延体离沟道有一定距离，沟道应变效果受到限制。
发明内容
针对上述技术问题，本发明提出了一种新型半导体器件及其制备方法，生长高应变的内侧墙绝缘介质层，然后在外延和源漏区退火之后通过相邻紧密接触的应变传导形成更强的纳米片沟道应变，由此增强载流子迁移率，提升器件与电路性能。
本发明采用了如下技术方案：
一种半导体器件，包括：
衬底；
纳米片堆栈部，其设置在所述衬底上；其中，所述纳米片堆栈部包括：多个纳米片形成的叠层，所述纳米片由半导体材料形成；所述纳米片形成的叠层构成多个导电沟道；
环绕式栅极，其环绕于所述纳米堆栈部周围；
源漏区；
多个所述纳米片之间、靠近源漏区的部分被高应变内侧墙绝缘介质层间隔。
同时本发明还公开了一种半导体器件的制备方法，包括如下步骤：
提供衬底；
在所述衬底上外延生长由第一半导体/第二半导体交替层叠的超晶格叠层；
刻蚀所述超晶格叠层，形成多个鳍片；
在所述鳍片上形成假栅，并对鳍片进行刻蚀；
对所述鳍片上的第一半导体、第二半导体的超晶格叠层进行选择性刻蚀形成纳米片堆栈部，从外向内刻蚀掉部分超晶格叠层中第一半导体形成的纳米片，刻蚀掉的空间内沉积高应变的内侧墙绝缘介质层，并进行退火，使得高应变的内侧墙绝缘介质层填充刻蚀掉的第一半导体形成的纳米片的空间；
选择外延生长工艺形成源漏区；
介质沉积与平坦化露出假栅；
实现纳米片的沟道释放，其中所述纳米片形成的叠层构成为多个导电沟道；
形成环绕式栅极，环绕于纳米堆栈部周围。
附图说明
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本发明的限制。而且在整个附图中，用相同的参考符号表示相同的部件。
图1为本发明在衬底上生长超晶格叠层示意图。
图2为本发明在超晶格叠层上形成第一侧墙示意图。
图3为本发明刻蚀超晶格叠层形成鳍片示意图。
图4为本发明去除第一侧墙、形成浅槽隔离区沿垂直鳍线方向的纵向剖面示意图。
图5为本发明在鳍片上形成假栅沿垂直鳍线方向的纵向剖面示意图。
图6为本发明在器件中定义的X-X、Y-Y方向。
图7为沿X-X线的剖面示意图，在假栅两侧形成第二侧墙、进行源漏刻蚀。
图8为本发明从外向内刻蚀掉部分第一半导体层沿X-X线的剖面示意图。
图9为本发明沉积高应变的内侧墙绝缘介质层、刻蚀掉外层沉积高应变的内侧墙绝缘介质层、沉积源漏区、形成紧密接触的高应变内侧墙绝缘介质层沿X-X线的剖面示意图。
图10为本发明沉积ILD0层介质层、去掉假栅、纳米沟道释放沿X-X线的剖面示意图。
图11为形成金属栅沿、高K介电层、沉积ILD-1介质层、接触孔光刻与刻蚀的剖面示意图。
具体实施方式
以下，将参照附图来描述本发明的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本发明的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本发明的概念。
在附图中示出了根据本发明实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本发明的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
在本实施例中，提供一种用于制造半导体器件的方法。结合图1-11为本发明的FET器件的制备工艺示意图，制备FET器件工艺包括：
如图1所述，提供衬底101，可为体硅(bulk silicon)。
衬底101是适合于形成一个或多个IC器件的半导体晶圆的部分，当采用体硅衬底，在体硅衬底中通过注入杂质，扩散，退火后形成高掺杂阱区，达到所需阱深。其中对P型FET，上述高掺杂阱区为N阱，注入的杂质为n型杂质离子，比如磷(P)离子；其中对N型FET，上述高掺杂阱区为p阱，注入的杂质为p型杂质离子，比如硼(B)离子。超晶格叠层外延过程中分别调控SiGe厚度和Si厚度，并调控Ge含量形成多组分的SiGe导电沟道。
去除体硅衬底表面的二氧化硅(SiO2)，并在体硅衬底上外延生长出多个周期的第一半导体201’/第二半导体202’的超晶格结构的叠层；超晶格结构中的每一层半导体厚度均在30纳米以下，最终生产出的厚度会直接决定纳米片通道的高度以及静电性能。
其中对P型FET，上述第一半导体201’/第二半导体202’超晶格为Si/SiGe叠层，对于N型FET，上述第一半导体201’/第二半导体202’超晶格为SiGe/Si叠层。
如图2所述，采用自对准的侧墙转移(SIT)工艺形成纳米尺度第一侧墙301阵列，第一侧墙301为氮化硅(SiNX),具体形成过程为：在超晶格叠层上覆盖一层牺牲层302，牺牲层302具体可为多晶硅(PolySi，p-si)或非晶硅(a-si)，刻蚀掉部分牺牲层，积淀氮化硅(SiNx)层，再采用各向异性刻蚀，刻蚀掉剩余的牺牲层，使其仅保留在超晶格叠层上多道周期性氮化硅(SiNx)第一侧墙(spacers)301，所述氮化硅(SiNx)第一侧墙301在光刻中起到硬掩膜(Hard Mask)的作用。
通过刻蚀工艺把外延生长的超晶格叠层做成多个周期分布的鳍片。以第一侧墙301为掩膜进行刻蚀，形成带有超晶格叠层结构的鳍片。所述鳍片上部为超晶格叠层形成的导电通道区，下部为衬底，形成如图3所示的鳍片。该鳍片不仅包括超晶格叠层结构，还包括深入到衬底的单晶硅结构。所述刻蚀工艺为干法刻蚀或湿法刻蚀，在一个实施例中可采用反应离子刻蚀(RIE)。鳍片将用以形成一或多个n型场效晶体管以及/或p型场效晶体管的水平纳米片。尽管图3示出了一个鳍片，应能理解可使用任何合适数量与形态的鳍片。鳍片的高度大约10nm-400nm，宽度大约为1-100nm。
如图4所示，在相邻的两个鳍之间形成浅槽隔离(shallow trench isolation,STI)区103。首先介电绝缘材料进行沉积，然后进行平坦化，例如用CMP工艺，然后进行介电绝缘材料选择性回刻，露出三维的鳍片结构，由此邻近于鳍片以形成浅沟槽隔离区103。浅沟槽隔离区103其上表面一般和鳍片中超晶格叠层结构与衬底单晶硅的界面齐平，也可高于或低于该界面水平线。浅沟槽隔离区103可由合适的介电材料所形成，如二氧化硅(SiO2)、氮化硅(SiNx)等。浅沟槽隔离区103的作用是隔开相邻鳍片上的晶体管。浅沟槽隔离区103区使得超晶格叠层的最底层的第一半导体层201’露出。
如图5所示，在露出的鳍片上、与鳍线相垂直的方向(即Y-Y方向)上形成假栅叠层(dummy gate)。假栅叠层为多层结构，包括栅绝缘介质(未示出)、假栅层106和硬掩膜层108。可采用热氧化、化学气相沉积、溅射(sputtering)等工艺形成假栅叠层结构。假栅叠层结构横跨鳍上部的超晶格叠层，多个假栅沿着鳍线方向周期性分布的。假栅层106所使用的材料可以是多晶硅(PolySi，p-si)或非晶硅(a-si)。硬掩膜层108所使用的材料可以是氧化物、碳化物、碳化物、有机物等。
如图6中定义方向，图6中设置了X-X、Y-Y两条虚线，X-X线为沿鳍线方向、鳍片的中心线，Y-Y线为垂直鳍线方向、鳍片的中心线，后续的附图均是以X-X、Y-Y两条线的剖面示意图。
图7所示，在假栅106两侧、沿鳍线方向(即X-X方向)分别设置氮化硅(SiNx)第二侧墙107，两侧的第二侧墙厚度相同。然后，采用假栅106、第二侧墙107作为掩膜，通过刻蚀工艺对鳍片进行源漏刻蚀。
然后如图8所示，进行pull-back刻蚀，对第一半导体层201’从源漏区向中心方向刻蚀掉部分。然后在鳍片外周沉积高应变的内侧墙绝缘介质层107’，材料可以是SiNX、SiO2、SiCN、SiCOX、SiNOX等,后续通过在外延生长和源漏区退火工艺之后通过相邻紧密接触的应变传导形成更强的纳米片沟道应变，由此增强载流子迁移率，提升器件与电路性能。
然后对高应变的内侧墙绝缘介质层107’进行刻蚀，刻蚀至在竖直放置与第二半导体层202’平齐。前述pull-back刻蚀造成的第一半导体层201’比第二半导体层201’缺失的部分，被高应变的内侧墙绝缘介质层107’填平，从而使得在纳米片沟道中分别在从源到漏的沟道方向上形成张应变和压应变。对于P型FET，生长压应力内侧墙绝缘介质，对于N型FET，生长张应力内侧墙绝缘介质。高应变的内侧墙绝缘介质层膜厚为1nm～100nm。
行外延生长源漏区110’。源漏区110’可利用合适的方法如金属有机化学气相沉积、分子束外延、液相外延、气相外延、选择性外延成长(selective epitaxial growth,SEG)、类似方法或前述的组合形成源极/漏极区。
如图10所示，对源漏区110’进行掺杂，对于P型FET，源漏区材料为硼(B)掺杂SiGe(SiGe:B)，对于N型FET，源漏区材料为磷(P)掺杂硅(Si)(Si:P)，并最终形成源漏区110，并进行退火，进行低温激活，使得纳米片沟道应变增加。退火温度范围为500℃～1000℃。在外延和源漏区退火之后通过相邻紧密接触的应变传导形成更强的纳米片沟道应变，由此增强载流子迁移率，提升器件与电路性能。
然后，在源漏区110上沉积隔离层111，防止后续步骤中假栅层106与源漏区110之间的互连短路，并对隔离层111进行化学机械抛光，使其平坦化，去除硬掩膜层108，露出假栅层106。
然后，通过选择性刻蚀或腐蚀工艺，将前述的多晶硅(PolySi，p-si)或非晶硅(a-si)形成的假栅层106刻蚀或腐蚀掉，即去掉假栅层106。
随后，选择性刻蚀超晶格叠层中的牺牲层，进行纳米片(nanosheet)沟道释放。对鳍片露出的导电通道区部分进行处理，移除每层第一半导体层201’，第一半导体层201’即为牺牲层，对第二半导体形成的纳米片202进行释放。纳米片202宽度范围为1-100nm，厚度范围为1-30nm，各纳米片202之间的间隔范围为3-30nm。
一种实施例，对于P型和N型FET，牺牲层均为GeSi层，选择性移除GeSi层，保留Si层，形成Si水平叠层纳米堆栈器件。选择性移除工艺中可使用相对于Si以较快的速率选择性地刻蚀SiGe的刻蚀剂。在一个实施例中，常规湿法工艺，各向同性腐蚀牺牲层进行纳米沟道释放，从而形成纳米片导电沟道。
另外一种实施例，对于P型和N型FET，分别进行沟道释放。
对于P型FET，牺牲层为Si层，选择性移除Si层，保留SiGe层，形成SiGe水平叠层纳米堆栈器件。选择性移除工艺中可使用相对于SiGe以较快的速率选择性地刻蚀Si的刻蚀剂。在一个实施例中，常规湿法工艺，各向同性腐蚀牺牲层进行纳米沟道释放，从而形成纳米片导电沟道。
对于N型FET，牺牲层为SiGe层，选择性移除SiGe层，保留Si层，形成Si水平叠层纳米堆栈器件。选择性移除工艺中可使用相对于Si以较快的速率选择性地刻蚀SiGe的刻蚀剂。在一个实施例中，常规湿法工艺，各向同性腐蚀牺牲层进行纳米沟道释放，从而形成纳米片导电沟道。
第二半导体纳米层片202叠层，形成了纳米堆栈部。
接着，如图11所示，沉积或生长界面氧化层(IL)，然后沉积高K介质层，使得高K介质层环绕纳米堆栈部表面。高K介电层可具有高于约6.0的介电常数，所述高k介质层材料可采用为HfO2、HfSiOx、HfON、HfSiON、HfAlOx、Al2O3、ZrO2、ZrSiOx、Ta2O5或La2O3的一种或几种的组合。
接着，在假栅106所形成的空间、高K介质层外沉积金属栅，形成多层高K/金属栅结构。金属栅包含覆盖层、阻挡层、功函数层、填充层多层结构。可通过选择光刻和腐蚀形成不同有效功函数的膜层结构，以调控器件阈值。一般利用化学气相沉积、物理气相沉积等工艺形成含金属栅。所述金属栅材料为TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax，MoNx、TiSiN、TiCN、TaAlC、TiAlN、TaN、PtSix、Ni3Si、Pt、Ru、Ir、Mo、Ti、Al、Cr、Au、Cu、Ag、HfRu或RuOx的一种或几种的组合。如图11中所示出，金属栅极填充了假栅层106去除后的空间。其后进行对多层高K/金属栅结构进行化学机械抛光，使其平坦化，并去除暴露于假栅空间之外位介质层表面的多余多层高K/金属栅材料，形成高K介质层115、金属栅113，其中二者填充在原第一半导体层201’的空间形成了环栅结构113-1。
接着在顶部进行ILD-1介质沉积，形成介质CMP层112，在介质CMP层112进行接触孔光刻与刻蚀，沉积孔硅化物114，引出接触电极。
后继完成多层后道互连和钝化保护工艺。
上述即为制备完整的半导体器件的工艺流程，形成了如图11所示的FET器件。
在一个实施例中，FET可采用绝缘体上硅(silicon-on-insulator，SOI)作为衬底，直接在绝缘层SiO2上外延生长超晶格叠层，其余工艺流程与前述以体硅为衬底的FET工艺流程相同，在此不再赘述。衬底101由体硅替换为SOI衬底可以有效抑制器件的衬底泄漏电流。
至此，提供了一种FET器件结构，如图11所述，FET器件包括：其包括衬底101，衬底101上由第二半导体形成的纳米片202堆叠形成的堆栈部。宽度范围为1-100nm，厚度范围为1-30nm，各纳米片202之间的间隔范围为3-30nm。。由第二半导体形成的纳米片202之间、靠近源漏区的地方被高应变的内侧墙绝缘介质层间隔；高应变的内侧墙绝缘介质层膜厚为1nm～100nm。。
环绕式栅极，其环绕于纳米堆栈部周围；环绕式栅极由内及外具体包括高K介电层115和金属栅113。高K介质层环绕纳米堆栈部表面，高K介电层115可具有高于约6.0的介电常数，所述高k介质层材料可采用为HfO2、HfSiOx、HfON、HfSiON、HfAlOx、Al2O3、ZrO2、ZrSiOx、Ta2O5或La2O3的一种或几种的组合。
金属栅113位于高K介电质层115内，金属栅113可为多层结构，所述金属栅材料为TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax，MoNx、TiSiN、TiCN、TaAlC、TiAlN、TaN、PtSix、Ni3Si、Pt、Ru、Ir、Mo、Ti、Al、Cr、Au、Cu、Ag、HfRu或RuOx的一种或几种的组合。
上述本申请实施例中的技术方案，至少具有如下的技术效果或优点：
本发明通过在半导体纳米片之间生长高应变的内侧墙绝缘介质层，然后在外延和源漏退火之后通过相邻紧密接触的应变传导形成更强的纳米片沟道应变，由此增强载流子迁移率，提升器件与电路性能。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本发明的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本发明的范围。本发明的范围由所附权利要求及其等价物限定。不脱离本发明的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本发明的范围之内。

Claims (20)

1.一种半导体器件，其特征在于：包括：
衬底；
纳米片堆栈部，其设置在所述衬底上；其中，所述纳米片堆栈部包括：多个纳米片形成的叠层，所述纳米片由半导体材料形成；所述纳米片形成的叠层构成多个导电沟道；
环绕式栅极，其环绕于所述纳米堆栈部周围；
源漏区；
多个所述纳米片之间、靠近源漏区的部分被高应变内侧墙绝缘介质层间隔。
2.根据权利要求1所述的半导体器件，其特征在于：所述半导体材料为Si或者SiGe。
3.根据权利要求1所述的半导体器件，其特征在于：所述环绕式栅极由外到内依次包括界面氧化层、高K介质层和金属栅。
4.根据权利要求1所述的半导体器件，其特征在于：所述纳米片宽度范围为1-100nm，厚度范围为1-30nm，多个纳米片之间的间隔范围为3-30nm。
5.根据权利要求1所述的半导体器件，其特征在于：所述衬底为体硅或绝缘体上硅。
6.根据权利要求1所述的半导体器件，其特征在于，所述高应变的内侧墙绝缘介质层为SiNX、SiO2、SiCN、SiCOX或SiNOX。
7.根据权利要求3所述的半导体器件，其特征在于：所述高k介质层材料为HfO2、HfSiOx、HfON、HfSiON、HfAlOx、Al2O3、ZrO2、ZrSiOx、Ta2O5或La2O3的一种或几种的组合；所述金属栅材料为TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax，MoNx、TiSiN、TiCN、TaAlC、TiAlN、TaN、PtSix、Ni3Si、Pt、Ru、Ir、Mo、Ti、Al、Cr、Au、Cu、Ag、HfRu或RuOx的一种或几种的组合。
8.根据权利要求1所述的半导体器件，其特征在于：高应变的内侧墙绝缘介质层膜厚为1nm～100nm。
9.根据权利要求1所述的半导体器件，其特征在于：对于P型半导体器件，生长压应力内侧墙绝缘介质，对于N型半导体器件，生长张应力内侧墙绝缘介质。
10.一种半导体器件的制备方法，其特征在于：包括如下步骤：
提供衬底；
在所述衬底上外延生长由第一半导体/第二半导体交替层叠的超晶格叠层；
刻蚀所述超晶格叠层，形成多个鳍片；
在所述鳍片上形成假栅，并对鳍片进行刻蚀；
对所述鳍片上的第一半导体、第二半导体的超晶格叠层进行选择性刻蚀形成纳米片堆栈部，从外向内刻蚀掉部分超晶格叠层中第一半导体形成的纳米片，刻蚀掉的空间内沉积高应变的内侧墙绝缘介质层，并进行退火，使得高应变的内侧墙绝缘介质层填充刻蚀掉的第一半导体形成的纳米片的空间；
选择外延生长工艺形成源漏区；
介质沉积与平坦化露出假栅；
实现纳米片的沟道释放，其中所述纳米片形成的叠层构成为多个导电沟道；形成环绕式栅极，环绕于纳米堆栈部周围。
11.根据权利要求10所述的方法，其特征在于：所述形成多个鳍片步骤具体为：在所述超晶格叠层上设置第一侧墙；以所述第一侧墙为掩膜刻蚀所述超晶格叠层，形成所述多个鳍片。
12.根据权利要求11所述的方法，其特征在于：还包括形成浅沟槽隔离区，具体为：在相邻鳍片之间生成浅沟隔离区，使得所述多个导电沟道位于浅沟隔离区之上。
13.根据权利要求12所述的方法，其特征在于：还包括形成源漏区，具体为：刻蚀掉相邻假栅之间的鳍片结构以形成源极、漏极生长空间；在所述生长空间外延生长源漏区，并在源漏区上淀积隔离层。
14.根据权利要求13所述的方法，其特征在于：形成所述环绕式栅极步骤具体为：形成源漏区后，选择腐蚀去掉假栅，在实现纳米片沟道释放后，在原假栅位置积淀栅极。
15.根据权利要求10所述的方法，其特征在于：所述第一半导体为Si，所述第二半导体为SiGe或者第一半导体为SiGe，所述第二半导体为Si。。
16.根据权利要求16所述的方法，其特征在于：所述环绕式栅极由外到内依次包括界面氧化层、高K介质层和金属栅。
17.根据权利要求10所述的方法，其特征在于：退火温度范围为500℃～1000℃。
18.根据权利要求10所述的方法，其特征在于：所述高应变的内侧墙绝缘介质层为SiNX、SiO2、SiCN、SiCOX、SiNOX。
19.根据权利要求10所述的方法，其特征在于：高应变的内侧墙绝缘介质层膜厚为1nm～100nm。
20.根据权利要求10所述的方法，其特征在于：对于P型半导体器件，生长压应力内侧墙绝缘介质，对于N型半导体器件，生长张应力内侧墙绝缘介质。
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