CN114883287A - 半导体封装结构及封装方法 - Google Patents
半导体封装结构及封装方法 Download PDFInfo
- Publication number
- CN114883287A CN114883287A CN202111548773.XA CN202111548773A CN114883287A CN 114883287 A CN114883287 A CN 114883287A CN 202111548773 A CN202111548773 A CN 202111548773A CN 114883287 A CN114883287 A CN 114883287A
- Authority
- CN
- China
- Prior art keywords
- heat dissipation
- semiconductor chip
- semiconductor
- dissipation block
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 106
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 19
- 230000017525 heat dissipation Effects 0.000 claims abstract description 107
- 239000004033 plastic Substances 0.000 claims abstract description 53
- 239000000853 adhesive Substances 0.000 claims abstract description 16
- 230000001070 adhesive effect Effects 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 239000008393 encapsulating agent Substances 0.000 claims 1
- 230000002708 enhancing effect Effects 0.000 abstract description 3
- 238000001746 injection moulding Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 230000009977 dual effect Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229940125898 compound 5 Drugs 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/48175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
- H01L2224/48179—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the bond pad protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
本发明公开了一种半导体封装结构及封装方法,该封装结构包括:引线框架,包括基岛和多个引脚,基岛的第一表面上设置有凹槽,多个引脚彼此间隔设置于基岛的周边;半导体芯片,至少部分地沉入凹槽内,并通过粘接剂至少与凹槽的底部粘连固定;多个键合线,用于连接多个引脚与半导体芯片的引出端;散热块,位于半导体芯片和多个键合线的上方;塑封体,用于封装引线框架、半导体芯片、多个键合线和散热块,其中,散热块部分的被嵌入在塑封体内。本发明可以增强封装结构的散热能力,对增强引线框架类的封装散热能力具有较强的通用性。
Description
技术领域
本发明涉及半导体封装技术领域,具体涉及一种半导体封装结构及封装方法。
背景技术
大规模集成器件和超大规模集成器件,其电路的工作温度极限要求特别严,因而与这些器件有关的散热问题变得特别敏锐。
目前引线框架封装在半导体市场中依旧占很高的市场份额。引线框架类封装的散热路径包括引线键合的四周管脚、塑封料顶部及四周的裸露面积以及部分封装如QFN、DFN等存在底部裸露的焊盘。
对于引线框架类封装而言,当将其焊接在PCB板上后,芯片因工作升温而带来的热量也会经由封装结构传热到PCB板上,此时PCB板在芯片散热过程中也会起到较大作用。然而,芯片通过PCB板进行散热主要依赖于PCB板的散热能力,当PCB板的散热能力受到限制比如PCB板尺寸较小时,PCB板与空气进行热交换的面积较小,进而引线框架类封装的散热能力将会大大削弱,使得封装内芯片的温度大幅升高,进而会限制芯片的使用。也即是说,现有的引线框架类封装结构的散热方案的通用性较差。
因此,有必要提供改进的技术方案以克服现有技术中存在的以上技术问题。
发明内容
为了解决上述技术问题,本发明提供了一种半导体封装结构及封装方法,可以增强封装结构的散热能力,对增强引线框架的封装散热能力具有较强的通用性。
根据本公开第一方面,提供了一种半导体封装结构,包括:引线框架,包括基岛和多个引脚,所述基岛的第一表面上设置有凹槽,多个引脚彼此间隔设置于基岛的周边;
半导体芯片,至少部分地沉入所述凹槽内,并通过粘接剂至少与所述凹槽的底部粘连固定;
多个键合线,用于连接所述多个引脚与所述半导体芯片的引出端;
散热块,位于所述半导体芯片和所述多个键合线的上方;
塑封体,用于封装所述引线框架、所述半导体芯片、所述多个键合线和所述散热块,
其中,所述散热块部分的被嵌入在所述塑封体内。
可选地,所述凹槽的开口尺寸大于所述半导体芯片的尺寸,当所述半导体芯片沉入所述凹槽内时,所述半导体芯片的至少一侧与所述凹槽的侧壁之间存在间隙。
可选地,所述散热块位于所述塑封体内的部分的底部与所述多个键合线的顶部彼此之间绝缘隔离。
可选地,所述基岛由金属材料制成。
可选地,所述半导体芯片包括多个引出端,且所述半导体芯片远离所述多个引出端的表面通过粘接剂与所述凹槽的底部粘连。
可选地,所述半导体封装结构还包括:散热片,设置于所述基岛的第二表面上。
可选地,所述多个引脚中包含有散热引脚。
可选地,所述散热块位于所述塑封体内的部分为倒阶梯结构。
可选地,所述散热块位于所述塑封体内的部分的截面形状为倒T字形。
可选地,所述散热块位于所述塑封体内的部分的截面形状为矩形。
可选地,所述散热块位于所述塑封体外的部分的截面形状为矩形。
可选地,所述散热块位于所述塑封体外的部分为翅片状结构。
可选地,所述散热块为金属块。
根据本公开第二方面,提供了一种半导体封装方法,包括:提供引线框架;
在所述引线框架上蚀刻形成凹槽;
将半导体芯片的至少部分沉入所述凹槽内并与所述引线框架电连接;
提供散热块;
对所述引线框架、所述半导体芯片和所述散热块进行塑封,
其中,所述散热块部分的被嵌入在所述塑封体内。
可选地,所述散热块位于所述塑封体内的部分为倒阶梯结构,或者所述散热块位于所述塑封体内的部分的截面形状为倒T字形或矩形。
可选地,所述散热块位于所述塑封体外的部分为翅片状结构,或者所述散热块位于所述塑封体外的部分的截面形状为矩形。
本发明的有益效果至少包括:
本发明实施例的半导体封装结构及封装方法中设置于引线框架上的具有一定深度的凹槽使得半导体芯片可以部分的沉入凹槽内,进而能够在半导体芯片与键合线上方预留出更大的可进一步处理的注塑空间,进而通过在该部分空间内嵌入散热块的部分,增加了封装结构的散热面积,同时由于嵌入在塑封体内的散热块部分替换了部分的塑封料,极大地降低了芯片节温至封装结构顶部的散热路径的热阻,在增强封装结构的散热能力的同时,对封装结构尺寸的改变程度较小,且对增强引线框架的封装散热能力具有较强的通用性,适合PCB散热受限或封装本身散热能力较弱的情形。
在优选地实施例中,半导体芯片的至少一侧与凹槽的侧壁之间的间隙可以作为溢胶缝隙,在保证半导体芯片与凹槽之间的紧密固定的情况下,也能够尽可能地减小凹槽底部的粘结剂对芯片沉入凹槽内的深度的影响,进一步地增大了半导体芯片与键合线上方所预留出的可进一步处理的注塑空间的大小。
在优选地实施例中,散热块的底部与多个键合线的顶部彼此之间绝缘隔离,可以防止多个键合线短路。
应当说明的是,以上的一般描述和后文的细节描述仅是示例性和解释性的,并不能限制本发明。
附图说明
图1示出根据本发明实施例提供的引线框架的结构示意图;
图2示出根据本发明实施例提供的引线框架承载半导体芯片时的结构示意图;
图3示出根据本发明实施例提供的采用键合线连接半导体芯片与引线框架后的剖面结构示意图;
图4示出根据本发明实施例提供的半导体封装结构的剖面结构示意图;
图5示出根据本发明实施例提供的半导体封装方法的流程示意图。
具体实施方式
为了便于理解本发明,下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施例。但是,本发明可以通过不同的形式来实现,并不限于本文所描述的实施例。相反的,提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。
本发明所公开的半导体封装结构可应用于例如QFN(Quad Fiat Nolead,方形扁平无引脚封装)、SOP(Small Outline Package,小尺寸封装)、ESOP(Exposed-Pad SmallOutline Package,裸露焊盘的小外形封装)、DFN(dual flat No-lead,双列扁平无引脚封装)、PDFN(Power Dual Flat No-lead,双列扁平无引脚功率封装)、DIP(Dual In-linePackage,双列直插式封装)、SOT(Small Outline Transistor,小外形晶体管封装)等封装结构中。
如图4所示,本发明实施例提供的半导体封装结构(本文中可简称为封装结构)100包括:引线框架1、半导体芯片(本文中可简称为芯片)2、多个键合线3、散热块4和塑封体5。
其中,引线框架1包括框架基体11以及设置于框架基体11上的基岛12和多个引脚13。
基岛12用于贴装芯片。基岛12包括第一表面和第二表面,基岛12的第一表面用于承载芯片,本实施例中,基岛12的第一表面上设置有凹槽14,半导体芯片2至少部分地沉入凹槽14内并通过粘接剂贴附于凹槽14内,其中半导体芯片2至少与凹槽14的底部粘连固定。如此,可以在半导体芯片2与键合线3上方预留出更大的可进一步处理的注塑空间。
可选地,贴附于基岛12上的半导体芯片2包括功率芯片和普通芯片中的至少之一。对于功率芯片,芯片2与凹槽14之间的粘接剂可选用为具有导电性能的导电胶;对于普通芯片,芯片2与凹槽14之间的粘接剂可选用为具有具有良好导热性能的绝缘胶。示例性的,基岛12例如可由金属材料(如铝)制作形成,以增强对芯片的散热性能。且进一步的,可选择将芯片2远离其多个引出端(即芯片引脚)的一面与凹槽14进行粘接,以保证芯片2的引出端不会与金属基岛12接触,以及方便后续的键合工艺。
进一步地,可在基岛12的第二表面上设置散热片以进一步提高封装结构100的散热能力。
可以理解的是,本发明中引线框架1上的基岛12的数量可以为1个也可以为多个,本发明对此不做限定。当基岛12的数量为多个时,可在每个基岛12上均设置对应的凹槽14。且每个基岛12上的凹槽14的开口形状与对应设置于该基岛12上的芯片2的形状大体相同,以及每个基岛12上的凹槽14的开口尺寸大于对应设置于该基岛12上的半导体芯片2的尺寸,当半导体芯片2沉入凹槽14内时,半导体芯片2的至少一侧与凹槽14的侧壁之间存在间隙。当半导体芯片2通过粘接剂贴附于凹槽14内时,该间隙可以作为溢胶缝隙,在保证半导体芯片2与凹槽14之间的紧密固定的情况下,也能够尽可能地减小凹槽14底部的粘结剂对芯片2沉入凹槽内的深度的影响,进而进一步地增大半导体芯片2与键合线3上方所预留出的可进一步处理的注塑空间的大小。
多个引脚13彼此间隔设置的位于基岛12的周边。可选地,可将多个引脚13中的每个引脚均作为功能引脚,通过多个键合线3与半导体芯片2的引出端电连接;也可将多个引脚13中的部分引脚作为功能引脚通过多个键合线3与半导体芯片2的引出端电连接,另一部分引脚彼此相连后作为散热引脚,以进一步增强封装结构100的散热能力。
散热块4位于半导体芯片2和多个键合线3的上方。且当采样塑封料对引线框架1、半导体芯片2、多个键合线3和散热块4进行塑封以形成塑封体5时,散热块4部分的被嵌入在塑封体5内。由于嵌入在塑封体5内的散热块部分替换了部分的塑封料,因此可以极大地降低芯片节温至封装结构顶部的散热路径的热阻,进而增强引线框架的封装散热能力,具有较强的通用性,适合PCB散热受限或封装本身散热能力较弱的情形。
进一步地,由于本发明实施例在引线框架1的基岛12上设置有凹槽14,并将半导体芯片2部分的沉入凹槽14内,进而能够在半导体芯片2与键合线3上方预留出更大的可进一步处理的注塑空间,当通过将散热块4的部分嵌入至塑封体5内以增加封装结构的散热能力时,对封装结构尺寸的改变程度较小,有助于实现半导体封装结构的小型化。因此,本发明实施例所公开的半导体封装结构能够实现对良好散热性能和小型化的兼容,具有很强的通用性和市场价值。
本实施例中,散热块4为具有良好散热性能的金属块。可以理解的是,如图3所示,当采用多个键合线3实现多个引脚13与半导体芯片2的引出端之间的电连接时,多个键合线3中的每个键合线在半导体芯片2的上方具有一定的打线高度,因此,本实施例中设置散热块4位于塑封体5内的部分的底部与多个键合线3的顶部彼此之间绝缘隔离,可以防止多个键合线3出现短路的情况。
可选地,在本发明一个可能的实施例中,散热块4位于塑封体5内的部分的截面形状为矩形。如此,可以实现对散热块4塑封料的更大程度的替换,进而能够更大程度地降低芯片节温至封装结构顶部的散热路径的热阻,以及更好地增强封装结构的散热能力。
可选地,在本发明另一个可能的实施例中,散热块4位于塑封体5内的部分的截面形状为倒T字形。如此,能够更大程度地增强散热块4与塑封体5之间的固定程度,有效的防止散热块4脱落。
可选地,在本发明再一个可能的实施例中,散热块4位于塑封体5内的部分为倒阶梯结构。如此,在很好的增强了封装结构100的散热性能的同时,也能够有效的防止散热块4脱落。
进一步地,散热块4还包括位于塑封体5外部的部分。如此,能够增加封装结构100的散热面积,进一步地增强了封装结构的散热能力。
可选地,在本发明一个可能的实施例中,散热块4位于塑封体5外的部分的截面形状为矩形,无需过多加工步骤,制作简单。在本发明另一个可能的实施例中,散热块4位于塑封体5外的部分为翅片状结构,能够更大程度地增加封装结构100的散热面积。
进一步地,本发明还公开了一种半导体封装方法,可用于形成如图4和前述各实施例中所描述的半导体封装结构。参考图5,该半导体封装方法具体包括执行如下步骤:
在步骤S1中,提供引线框架。
参考图1,本实施例中,引线框架1包括框架基体11、基岛12和多个引脚13。其中,所形成的引线框架1的具体结构可参考前文描述,此处不再赘述。
在步骤S2中,在引线框架上蚀刻形成凹槽。
本实施例中,参考图1,可对承载半导体芯片2的引线框架1上的基岛12进行蚀刻处理,以蚀刻形成具有预定深度的凹槽14。
在步骤S3中,将半导体芯片的至少部分沉入所述凹槽内并与所述引线框架电连接。
本实施例中,参考图2,将半导体芯片2至少部分地沉入凹槽14内并通过粘接剂贴附于凹槽14内,其中半导体芯片2至少与凹槽14的底部粘连固定。同时参考图3,可采用键合工艺实现半导体芯片2的引出端与引线框架1的多个引脚13之间的电连接。
进一步地,基岛12上的凹槽14的开口形状与对应设置于该基岛12上的芯片2的形状大体相同,以及每个基岛12上的凹槽14的开口尺寸大于对应设置于该基岛12上的半导体芯片2的尺寸,当半导体芯片2沉入凹槽14内时,半导体芯片2的至少一侧与凹槽14的侧壁之间存在间隙。当半导体芯片2通过粘接剂贴附于凹槽14内时,该间隙可以作为溢胶缝隙,在保证半导体芯片2与凹槽14之间的紧密固定的情况下,也能够尽可能地减小凹槽14底部的粘结剂对芯片2沉入凹槽内的深度的影响,进而进一步地增大半导体芯片2与键合线3上方所预留出的可进一步处理的注塑空间的大小。
在步骤S4中,提供散热块。
本实施例中,散热块4例如为具有特定样式和良好散热性能的金属块。
在步骤S5中,对引线框架、半导体芯片和散热块进行塑封。
本实施例中,可通过塑封模具将引线框架1、半导体芯片2和散热块4进行塑封,形成塑封体5。且可选地,塑封体5采用具有绝缘属性且结合力强的材料,如为环氧树脂。
进一步的,在塑封过程中,可采用塑封料对散热块4的部分进行包裹塑封,以使得散热块4部分地被嵌入在塑封体5内。此时,可选地,散热块4位于塑封体5内的部分为倒阶梯结构,或者散热块4位于塑封体5内的部分的截面形状为倒T字形或矩形。当散热块4未完全嵌入至塑封体5内时,可选地,散热块4位于塑封体5外的部分为翅片状结构,或者散热块4位于塑封体5外的部分的截面形状为矩形。具体可参考前述对散热块4的描述进行理解,此处不再赘述。
综上,本发明实施例的半导体封装结构及封装方法中设置于引线框架上的具有一定深度的凹槽使得半导体芯片可以部分的沉入凹槽内,进而能够在半导体芯片与键合线上方预留出更大的可进一步处理的注塑空间,进而通过在该部分空间内嵌入散热块的部分,增加了封装结构的散热面积,同时由于嵌入在塑封体内的散热块部分替换了部分的塑封料,极大地降低了芯片节温至封装结构顶部的散热路径的热阻,在增强封装结构的散热能力的同时,对封装结构尺寸的改变程度较小,且对增强引线框架的封装散热能力具有较强的通用性,适合PCB散热受限或封装本身散热能力较弱的情形。
在优选地实施例中,半导体芯片的至少一侧与凹槽的侧壁之间的间隙可以作为溢胶缝隙,在保证半导体芯片与凹槽之间的紧密固定的情况下,也能够尽可能地减小凹槽底部的粘结剂对芯片沉入凹槽内的深度的影响,进一步地增大了半导体芯片与键合线上方所预留出的可进一步处理的注塑空间的大小。
在优选地实施例中,散热块的底部与多个键合线的顶部彼此之间绝缘隔离,可以防止多个键合线短路。
最后应说明的是:显然,上述实施例仅仅是为清楚地说明本发明所作的举例,而并非对实施方式的限定。对于所属领域的普通技术人员来说,在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引申出的显而易见的变化或变动仍处于本发明的保护范围之中。
Claims (13)
1.一种半导体封装结构,其中,包括:
引线框架,包括基岛和多个引脚,所述基岛的第一表面上设置有凹槽,多个引脚彼此间隔设置于基岛的周边;
半导体芯片,至少部分地沉入所述凹槽内,并通过粘接剂至少与所述凹槽的底部粘连固定;
多个键合线,用于连接所述多个引脚与所述半导体芯片的引出端;
散热块,位于所述半导体芯片和所述多个键合线的上方;
塑封体,用于封装所述引线框架、所述半导体芯片、所述多个键合线和所述散热块,
其中,所述散热块部分的被嵌入在所述塑封体内。
2.根据权利要求1所述的半导体封装结构,其中,所述凹槽的开口尺寸大于所述半导体芯片的尺寸,当所述半导体芯片沉入所述凹槽内时,所述半导体芯片的至少一侧与所述凹槽的侧壁之间存在间隙。
3.根据权利要求1所述的半导体封装结构,其中,所述散热块位于所述塑封体内的部分的底部与所述多个键合线的顶部彼此之间绝缘隔离。
4.根据权利要求1所述的半导体封装结构,其中,所述基岛由金属材料制成。
5.根据权利要求1所述的半导体封装结构,其中,所述半导体芯片包括多个引出端,且所述半导体芯片远离所述多个引出端的表面通过粘接剂与所述凹槽的底部粘连。
6.根据权利要求1所述的半导体封装结构,其中,所述半导体封装结构还包括:
散热片,设置于所述基岛的第二表面上。
7.根据权利要求1所述的半导体封装结构,其中,所述多个引脚中包含有散热引脚。
8.根据权利要求1所述的半导体封装结构,其中,所述散热块位于所述塑封体内的部分为倒阶梯结构;或者所述散热块位于所述塑封体内的部分的截面形状为倒T字形或矩形。
9.根据权利要求8所述的半导体封装结构,其中,所述散热块位于所述塑封体外的部分的截面形状为矩形;或者所述散热块位于所述塑封体外的部分为翅片状结构。
10.根据权利要求1所述的半导体封装结构,其中,所述散热块为金属块。
11.一种半导体封装方法,其中,包括:
提供引线框架;
在所述引线框架上蚀刻形成凹槽;
将半导体芯片的至少部分沉入所述凹槽内并与所述引线框架电连接;
提供散热块;
对所述引线框架、所述半导体芯片和所述散热块进行塑封,
其中,所述散热块部分的被嵌入在所述塑封体内。
12.根据权利要求11所述的半导体封装方法,其中,所述散热块位于所述塑封体内的部分为倒阶梯结构,或者所述散热块位于所述塑封体内的部分的截面形状为倒T字形或矩形。
13.根据权利要求11所述的半导体封装方法,其中,所述散热块位于所述塑封体外的部分为翅片状结构,或者所述散热块位于所述塑封体外的部分的截面形状为矩形。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111548773.XA CN114883287A (zh) | 2021-12-17 | 2021-12-17 | 半导体封装结构及封装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111548773.XA CN114883287A (zh) | 2021-12-17 | 2021-12-17 | 半导体封装结构及封装方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN114883287A true CN114883287A (zh) | 2022-08-09 |
Family
ID=82666910
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202111548773.XA Pending CN114883287A (zh) | 2021-12-17 | 2021-12-17 | 半导体封装结构及封装方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN114883287A (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116685044A (zh) * | 2022-12-14 | 2023-09-01 | 荣耀终端有限公司 | 电路板组件、电池保护板和电子设备 |
CN116884932A (zh) * | 2023-09-06 | 2023-10-13 | 深圳智芯微电子科技有限公司 | 芯片封装结构 |
-
2021
- 2021-12-17 CN CN202111548773.XA patent/CN114883287A/zh active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116685044A (zh) * | 2022-12-14 | 2023-09-01 | 荣耀终端有限公司 | 电路板组件、电池保护板和电子设备 |
CN116884932A (zh) * | 2023-09-06 | 2023-10-13 | 深圳智芯微电子科技有限公司 | 芯片封装结构 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR940007757Y1 (ko) | 반도체 패키지 | |
US6590281B2 (en) | Crack-preventive semiconductor package | |
US5172214A (en) | Leadless semiconductor device and method for making the same | |
US8350369B2 (en) | High power semiconductor package | |
EP2605276B1 (en) | Packaged leadless semiconductor device | |
KR100369907B1 (ko) | 반도체 패키지와 그 반도체 패키지의 기판 실장 구조 및적층 구조 | |
JP2001077277A (ja) | 半導体パッケージおよび半導体パッケージ製造方法 | |
US8592962B2 (en) | Semiconductor device packages with protective layer and related methods | |
CN114883287A (zh) | 半导体封装结构及封装方法 | |
KR19980032479A (ko) | 표면 설치 to-220 패키지 및 그의 제조 공정 | |
US8659133B2 (en) | Etched surface mount islands in a leadframe package | |
KR19980055817A (ko) | 버텀리드 반도체 패키지 및 그 제조 방법 | |
KR101994727B1 (ko) | 전력 모듈 패키지 및 그 제조방법 | |
CN114068468A (zh) | 引线框架及封装结构 | |
KR101443970B1 (ko) | 전력 모듈 패키지 | |
CN218632028U (zh) | 半导体封装结构 | |
KR20150061441A (ko) | 패키지 기판 및 그 제조방법 및 그를 이용한 전력 모듈 패키지 | |
KR0119757Y1 (ko) | 반도체 패키지 | |
CN218160365U (zh) | 封装结构 | |
KR19980084769A (ko) | 고방열 패키지 및 그 제조방법 | |
KR100321149B1 (ko) | 칩사이즈 패키지 | |
JP5145596B2 (ja) | 半導体装置 | |
JPH07193180A (ja) | 樹脂封止型半導体装置 | |
KR100370480B1 (ko) | 반도체 패키지용 리드 프레임 | |
KR20010061847A (ko) | 열방출형 반도체 패키지 및 이 패키지가 실장된 메모리 모듈 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |