CN114883199A - 制作导电迹线的方法及所得结构 - Google Patents

制作导电迹线的方法及所得结构 Download PDF

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CN114883199A
CN114883199A CN202210498183.9A CN202210498183A CN114883199A CN 114883199 A CN114883199 A CN 114883199A CN 202210498183 A CN202210498183 A CN 202210498183A CN 114883199 A CN114883199 A CN 114883199A
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seed material
over
conductive traces
copper
conductive
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克里斯托弗·J·甘比
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本申请涉及一种制作导电迹线的方法及所得结构。一个实施例是一种形成导电迹线的方法，其包括：在衬底的表面上方形成晶种材料；在所述晶种材料上方形成经图案化掩模材料以界定沟槽，从而使所述晶种材料的位于所述沟槽内的部分被暴露；及在所述沟槽中的所述经暴露晶种材料上方沉积导电材料以形成导电迹线。移除所述经图案化掩模材料的至少一部分，在所述导电迹线的侧表面及上部表面上方形成阻挡层，且移除所述晶种材料的经暴露部分。还揭示导电迹线及并入有导电迹线的结构。

Description

制作导电迹线的方法及所得结构
分案申请信息
本发明是申请日为2018年12月12日、申请号为201811520796.8、发明名称为“制作导电迹线的方法及所得结构”的发明专利申请案的分案申请。
优先权主张
本申请案主张于2017年12月14日提出申请的美国专利申请案第15/841,660号“制作导电迹线的方法及所得结构(METHODS OF FABRICATING CONDUCTIVE TRACES ANDRESULTING STRUCTURES)”的申请日期的权益。
技术领域
本文中所揭示的实施例涉及用于制作导电迹线的方法及如此形成的导电迹线。更具体来说，本文中所揭示的实施例涉及用于制作用于高频率信号发射的导电迹线的方法及所得结构，包含(不加限制地)并入有此类导电迹线的重布层(RDL)及包含此类RDL的组合件。
背景技术
近年来，半导体工业已发展到将铜用于导电迹线，所述金属提供比先前材料(例如铝或铝合金)低的电阻及因此低的信号阻抗。已通过采用越来越高的频率信号以适应电路中的较快切换速度的工业而增强此趋势，以便将电力消耗维持处于合理水平。
与铜迹线的使用相关联的一种现象是响应于由铜迹线展现的表面饰面的所谓的“集肤效应”，所述现象在较低频率下为可忽略的但在大约1GHz及更高的频率下变得显著。随着频率增加，集肤效应将电流驱动到铜的表面中，从而随着表面饰面的粗糙度增加而急剧增加电力损失且减小信号速度。此归因于导体的有效长度随着电流沿循铜的粗糙表面形貌而增加。因此，在高频率下，铜的有效阻抗依据电流在粗糙铜表面上必须横穿的经增加距离而增加。
制作导电迹线(例如针对RDL)的常规方法涉及在衬底上沉积毯覆晶种层，后续接着沉积及图案化光致抗蚀剂、电镀铜以在光致抗蚀剂中的沟槽中形成迹线，且接着从衬底剥除光致抗蚀剂以暴露晶种层，接着将所述晶种层蚀刻。
在图1A到1E中图解说明常规制作工艺。在图1A中，衬底100具有金属沉积(举例来说，如通过物理气相沉积(即，溅镀))的晶种层102，以用作粘合层且用作用于其上的金属的后续电镀的电极。在图1B中，在晶种层102上沉积一层光致抗蚀剂104，此后将光致抗蚀剂图案化、显影且将光致抗蚀剂104的部分移除以形成沟槽106。在图1C中，在晶种层102的被暴露于沟槽106中的部分上方电镀铜以形成导电迹线108。接着将光致抗蚀剂104移除，从而暴露导电迹线108，所述导电迹线因电镀工艺而展现平滑表面，如图1D中所展示。然而，还如图1D中所展示，晶种层102的先前由经图案化光致抗蚀剂104覆盖的部分现在被暴露，从而需要进行移除以避免邻近导电迹线108之间的电短路。当通过湿法蚀刻而移除晶种层102(如图1E中所展示)时，经电镀导电迹线108的表面也被蚀刻，从而导致粗糙表面R、增加导电迹线阻抗。因此，高频率信号发射由于集肤效应而受损，从而导致信号损失且需要额外电力来维持信号速度。
发明内容
一种形成导电迹线的方法包括：在衬底的表面上方形成晶种材料；在所述晶种材料上方形成经图案化掩模材料以界定沟槽，从而使所述晶种材料的位于所述沟槽内的部分被暴露；及在所述沟槽中的所述经暴露晶种材料上方沉积导电材料以形成导电迹线。移除所述经图案化掩模材料的至少一部分。在所述导电迹线的侧表面及上部表面上方形成阻挡层，且移除所述晶种材料的经暴露部分。
一种形成导电迹线的方法包括：在衬底的表面上方形成铜晶种材料；在所述铜晶种材料上方形成及图案化正型光致抗蚀剂材料以界定延伸到所述铜晶种材料的沟槽；在所述沟槽中的经暴露铜晶种材料上方电化学沉积铜以形成导电迹线；及蚀刻所述经图案化正型光致抗蚀剂材料以至少从所述光致抗蚀剂材料的邻近所述导电迹线的侧表面的侧表面移除一定深度的所述光致抗蚀剂材料以使所述光致抗蚀剂材料相对于所述导电迹线的侧表面凹陷。在所述光致抗蚀剂材料的所述侧表面与所述导电迹线的所述邻近侧表面之间且在所述导电迹线的上部表面上方电化学沉积金属阻挡层。剥除剩余正型光致抗蚀剂材料以暴露所述铜晶种材料的部分，且蚀刻所述铜晶种材料的所述经暴露部分。
一种结构包括：导电迹线，其通过介电材料而相互电隔离。所述导电迹线被配置有矩形横截面，且包括铜芯，且所述铜芯的侧表面及所述铜芯的延伸于所述侧表面之间的表面被覆盖有金属阻挡层。
附图说明
图1A到1E示意性地描绘用于在衬底上制作导电迹线的常规工艺流程；
图2A到2G示意性地描绘根据本发明的实施例的用于在衬底上制作导电迹线的工艺流程；
图3A到3D示意性地描绘根据本发明的其它实施例的用于在衬底上制作导电迹线的工艺流程；
图4A是根据本发明的实施例形成的导电迹线的示意性俯视立面图；
图4B是根据本发明的实施例形成的导电迹线的示意性侧视立面图；
图4C是根据本发明的实施例形成的RDL的层级的导电迹线的示意性透视图；且
图4D是包含根据本发明的实施例形成的导电迹线的多个层级的RDL的侧视示意性部分横截面立面图。
具体实施方式
本发明的实施例包括形成展现平滑表面饰面的导电迹线的方法。在发射高频率信号时，如此形成的导电迹线大体上消除集肤效应且展现经减小阻抗，从而增强信号发射速度而不增加电力需求。
以下描述提供特定细节(例如大小、形状、材料组成及定向)，以便提供对本发明的实施例的透彻描述。然而，所属领域的技术人员将理解，可在无需采用这些特定细节的情况下实践本发明的实施例。本发明的实施例可连同工业中所采用的常规制作技术一起实践。另外，下文所提供的描述并不形成用于制造RDL或包含导电迹线的其它电子结构(例如包含导电迹线的结构，或包含并入有导电迹线的结构的组合件)的完整工艺流程。下文仅详细地描述用于理解本发明的实施例所必需的那些工艺动作及结构。如本文中所描述，用以形成包含导电迹线的完整结构或包含并入有导电迹线的结构的完整组合件的额外动作可通过常规制作工艺而执行。
本文中所呈现的图式仅为出于说明性目的，且并不意指为任何特定材料、组件、结构、装置或系统的实际视图。预期所描绘的形状会由于(举例来说)制造技术及/或公差而有所变化。因此，本文中所描述的实施例不应视为限制于如所图解说明的特定形状或区域，而是包含因(举例来说)制造而引起的形状偏差。举例来说，被图解说明或描述为方框形状的区域可具有粗糙及/或非线性特征，且被图解说明或描述为圆形的区域可包含一些粗糙及/或线性特征。此外，所图解说明的表面之间的锐角可被修圆，且反之亦然。因此，图中所图解说明的区域本质上为示意性的，且其形状并非打算图解说明区域的精确形状且并非打算限制本权利要求书的范围。所述图式未必按比例绘制。
如本文中所使用，术语“包括”、“包含”、“含有”、“由…表征”及其语法等效内容为包含性或开放式术语，所述包含性或开放式术语不排除额外未经陈述元件或方法动作，但还包含较限制性术语“由…组成”、“基本上由…组成”及其语法等效内容。如本文中所使用，关于材料、结构、特征或方法动作的术语“可(may)”指示此材料、结构、特征或方法动作预期用于实施本发明的实施例，且此术语优先于较限制性术语“是(is)”而使用以便避免对于应该或必须排除可与此材料、结构、特征或方法动作组合使用的其它兼容材料、结构、特征及方法的任何暗示。
如本文中所使用，术语“纵向”、“垂直”、“横向”及“水平”是参考其中或其上形成一或多个结构及/或特征的衬底(例如，基底材料、基底结构、基底构造等)的主平面，且未必是由地球的引力场界定。“横向”或“水平”方向是大体上平行于衬底的主平面的方向，而“纵向”或“垂直”方向是大体上垂直于衬底的主平面的方向。衬底的主平面由衬底的具有与衬底的其它表面相比相对大面积的表面界定。
如本文中所使用，为便于描述，可使用空间相对术语(例如“底下”、“下面”、“下部”、“底部”、“上面”、“上方”、“上部”、“顶部”、“前”、“后”、“左”、“右”等等)来描述一个元件或特征与另一元件或特征的关系，如各图中所图解说明。除非另有规定，否则除图中所描绘的定向之外，所述空间相关术语还打算囊括材料的不同定向。举例来说，如果颠倒各图中的材料，那么描述为在其它元件或特征“上方”或“上面”或“上”或者“顶部上”的元件则将定向为在其它元件或特征“下面”或“底下”或“下方”或者“底部上”。因此，术语“上方”可囊括对所属领域的技术人员将为明显的上面及下面的定向两者(此取决于使用所述术语的上下文)。可以其它方式(例如，旋转90度、反转、翻转等)定向材料且据此解释本文中所使用的空间相对描述语。
如本文中所使用，单数形式“一(a、an)”及“所述(the)”也打算包含复数形式，除非上下文另有明确指示。
如本文中所使用，术语“配置(configured及configuration)”是指促进以预定方式操作结构及设备中的一或多者的至少一个结构及至少一个设备中的一或多者的大小、形状、材料组成、定向及布置。
如本文中所使用，参考给定参数、性质或条件的术语“大体上”意指且包含达到所属领域的技术人员将理解的以变化程度(例如在可接受制造公差内)满足给定参数、性质或条件的程度。通过实例方式，取决于大体上满足的特定参数、性质或条件，所述参数、性质或条件可得到至少90.0％满足、至少95.0％满足、至少99.0％满足或甚至至少99.9％满足。
如本文中所使用，参考给定参数的术语“约”包含所陈述值且具有由上下文指定的含义(例如，其包含与给定参数的测量相关联的误差程度)。
如本文中所使用，如应用于表征导电迹线的表面饰面的术语“平滑”意指且包含展现不超过约2纳米(nm)RMS的形貌变化(如使用原子力显微镜所测量)的表面饰面。换句话说，平滑表面将向观察者展现镜面饰面。
如本文中所使用，术语“层”意指且包含驻留在结构上的材料的层级、膜或涂层，除非另有指示，否则所述层级可在材料的部分之间为连续或不连续的，且所述层级可为保形或非保形的。
参考图2A到2G，将描述根据本发明的实施例的用于形成导电迹线的工艺流程。
参考图2A，衬底200可包括电介质，所述电介质放置于现有结构(举例来说，半导体结构(例如，晶片、晶片分段或半导体裸片))上方、半导体结构上、陶瓷、玻璃或另一载体衬底上。举例来说，在一些实施例中，衬底200可包括半导体裸片(例如，存储器裸片)的阵列且将形成于所述阵列上的迹线将包括与每一裸片相关联的RDL的部分。在其它实施例中，衬底可包括牺牲衬底，多个RDL在所述牺牲衬底上形成且随后被单粒化及移除以供用于制作(举例来说)扇出封装(FOP)组合件。衬底200具有晶种材料202，所述晶种材料可被表征为沉积于其上(举例来说，如通过物理气相沉积，还称作“溅镀”)的一或多种金属的层。在一个实施例中，衬底200可包括承载有机聚合物的玻璃晶片，所述有机聚合物经配制以用于一或若干结构的后续释放(通过经由所述玻璃暴露于激光)，所述一或若干结构承载形成于其上的导电迹线。晶种材料202可包括单个铜层或可为双层且包括(举例来说)第一经沉积钛层、后续接着第二铜层。钛可用以增强待形成的导电迹线以及阻挡层相对于衬底200的粘合性。晶种材料202可形成为(举例来说)约
Figure BDA0003633710200000051
Figure BDA0003633710200000052
的厚度。
参考图2B，在晶种材料202上沉积(举例来说，通过旋涂或喷涂)一层掩模材料(举例来说，正型或负型光致抗蚀剂204)。在一个实施例中，采用正型光致抗蚀剂，由于(与负型光致抗蚀剂相比)阶梯覆盖性(step coverage)为优越的，因此可实现较小特征大小且可采用水性显影剂基底。光致抗蚀剂204通过常规技术而以光学光刻方式图案化及显影，且光致抗蚀剂204的未显影部分经移除以形成暴露晶种材料202的部分的沟槽206。
参考图2C，在晶种材料202中的铜的被暴露于沟槽206中的部分上方电镀元素铜(所述工艺还在此项技术中被表征为电化学沉积(ECD))以形成导电迹线208，所述导电迹线还可被表征为展现平滑侧表面210及上部表面212的迹线芯。仅通过实例方式，导电迹线208可具有约2μm的高度，且具有从约2μm到约100μm的宽度，接近所述范围的上端的宽度更适合于电力发射。如所形成，侧表面210及上部表面212展现不超过约2纳米(nm)RMS的形貌变化。以另一方式表征，所述表面展现镜面饰面。
参考图2D，将光致抗蚀剂204的剩余部分干法(即，反应性离子)蚀刻以从其侧表面214及上部表面216移除一定深度的光致抗蚀剂材料，从而附带地减小光致抗蚀剂204的高度，但在导电迹线208的侧表面210与光致抗蚀剂204的邻近侧表面214之间较显著地形成间隙218。在一些实施例中，间隙218的宽度W可介于约0.25μm与约2μm之间。考虑到间隙218的纵横比，所述间隙必须为充分宽的，以使所采用的电沉积工具确保在工艺中所使用的电解质将到达间隙218的底部。换句话说，蚀刻使光致抗蚀剂204相对于导电迹线208而凹陷。
参考图2E，在间隙218中且在导电迹线208的上部表面212上方沉积另一金属(举例来说，镍或金)以在导电迹线208的侧表面210及上部表面212上方形成蚀刻阻挡层220，蚀刻阻挡层220向下延伸到晶种材料202。用于蚀刻阻挡层220的其它适合材料包含(举例来说)钽、钴、铟、TiN、钒及前述各项中的任何者的组合。针对适合于阻挡层220的材料的主要准则是蚀刻剂相对于移除阻挡层220的材料上方的那些材料对移除晶种材料具有选择性。除了保护导电迹线208免受蚀刻剂之外，蚀刻阻挡层220还可用作互连件冶金的基底。举例来说，金或镍可用作用于在其上方后续形成兼容金属的互连件或者形成焊料球的凸块下金属(UBM)的适合冶金。替代地，如果期望或需要与互连件或外部连接具有冶金兼容性，那么可选择性地掩蔽导电迹线208的上部表面212且在阻挡层220上于选定位置处电镀另一金属。
参考图2F，可如常规地剥除光致抗蚀剂204以暴露导电迹线之间的晶种材料202。
参考图2G，接着湿法(化学)蚀刻导电迹线208之间的晶种材料202以将导电迹线208彼此电隔离。所采用的蚀刻剂相对于蚀刻阻挡层220的金属对晶种材料202的一或若干金属具有选择性，此保留且保护导电迹线208的平滑侧表面210及上部表面212，从而显著减少前述集肤效应的任何不利后果且保持信号发射速度而无需增加电力。如果采用铜与钛或用于粘合到衬底的另一金属的双层，那么采用不同蚀刻剂，每一蚀刻剂分别相对于铜对铜与钛(或其它金属)具有选择性。迹线208的底侧222也呈现未被蚀刻的平滑表面。如图2G中所展示，晶种材料202的蚀刻可导致蚀刻阻挡层220下面的侧表面210的底部处的轻微底切；然而，考虑到相对薄晶种材料202，底切(为了在图式的图中清晰起见而被放大)对于导电迹线208或紧接在其下方的晶种材料202的剩余分段不具有显著不利影响。
在另一实施例中，工艺流程与图2A到2C中的先前实施例的工艺流程相同。然而，在形成导电迹线208之后，剥除光致抗蚀剂204，且可在衬底200上方沉积第二光致抗蚀剂204′、将所述第二光致抗蚀剂图案化及显影(如图3A中所展示)以在迹线208的侧表面210与光致抗蚀剂204′的位于每一迹线208侧面的部分的邻近侧表面214′之间提供具有适合宽度W的间隙218。光致抗蚀剂204′可为与光致抗蚀剂204相同的类型(正型或负型)，且具有相同或不同组成。
如图3B中所展示，在间隙218中且在导电迹线208的上部表面212上方沉积另一金属(举例来说，镍或金)以在导电迹线208的侧表面210及上部表面212上方形成蚀刻阻挡层220，蚀刻阻挡层220向下延伸到晶种材料202。用于蚀刻阻挡层220的其它适合材料包含(举例来说)钽、钴、铟、TiN、钒及前述各项中的任何者的组合。如先前所述，除了保护导电迹线208免受蚀刻剂之外，蚀刻阻挡层220还可用作互连件或其它电连接结构冶金的基底。举例来说，金或镍可用作用于在其上方后续形成兼容金属的互连件或者形成焊料球的凸块下金属(UBM)的适合冶金。替代地，如果期望或需要与互连件或外部连接具有冶金兼容性，那么可选择性地掩蔽导电迹线208的上部表面212且在阻挡层220上于选定位置处电镀另一金属(例如，另一金属223)。为简洁及清晰起见，仅在图3B中描绘另一金属(例如，另一金属223)。
如图3C中所展示，可如常规地剥除光致抗蚀剂204′以暴露导电迹线208之间的晶种材料202。
如图3D中所展示，接着湿法蚀刻导电迹线208之间的晶种材料202以将导电迹线208彼此电隔离。所采用的蚀刻剂相对于蚀刻阻挡层220的金属对晶种材料202的一或若干金属具有选择性，此保留且保护导电迹线208的平滑侧表面210及上部表面212，从而显著减少前述集肤效应的任何不利后果且保持信号发射速度而无需增加电力。迹线208的底侧222也呈现未被蚀刻的平滑表面。如图3D中所展示，晶种材料202的蚀刻可导致蚀刻阻挡层220下面的侧表面210的底部处的轻微底切；然而，考虑到相对薄晶种材料202，底切(为了在图式的图中清晰起见而被放大)对于导电迹线208或紧接在其下方的晶种材料202的剩余分段不具有显著不利影响。
图4A是根据本发明的实施例的形成于衬底200上的导电迹线208的一部分的示意性俯视立面图。以虚线描绘位于导电迹线的侧表面210上的蚀刻阻挡层220以及覆盖上部表面212的阻挡层220。
图4B是根据本发明的实施例的形成于衬底200上的导电迹线208的一部分的示意性侧视立面图。以虚线描绘位于导电迹线208的上部表面212上的阻挡层220以及覆盖侧表面210(展示一个)的阻挡层220。
图4C是RDL 300的导电迹线208的示意性透视图，迹线208通过介电材料302(举例来说，聚酰亚胺)而相互电隔离。阻挡层220覆盖迹线208的侧表面210及上部表面212。
图4D是根据本发明的实施例的包含RDL 300的结构的示意性侧视立面图，所述RDL包含导电迹线208的多个层级，每一导电迹线具有由阻挡层覆盖的侧表面及上部表面。迹线208通过电介质302而相互电隔离，各种迹线层级通过互连件304而电连接，其它互连件306经定位以在RDL 300的一侧上连接到半导体裸片400，且仍其它互连件包括UBM 308，所述UBM具有呈放置于其上的焊料凸块310的形式的导电元件以用于将半导体裸片400连接到较高层级封装402。
本发明的实施例包含一种形成导电迹线的方法，其包括：在衬底的表面上方形成晶种材料；在所述晶种材料上方形成经图案化掩模材料以界定沟槽，从而使所述晶种材料的位于所述沟槽内的部分被暴露；在所述沟槽中的所述经暴露晶种材料上方沉积导电材料以形成导电迹线；移除所述经图案化掩模材料的至少一部分；在所述导电迹线的侧表面及上部表面上方形成阻挡层；及移除所述晶种材料的经暴露部分。
本发明的实施例还包含一种进行以下操作的方法：在衬底的表面上方形成铜晶种材料；在所述铜晶种材料上方形成及图案化正型光致抗蚀剂材料以界定延伸到所述铜晶种材料的沟槽；在所述沟槽中的经暴露铜晶种材料上方电化学沉积铜以形成导电迹线；蚀刻所述经图案化正型光致抗蚀剂材料以至少从所述光致抗蚀剂材料的邻近所述导电迹线的侧表面的侧表面移除一定深度的所述光致抗蚀剂材料以使所述光致抗蚀剂材料相对于所述导电迹线的侧表面凹陷；在所述光致抗蚀剂材料的所述侧表面与所述导电迹线的所述邻近侧表面之间且在所述导电迹线的上部表面上方电化学沉积金属阻挡层；剥除剩余正型光致抗蚀剂材料以暴露所述晶种材料的部分；及蚀刻所述晶种材料的所述经暴露部分。本发明的实施例进一步包含一种结构，其包括：导电迹线，其通过介电材料而相互电隔离；其中所述导电迹线被配置有矩形横截面、包括铜芯，且所述铜芯的侧表面及所述铜芯的延伸于所述侧表面之间的表面被覆盖有金属阻挡层。
尽管已结合各图描述特定说明性实施例，但所属领域的技术人员将认识到并了解，由本发明囊括的实施例不限于本文中明确展示及描述的那些实施例。而是，可在不背离由本发明囊括的实施例的范围的情况下做出对本文中所描述的实施例的许多添加、删除及修改，例如后文中所主张的那些内容，包含合法等效内容。另外，来自一个所揭示实施例的特征可与另一所揭示实施例的特征组合，同时仍囊括于本发明的范围内。

Claims (25)

1.一种形成导电迹线的方法，所述方法包括：
形成延伸于衬底的平面表面的一部分上方的晶种材料；
在所述晶种材料上方形成经图案化掩模材料以界定沟槽，从而使所述晶种材料的位于所述沟槽内的部分被暴露；
在所述沟槽中的所述经暴露晶种材料上方沉积导电材料以形成导电迹线；
通过干法蚀刻工艺移除所述经图案化掩模材料的至少一部分以在所述经图案化掩模材料与所述导电迹线之间形成间隙；
在移除所述经图案化掩模材料的所述至少一部分之后，在所述导电迹线的侧表面及上部表面上方直接形成阻挡层以完全填充所述间隙；
在形成所述阻挡层之后，移除所述经图案化掩模材料的剩余部分；及
移除所述晶种材料的经暴露部分。
2.根据权利要求1所述的方法，其中：
移除所述经图案化掩模材料的至少一部分包括：至少从所述经图案化掩模材料的邻近所述导电迹线的侧表面的侧表面移除一定深度的所述经图案化掩模材料，以在所述经图案化掩模材料与所述导电迹线之间形成所述间隙；及
形成阻挡层包括：在邻近所述侧表面的所述间隙中且在所述导电迹线的上部表面上方形成阻挡层。
3.根据权利要求1所述的方法，其中在衬底的表面上方形成晶种材料包括：通过物理气相沉积而形成所述晶种材料铜的至少一部分。
4.根据权利要求3所述的方法，其中在所述沟槽中的所述经暴露晶种材料上方沉积导电材料以形成导电迹线包括：在所述沟槽中电镀铜。
5.根据权利要求4所述的方法，其中在所述沟槽中电镀铜包括：将所述导电迹线形成为展现所述侧表面及所述上部表面的不超过约2纳米(nm)RMS的形貌变化。
6.根据权利要求5所述的方法，其中在所述导电迹线的侧表面及上部表面上方形成阻挡层包括：在所述侧表面及上部表面上方电镀镍、金、钽、钴、铟、TiN、钒或其组合。
7.根据权利要求6所述的方法，其进一步包括仅在所述导电迹线的所述上部表面中的至少一者的一部分上方电镀另一金属。
8.根据权利要求3所述的方法，其中形成晶种材料进一步包括：在于钛上方形成所述晶种材料铜的所述至少一部分之前通过物理气相沉积而形成钛。
9.根据权利要求1所述的方法，其中在所述晶种材料上方形成及图案化掩模材料包括：形成及图案化光致抗蚀剂材料。
10.根据权利要求1所述的方法，其中移除所述晶种材料的经暴露部分包括：利用相对于所述阻挡层的材料对所述晶种材料的一或多种材料具有选择性的一或多种蚀刻剂来蚀刻所述晶种材料的所述经暴露部分。
11.一种形成导电迹线的方法，所述方法包括：
在衬底的表面上方形成铜晶种材料；
在所述铜晶种材料上方形成及图案化正型光致抗蚀剂材料以界定延伸到所述铜晶种材料的沟槽；
在所述沟槽中的经暴露铜晶种材料上方电化学沉积铜以形成导电迹线；
干法蚀刻所述经图案化正型光致抗蚀剂材料以至少从所述正型光致抗蚀剂材料的邻近所述导电迹线的侧表面的侧表面移除一定深度的所述正型光致抗蚀剂材料以使所述正型光致抗蚀剂材料相对于所述导电迹线的侧表面凹陷；
在所述光致抗蚀剂材料的所述侧表面与所述导电迹线的所述邻近侧表面之间且在所述导电迹线的上部表面上方电化学直接沉积金属阻挡层；
剥除剩余正型光致抗蚀剂材料以暴露所述铜晶种材料的部分；及
蚀刻所述铜晶种材料的所述经暴露部分。
12.根据权利要求11所述的方法，其中电化学沉积金属阻挡层包括：电化学沉积镍、金、钽、钴、铟、TiN、钒或其组合。
13.根据权利要求11所述的方法，其中蚀刻所述经图案化正型光致抗蚀剂材料包括反应性离子蚀刻。
14.根据权利要求11所述的方法，其中在所述沟槽中电化学沉积铜包括：将所述导电迹线形成为展现所述侧表面及所述上部表面的不超过约2纳米(nm)RMS的形貌变化。
15.一种通过权利要求1-14中任一项所述的方法形成的结构，其包括：
在晶种材料上的导电迹线；
其中所述导电迹线被配置有矩形横截面，且包括铜芯，且所述铜芯的侧表面及所述铜芯的延伸于所述侧表面之间的第一表面被覆盖有金属阻挡层，其中沿着所述铜芯的所述侧表面延伸的所述金属阻挡层在所述铜芯的延伸于所述侧表面之间且与所述第一表面相对的第二表面处停止，且所述铜芯展现不超过约2纳米(nm)RMS的所述侧表面的形貌变化。
16.根据权利要求15所述的结构，其中所述金属阻挡层包括镍、金、钽、钴、铟、TiN、钒或其组合。
17.根据权利要求15所述的结构，其进一步包括：
重布层RDL，所述RDL包括所述导电迹线及所述导电迹线之间的介电材料，以及
至少一个半导体裸片，所述至少一个半导体裸片在所述RDL的一侧上电连接到所述导电迹线中的至少一些导电迹线。
18.根据权利要求17述的结构，其进一步包括导电元件，所述导电元件在所述RDL的与所述至少一个半导体裸片相对的一侧上电连接到所述导电迹线中的至少一些导电迹线。
19.根据权利要求15所述的结构，其中所述晶种材料的横向宽度小于所述铜芯的横向宽度。
20.一种结构，其包括：
导电迹线，其定位于衬底上方；
晶种材料，其位于所述导电迹线与所述衬底之间；
其中所述导电迹线包括配置有矩形横截面的铜芯，所述导电迹线具有光滑侧表面和光滑上表面，所述光滑侧表面具有镜面抛光，所述光滑上表面具有镜面抛光且在所述侧表面之间延伸，且所述晶种材料具有小于所述导电迹线的宽度的宽度；以及
金属阻挡层，其在所述上表面上方且沿着所述铜芯的所述侧表面延伸，且停止在所述铜芯的下表面的在所述侧表面之间延伸且与所述第一表面相对的水平面上。
21.根据权利要求20所述的结构，其中所述金属阻挡层包括镍、金、钽、钴、铟、TiN、钒或其组合。
22.根据权利要求20所述的结构，其中所述铜芯的所述平滑上表面和所述平滑侧表面展现不超过约2纳米(nm)RMS的形貌变化。
23.根据权利要求20所述的结构，其中所述导电迹线和介电材料包括重布层RDL，且进一步包括至少一个半导体裸片，所述至少一个半导体裸片在所述RDL的一侧上电连接到所述导电迹线中的至少一些导电迹线。
24.根据权利要求23所述的结构，其进一步包括导电元件，所述导电元件在所述RDL的与所述至少一个半导体裸片相对的一侧上电连接到所述导电迹线中的至少一些导电迹线。
25.根据权利要求20所述的结构，其中所述晶种材料从所述铜芯的所述侧表面横向凹陷。
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US10811313B2 (en) 2020-10-20
US10332792B1 (en) 2019-06-25
US20190189507A1 (en) 2019-06-20
CN110021580A (zh) 2019-07-16

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