CN1147932C - 半导体存储器 - Google Patents
半导体存储器Info
- Publication number
- CN1147932C CN1147932C CNB981035485A CN98103548A CN1147932C CN 1147932 C CN1147932 C CN 1147932C CN B981035485 A CNB981035485 A CN B981035485A CN 98103548 A CN98103548 A CN 98103548A CN 1147932 C CN1147932 C CN 1147932C
- Authority
- CN
- China
- Prior art keywords
- function pin
- electrode pad
- memory chip
- center line
- assigned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/0554—External layer
- H01L2224/05599—Material
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/1517—Multilayer substrate
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- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Wire Bonding (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (11)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP227394/1997 | 1997-08-08 | ||
JP227394/97 | 1997-08-08 | ||
JP9227394A JP2943781B2 (ja) | 1997-08-08 | 1997-08-08 | 半導体メモリ |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1208962A CN1208962A (zh) | 1999-02-24 |
CN1147932C true CN1147932C (zh) | 2004-04-28 |
Family
ID=16860144
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB981035485A Expired - Fee Related CN1147932C (zh) | 1997-08-08 | 1998-08-07 | 半导体存储器 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5991185A (zh) |
JP (1) | JP2943781B2 (zh) |
CN (1) | CN1147932C (zh) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6285558B1 (en) * | 1998-09-25 | 2001-09-04 | Intelect Communications, Inc. | Microprocessor subsystem module for PCB bottom-side BGA installation |
JP2003174111A (ja) * | 2001-12-06 | 2003-06-20 | Sanyo Electric Co Ltd | 半導体装置 |
US8222721B2 (en) * | 2003-09-15 | 2012-07-17 | Silicon Laboratories Inc. | Integrated circuit suitable for use in radio receivers |
US7820485B2 (en) * | 2008-09-29 | 2010-10-26 | Freescale Semiconductor, Inc. | Method of forming a package with exposed component surfaces |
US8415203B2 (en) * | 2008-09-29 | 2013-04-09 | Freescale Semiconductor, Inc. | Method of forming a semiconductor package including two devices |
JP2011066298A (ja) * | 2009-09-18 | 2011-03-31 | Renesas Electronics Corp | 半導体チップ、及びこれを備えた半導体装置 |
JP2012114241A (ja) | 2010-11-25 | 2012-06-14 | Renesas Electronics Corp | 半導体チップおよび半導体装置 |
KR102354986B1 (ko) | 2015-07-08 | 2022-01-24 | 삼성전자주식회사 | 솔리드 스테이트 드라이브 |
CN107049730B (zh) * | 2015-09-04 | 2019-08-20 | 王秀贞 | 一种连体按压催乳按摩器械 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0815167B2 (ja) * | 1986-03-26 | 1996-02-14 | 株式会社日立製作所 | 半導体装置 |
JP2633249B2 (ja) * | 1987-04-27 | 1997-07-23 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
US5019889A (en) * | 1988-06-29 | 1991-05-28 | Hitachi, Ltd. | Semiconductor integrated circuit device |
US5300796A (en) * | 1988-06-29 | 1994-04-05 | Hitachi, Ltd. | Semiconductor device having an internal cell array region and a peripheral region surrounding the internal cell array for providing input/output basic cells |
JP2925337B2 (ja) * | 1990-12-27 | 1999-07-28 | 株式会社東芝 | 半導体装置 |
JP2888755B2 (ja) * | 1994-04-28 | 1999-05-10 | 株式会社メガチップス | 半導体装置 |
-
1997
- 1997-08-08 JP JP9227394A patent/JP2943781B2/ja not_active Expired - Fee Related
-
1998
- 1998-08-06 US US09/129,894 patent/US5991185A/en not_active Expired - Lifetime
- 1998-08-07 CN CNB981035485A patent/CN1147932C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1208962A (zh) | 1999-02-24 |
JPH1167817A (ja) | 1999-03-09 |
US5991185A (en) | 1999-11-23 |
JP2943781B2 (ja) | 1999-08-30 |
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