CN114696863A - 高频模块 - Google Patents
高频模块 Download PDFInfo
- Publication number
- CN114696863A CN114696863A CN202111508545.XA CN202111508545A CN114696863A CN 114696863 A CN114696863 A CN 114696863A CN 202111508545 A CN202111508545 A CN 202111508545A CN 114696863 A CN114696863 A CN 114696863A
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- China
- Prior art keywords
- semiconductor device
- output matching
- matching circuit
- circuit
- frequency
- Prior art date
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- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
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Abstract
本发明提供一种高频模块,能够抑制信号传输损耗的增大,并且提高从半导体装置的散热特性。在模块基板安装有包含高频放大电路和频带选择开关的半导体装置。连接在高频放大电路与频带选择开关之间的输出匹配电路设置于模块基板。半导体装置包含:第一部件,形成有包含元素半导体系的半导体元件的频带选择开关;和第二部件,与第一部件面接触地接合,并形成有包含化合物半导体系的半导体元件的高频放大电路。从第一部件以及第二部件突出多个导体突起。半导体装置经由多个导体突起安装于模块基板,在俯视时,半导体装置配置在输出匹配电路的附近,或者半导体装置和构成输出匹配电路的无源元件重叠。
Description
技术领域
本发明涉及高频模块。
背景技术
在用于移动通信、卫星通信等的电子设备中组装有将高频信号的收发功能一体化的RF前端模块。RF前端模块具备:具有高频放大功能的单片微波集成电路元件(MMIC)、控制高频放大电路的控制IC、开关IC、双工器等。
在下述的专利文献1中公开了通过在MMIC上堆叠控制IC而小型化的高频模块。专利文献1所公开的高频模块包含搭载在模块基板上的MMIC、和堆叠于MMIC上的控制IC。MMIC的电极、控制IC的电极以及模块基板上的电极通过引线接合而电连接。
专利文献1:美国专利申请公开第2015/0303971号说明书
在高频放大电路中例如使用异质结双极晶体管(HBT)。HBT在动作中产生集电极损耗而发热。发热引起的HBT的温度上升作用于使集电极电流进一步增大的方向。若满足该正反馈的条件,则导致HBT热失控。为了避免HBT的热失控,而限制HBT的输出功率的上限值。
发明内容
为了实现高频放大电路的高输出化,优选提高从包含HBT等的半导体装置的散热特性。在专利文献1所公开的高频模块中,难以满足近年来对高频放大电路的高输出化的要求。另外,若动作频率变高,则信号传输中的损耗容易变大。本发明的目的在于提供一种能够抑制信号传输损耗的增大且提高从半导体装置的散热特性的高频模块。
根据本发明的一个观点,提供高频模块,具备:
模块基板;
半导体装置,安装于上述模块基板,并包含高频放大电路和频带选择开关;以及
输出匹配电路,设置于上述模块基板,并连接在上述高频放大电路与上述频带选择开关之间,
上述频带选择开关使输入的高频信号从多个接点中所选择的一个接点输出,
上述半导体装置包含:
第一部件,包含上述频带选择开关,上述频带选择开关包含元素半导体系的半导体元件;
第二部件,与上述第一部件面接触地接合,并包含上述高频放大电路,上述高频放大电路包含化合物半导体系的半导体元件;以及
多个导体突起,配置于在俯视时包含在上述第一部件以及上述第二部件的每个部件中的位置,
上述半导体装置通过使上述第二部件与上述模块基板对置,并经由上述多个导体突起而安装于上述模块基板,
在俯视时,上述半导体装置配置在上述输出匹配电路的附近,或者上述半导体装置和构成上述输出匹配电路的至少一个无源元件重叠。
由于将形成有高频放大电路的第二部件与形成有频带选择开关的第一部件接合,因此与将高频放大电路和频带选择开关分别安装于模块基板的结构相比,能够实现小型化。由于形成从高频放大电路所包含的半导体元件朝向第一部件的传热路径和经由导体突起到达模块基板的传热路径这两个传热路径,因此能够提高从高频放大电路所包含的半导体元件的散热特性。
在俯视时,在输出匹配电路所包含的无源元件与半导体装置之间未搭载构成输出匹配电路的构件以外的电路部件,或者构成输出匹配电路的无源元件和半导体装置重叠,因此能够使半导体装置和输出匹配电路的距离接近。因此,能够使从设置于半导体装置的高频放大电路及频带选择开关的各个到输出匹配电路的距离接近。从高频放大电路到输出匹配电路的传输线路以及从输出匹配电路到频带选择开关的传输线路变短,因此能够减少传输损耗。
附图说明
图1A是表示根据第一实施例的高频模块的各构成要素的俯视时的位置关系的图,图1B是示意性地表示高频模块的截面构造的图。
图2是表示根据第一实施例的高频模块的电路结构的框图。
图3A是构成形成于根据第一实施例的高频的第二部件的功率级放大电路(图2)的一个单元的等效电路图,图3B是构成形成于第二部件的功率级放大电路的一个单元的剖视图。
图4A~图4F的附图是制造中途阶段的半导体装置的剖视图。
图5A~图5C的附图是制造中途阶段的半导体装置的剖视图,图5D是完成的半导体装置的剖视图。
图6A是表示根据第二实施例的高频模块的各构成要素的俯视时的位置关系的图,图6B是示意性地表示高频模块的截面构造的图。
图7A是表示根据第二实施例的高频模块的输出匹配电路的一个例子的等效电路图,图7B是表示输出匹配电路的构成要素的平面配置的一个例子的图。
图8A是表示根据第三实施例的高频模块的输出匹配电路的一个例子的等效电路图,图8B是表示输出匹配电路的构成要素的平面配置的一个例子的图。
图9A以及图9B分别是示意性地表示根据第四实施例以及第四实施例的变形例的高频模块的截面构造的图。
图10是示意性地表示根据第五实施例的高频模块的截面构造的图。
附图标记说明
20…高频模块;21…模块基板;21A…第一面;21B…第二面;22…布线;24…输出匹配电路与半导体装置之间的区域;25、26…模制树脂;27…导体柱;30…半导体装置;31…第一部件;32…第二部件;35…导体突起;36…部件间连接布线;37…焊盘;41…频带选择开关;42…第一控制电路;43…输入开关;50…高频放大电路;51…驱动级放大电路;52…功率级放大电路;60…输出匹配电路;61…电感器;62…电容器;65…焊料凸块;70…双工器;71…低噪声放大器;72…天线开关;73…频带选择开关;74…输出端子选择开关;75…第二控制电路;80…层间绝缘膜;81…保护膜;81A…开口;83…焊料;200…母基板;201…剥离层;202…元件形成层;204…连结支承体;210…基板;401…基底半导体层;401A…导电区域;401B…元件分离区域;402…晶体管;402B…基极层;402C…集电极层;402E…发射极层;403B…基极电极;403C…集电极;403E…发射极电极;404B…基极布线;404BB…基极偏置布线;404C…集电极布线;404E…发射极布线;405E…发射极布线;405RF…高频信号输入布线;406、407、408…层间绝缘膜。
具体实施方式
[第一实施例]
参照图1A~图5D的附图,对根据第一实施例的高频模块进行说明。
图1A是表示根据第一实施例的高频模块20的各构成要素的俯视时的位置关系的图,图1B是示意性地表示高频模块20的截面构造的图。在模块基板21安装有半导体装置30、输出匹配电路60、多个双工器70、低噪声放大器71、天线开关72以及其它表面安装型的多个无源元件(表面安装型构件(SMD))。半导体装置30包含第一部件31、和与第一部件31面接触地接合的第二部件32。例如,第一部件31由元素半导体系构成,第二部件32由化合物半导体构成。
在第一部件31设置有频带选择开关41、第一控制电路42以及输入开关43。第一部件31包含元素半导体系的半导体基板、例如硅基板或绝缘体上硅(SOI)基板,频带选择开关41、第一控制电路42以及输入开关43由在半导体基板的表层部形成的元素半导体系的半导体元件等构成。
在第二部件32设置有高频放大电路50。第二部件32包含由化合物半导体例如GaAs构成的基底半导体层、和配置于该基底半导体层上的由化合物半导体构成的半导体元件例如异质结双极晶体管(HBT)等。高频放大电路50由半导体元件等构成,该半导体元件由化合物半导体构成。
输出匹配电路60包含电感器以及电容器等多个无源元件,由集成型无源设备(IPD)构成。此外,也可以组合多个表面安装型的单独的无源元件组合来构成输出匹配电路60。
在俯视时,第二部件32包含在第一部件31中。半导体装置30具备多个导体突起35,该多个导体突起配置在俯视时包含在第一部件31及第二部件32的每个部件中的位置。多个导体突起35从第一部件31及第二部件32朝向模块基板突出。半导体装置30通过使第二部件32与模块基板21对置,并经由多个导体突起35以倒装片方式安装于模块基板21。作为多个导体突起35,使用在由Cu构成的突起的顶面载置焊料的Cu柱凸块。此外,作为导体突起35,也可以使用如Au凸块那样不在上表面载置焊料的构造的凸块。这样的构造的突起也被称为“柱”。另外,作为导体突起35,也可以采用在焊盘上竖立导体柱的构造。这样的构造的导体突起也被称为“接线柱”。另外,作为导体突起35,也可以使用使焊料回流而成为球状的球凸块。作为导体突起35,除了这些各种构造之外,也能够使用包含从基板突出的导体的各种构造。
低噪声放大器71也经由多个导体突起以倒装片方式安装于模块基板21。输出匹配电路60以及多个双工器70经由焊料凸块65以倒装片方式安装于模块基板21。此外,这些倒装片方式安装用的凸块是一个例子,也可以使用其它构造的凸块。例如也可以使用Au凸块等。安装于模块基板21的多个电子部件被模制树脂25密封。
设置于半导体装置30的第二部件32的高频放大电路50的输出端口经由导体突起35及模块基板21内的布线22以及输出匹配电路60的焊料凸块65与输出匹配电路60连接。并且,输出匹配电路60经由另一个焊料凸块65、模块基板21内的另一个布线22以及从第一部件31突出的导体突起35与设置于第一部件31的频带选择开关41连接。布线22由配置在模块基板21内的多个布线层所包含的金属图案以及连接布线层间的多个通孔构成。
在俯视时,半导体装置30配置于输出匹配电路60的附近。此处,“半导体装置30配置于输出匹配电路60的附近”意味着从半导体装置30到输出匹配电路60的最短距离比从半导体装置30到其它电路部件例如双工器70的最短距离短。若使从半导体装置30到输出匹配电路60的最短距离比从半导体装置30到双工器70的最短距离短,则能够提高信号收发的隔离性。
优选地,在俯视时,半导体装置30和输出匹配电路60直接相邻地配置。优选地,在半导体装置30与输出匹配电路60之间的区域24不搭载电路部件。
在输出匹配电路60由多个表面安装型的无源元件构成的情况下,在构成输出匹配电路60的多个表面安装型的无源元件中离半导体装置30最近而配置的无源元件与半导体装置30之间的区域不搭载电路部件。在输出匹配电路60包含表面安装型的多个无源元件的情况下,输出匹配电路60由这多个无源元件以及连接这多个无源元件彼此的布线构成。此外,连接这些无源元件和输出匹配电路60以外的电路部件的布线不包含在输出匹配电路60中。
在输出匹配电路60由一个集成型无源设备(IPD)构成的情况下,在构成输出匹配电路60的一个无源元件(即,IPD)与半导体装置30之间不搭载电路部件。在这种情况下,若着眼于构成输出匹配电路60的一个IPD所包含的电容器、电感器等多个无源元件,则在输出匹配电路60所包含的多个无源元件中离半导体装置30最近而配置的无源元件与半导体装置30之间的区域不搭载电路部件。
图2是表示根据第一实施例的高频模块20的电路结构的框图。高频模块20包含安装于模块基板21的半导体装置30。半导体装置30包含设置于第一部件31的输入开关43、第一控制电路42以及发送用的频带选择开关41。第二部件32包含高频放大电路50。高频放大电路50设为驱动级放大电路51和功率级放大电路52的两级结构。
在模块基板21还安装有输出匹配电路60、多个双工器70、天线开关72、两个接收用的频带选择开关73、两个低噪声放大器71、接收用的输出端子选择开关74以及第二控制电路75。该高频模块20具有进行频分双工(FDD)方式的收发的功能。此外,在图1A中,省略接收用的频带选择开关73、输出端子选择开关74以及第二控制电路75的记载。在图2中,对设置于第一部件31的电子电路上附加相对淡的阴影线,对设置于第二部件32的电子电路上附加相对浓的阴影线。
输入开关43的两个输入侧的接点分别经由设置于第一部件31的导体突起35(图1B)与模块基板21的高频信号输入端子IN1、IN2连接。在图2中,用空心的正方形示出经由导体突起35的连接部位。从两个高频信号输入端子IN1、IN2输入高频信号。输入开关43从输入侧的两个接点选择一个接点,使输入到所选择的接点的高频信号输入至驱动级放大电路51。输入开关43与驱动级放大电路51的输入端口的连接使用部件间连接布线36。部件间连接布线36不经由模块基板21地连接设置于第一部件31的电子电路和设置于第二部件32的电子电路。对于部件间连接布线36的构造,在后面参照图4A~图5D的附图,在说明制造工序时进行说明。在图2中,用相对粗的实线示出通过部件间连接布线36连接的部位。
由驱动级放大电路51放大后的高频信号被输入到功率级放大电路52。由功率级放大电路52放大后的高频信号通过输出匹配电路60输入到频带选择开关41的一个输入侧的接点。功率级放大电路52的输出端口和输出匹配电路60经由设置于第二部件32的导体突起35(图1B)以及模块基板21内的布线22(图1B)而连接。输出匹配电路60和频带选择开关41的输入侧的接点经由设置于模块基板21的布线22(图1B)以及设置于第一部件31的导体突起35(图1B)而连接。频带选择开关41从多个输出侧的接点选择一个接点,使由功率级放大电路52放大后的高频信号从所选择的接点输出。
频带选择开关41的输出侧的多个接点中的两个接点分别经由导体突起35(图1B)与辅助输出端子PAAUX1、PAAUX2连接。其它的六个接点分别经由导体突起35(图1B)与按照每个频带准备的多个双工器70的发送用输入端口连接。频带选择开关41具有从按照每个频带准备的多个双工器70中选择一个双工器70的功能。
天线开关72具有电路侧的多个接点和天线侧的两个接点。天线开关72的多个电路侧的接点中的两个接点分别与发送信号输入端子TRX1、TRX2连接。电路侧的其它的六个接点分别与多个双工器70的输入输出共用端口连接。天线侧的两个接点分别与天线端子ANT1、ANT2连接。在天线端子ANT1、ANT2分别连接天线。
天线开关72将两个天线侧的接点分别连接于从电路侧的多个接点选择的两个接点。在使用一个频带进行通信的情况下,天线开关72将电路侧的一个接点与天线侧的一个接点连接。由高频放大电路50放大且通过了对应的频带用的双工器70的高频信号从与所选择的天线侧的接点连接的天线发送。
两个接收用的频带选择开关73的各个具有输入侧的四个接点。两个频带选择开关73各自的输入侧的四个接点中的三个接点分别与双工器70的接收用输出端口连接。两个频带选择开关73各自的剩余的一个接点分别与辅助输入端子LNAAUX1、LNAAUX2连接。
与两个接收用的频带选择开关73对应地准备两个低噪声放大器71。两个接收用的频带选择开关73分别使通过了双工器70的接收信号输入到对应的低噪声放大器71。
输出端子选择开关74的两个电路侧的接点分别与两个低噪声放大器71的输出端口连接。输出端子选择开关74的三个端子侧的接点分别与接收信号输出端子LNAOUT1、LNAOUT2、LNAOUT3连接。由低噪声放大器71放大后的接收信号从由输出端子选择开关74选择的接收信号输出端子输出。
从设置于模块基板21的电源端子VCC1、VCC2分别向驱动级放大电路51以及功率级放大电路52施加电源电压。电源端子VCC1、VCC2经由设置于第二部件32的导体突起35(图1B)与高频放大电路50连接。
第一控制电路42经由设置于第一部件31的导体突起35(图1B)与电源端子VIO1、控制信号端子SDATA1以及时钟端子SCLK1连接。第一控制电路42基于给与控制信号端子SDATA1的控制信号来控制高频放大电路50。第一控制电路42与高频放大电路50的连接使用部件间连接布线36。
第二控制电路75与电源端子VIO2、控制信号端子SDATA2以及时钟端子SCLK2连接。第二控制电路75基于给与控制信号端子SDATA2的控制信号来控制低噪声放大器71、频带选择开关73以及输出端子选择开关74。
在模块基板21还设置有电源端子VBAT以及漏极电压端子VDD2。从电源端子VBAT向高频放大电路50的偏置电路以及第一控制电路42供给电源。从漏极电压端子VDD2向安装于模块基板21的低噪声放大器71施加电源电压。
图3A是构成形成于第二部件32的功率级放大电路52(图2)的一个单元的等效电路图。功率级放大电路52包含相互并联连接的多个单元。各单元包含:晶体管402、输入电容器Cin以及镇流电阻元件Rb。晶体管402的基极经由输入电容器Cin与高频信号输入布线405RF连接。并且,晶体管402的基极经由镇流电阻元件Rb与基极偏置布线404BB连接。晶体管402的发射极接地。向晶体管402的集电极施加电源电压,并且从集电极输出放大后的高频信号。
图3B是构成形成于第二部件32的功率级放大电路52的一个单元的剖视图。第一部件31例如包含:硅基板、SOI基板等半导体基板、以及形成在其上的多层布线构造。虽然在图3B中未示出,但在构成第一部件31的半导体基板的表层部形成有频带选择开关41、第一控制电路42以及输入开关43(图1A)。
第二部件32包含基底半导体层401。基底半导体层401与第一部件31面接触,从而将第二部件32与第一部件31接合。基底半导体层401被划分为导电区域401A和元件分离区域401B。基底半导体层401例如使用GaAs。导电区域401A由n型GaAs形成,元件分离区域401B通过将绝缘杂质离子注入到n型GaAs层而形成。
在导电区域401A上配置有晶体管402。晶体管402包含从导电区域401A起依次层叠的集电极层402C、基极层402B以及发射极层402E。发射极层402E配置在基极层402B的一部分区域之上。作为一个例子,集电极层402C由n型GaAs形成,基极层402B由p型GaAs形成,发射极层402E由n型InGaP形成。即,晶体管402是异质结双极晶体管。
在基极层402B上配置有基极电极403B,基极电极403B与基极层402B电连接。在发射极层402E上配置有发射极电极403E,发射极电极403E与发射极层402E电连接。在导电区域401A上配置有集电极403C。集电极403C经由导电区域401A与集电极层402C电连接。
在基底半导体层401上配置有第一层的层间绝缘膜406,以便覆盖晶体管402、集电极403C、基极电极403B以及发射极电极403E。第一层的层间绝缘膜406例如由SiN等无机绝缘材料形成。在层间绝缘膜406设置有多个开口。
在层间绝缘膜406上配置有第一层的发射极布线404E、基极布线404B、集电极布线404C、基极偏置布线404BB以及镇流电阻元件Rb。发射极布线404E通过设置于层间绝缘膜406的开口与发射极电极403E连接。基极布线404B通过设置于层间绝缘膜406的其它开口与基极电极403B连接。集电极布线404C通过设置于层间绝缘膜406的其它开口与集电极403C连接。
基极布线404B延伸到未配置晶体管402的区域,其前端与镇流电阻元件Rb的一个端部重叠。在重叠部分,基极布线404B和镇流电阻元件Rb电连接。镇流电阻元件Rb的另一个端部与基极偏置布线404BB重叠。在重叠部分,镇流电阻元件Rb和基极偏置布线404BB电连接。
在层间绝缘膜406上配置有第二层的层间绝缘膜407,以便覆盖第一层的发射极布线404E、基极布线404B、镇流电阻元件Rb以及基极偏置布线404BB。第二层的层间绝缘膜407也由SiN等无机绝缘材料形成。
在层间绝缘膜407上配置有第二层的发射极布线405E以及高频信号输入布线405RF。第二层的发射极布线405E通过设置于层间绝缘膜407的开口与第一层的发射极布线404E连接。在俯视时,高频信号输入布线405RF的一部分与第一层的基极布线404B重叠。在两者的重叠区域形成输入电容器Cin。
配置有第三层的层间绝缘膜408,以便覆盖第二层的发射极布线405E以及高频信号输入布线405RF。第三层的层间绝缘膜408例如由聚酰亚胺等有机绝缘材料形成。
接下来,参照图4A~图5D的附图,对根据第一实施例的半导体装置30的制造方法进行说明。图4A~图5C的附图是制造中途阶段的半导体装置30的剖视图,图5D是完成的半导体装置30的剖视图。
如图4A所示,在GaAs等化合物半导体的单晶的母基板200上使剥离层201外延生长,在剥离层201上形成元件形成层202。在元件形成层202形成有图2所示的第二部件32的高频放大电路50的电子电路等。这些电子电路通过一般的半导体工艺形成。在图4A中,对于形成于元件形成层202的元件构造,省略记载。在该阶段,元件形成层202未分离成各个第二部件32。
接下来,如图4B所示,将抗蚀剂图案(未图示)作为蚀刻掩模,对元件形成层202(图4A)以及剥离层201进行图案化。在该阶段,元件形成层202(图4A)被分离成各个第二部件32。
接下来,如图4C所示,在分离后的第二部件32上粘贴连结支承体204。由此,多个第二部件32经由连结支承体204相互连结。此外,可以留下在图4B的图案化工序中用作蚀刻掩模的抗蚀剂图案,并使抗蚀剂图案介于第二部件32与连结支承体204之间。
接下来,如图4D所示,针对母基板200以及第二部件32选择性地蚀刻剥离层201。由此,从母基板200剥离第二部件32以及连结支承体204。为了选择性地蚀刻剥离层201,而使用蚀刻耐性与母基板200及第二部件32均不同的化合物半导体作为剥离层201。
如图4E所示,准备形成设置于第一部件31的频带选择开关41、第一控制电路42以及输入开关43(图1A)等的基板210。在该阶段,基板210没有被分离成各个第一部件31。
如图4F所示,将第二部件32与基板210接合。第二部件32与基板210的接合通过范德瓦耳斯键或者氢键。除此之外,也可以通过静电、共价键合、共晶合金键合等将第二部件32与基板210接合。例如,在基板210的表面的一部分由Au形成的情况下,也可以使第二部件32与Au区域密接并进行加压,从而将两者接合。
接下来,如图5A所示,从第二部件32剥离连结支承体204。在剥离连结支承体204之后,如图5B所示,在基板210以及第二部件32上形成层间绝缘膜80以及再布线层。再布线层包含部件间连接布线36以及焊盘37。
接下来,如图5C所示,在再布线层上形成保护膜81,在保护膜81形成开口81A等。然后,在开口81A内以及保护膜81上形成导体突起35。并且,在这些导体突起35的顶面载置焊料83来进行回流处理。
最后,如图5D所示,切割基板210。由此,得到单片化的半导体装置30。在俯视时,单片化后的半导体装置30各自的第一部件31比第二部件32大。单片化后的半导体装置30以倒装片方式安装于模块基板21(图1A、图1B)。
接下来,对第一实施例的优异的效果进行说明。
在第一实施例中,将包含元素半导体系的半导体元件的第一部件31和包含化合物半导体系的半导体元件的第二部件32堆叠而成为一个半导体装置30。因此,与将两者单独安装于模块基板21的结构相比,能够实现高频模块20的小型化。并且,由于频带选择开关41设置于第一部件31,因此与将频带选择开关41单独安装于模块基板21的结构相比,能够实现高频模块20的小型化。
并且,形成在第二部件32所包含的晶体管402(图3B)产生的热到达第一部件31(图1B、图5D)的传热路径、和经由导体突起35(图5D)到达模块基板21(图1B)的传热路径这两个传热路径。由于比第二部件32大的第一部件31以及模块基板21作为散热器发挥功能,所以能够提高从晶体管402的散热特性。
并且,在第一实施例中,半导体装置30配置在输出匹配电路60的附近。例如,在俯视时,在半导体装置30与输出匹配电路60之间的区域24(图1A)未搭载电路部件。因此,能够缩短图2所示的从高频放大电路50到输出匹配电路60的传输线路以及从输出匹配电路60到频带选择开关41的传输线路。通过缩短传输线路,能够减少高频信号的传输损耗。其结果,能够实现高效率化。
为了缩短从高频放大电路50到输出匹配电路60的传输线路以及从输出匹配电路60到频带选择开关41的传输线路,优选相对于俯视时的第一部件31的几何中心,使第二部件32以及频带选择开关41偏向输出匹配电路60侧而配置。
[第二实施例]
接下来,参照图6A~图7B的附图,对根据第二实施例的高频模块进行说明。以下,对于与参照图1A~图5D的附图进行说明的根据第一实施例的高频模块相同的结构,省略说明。
图6A是表示根据第二实施例的高频模块20的各构成要素的俯视时的位置关系的图,图6B是示意性地表示高频模块20的截面构造的图。在第一实施例(图1A)中,在俯视时,半导体装置30与输出匹配电路60不重叠,配置在输出匹配电路60的附近。与此相对,在第二实施例中,在俯视时,半导体装置30与输出匹配电路60所包含的多个无源元件中的一部分无源元件的至少一部分重叠。
如图6B所示,输出匹配电路60包含电感器61和电容器62。电感器61由配置在模块基板21内的金属图案形成。电容器62使用安装于模块基板21的单独的表面安装部件。在俯视时,电感器61的至少一部分与半导体装置30重叠,电容器62配置在半导体装置30的附近。在俯视时,电容器62和半导体装置30相邻地配置。例如,在输出匹配电路60所包含的表面安装型的无源元件中的配置于离半导体装置30最近的位置的表面安装型的无源元件与半导体装置30之间未搭载电路部件。
图7A是表示输出匹配电路60的一个例子的等效电路图。在高频放大电路50的输出端口与频带选择开关41之间串联连接有串联电感器L1、L2以及串联电容器C3。在串联电感器L1与L2之间连接有接地连接电容器C1,在串联电感器L2与串联电容器C3之间连接有接地连接电容器C2。另外,电源电压Vcc经由扼流线圈LC被施加到高频放大电路50的输出端口。在电源电压Vcc与接地之间连接有去耦电容器CD。
图7B是表示输出匹配电路60的构成要素的平面配置的一个例子的图。在图7B中,对模块基板21(图6B)的第一层的布线层的金属图案附加向右上倾斜的浓的阴影线,对比第一层深的第二层的布线层的金属图案附加向右下倾斜的淡的阴影线。第一层的布线层的金属图案和第二层的布线层的金属图案重叠的圆形的区域意味着配置有连接两者的通孔。输出匹配电路60包含:由配置于模块基板21的金属图案构成的无源元件、和安装于模块基板21的表面安装型的无源元件(SMD)。
串联电感器L1由第一层的布线层所包含的螺旋状的金属图案形成,在俯视时,包含在半导体装置30中。此外,也可以将构成串联电感器L1的金属图案形成为曲折形状。另一个串联电感器L2由俯视时配置于半导体装置30的外侧的第一层的布线层所包含的金属图案形成。
接地连接电容器C1、C2以及串联电容器C3使用单独的表面安装型的无源元件(SMD)。在构成输出匹配电路60的表面安装型的多个单独的无源元件(即、接地连接电容器C1、C2以及串联电容器C3)中的配置于离半导体装置30最近的位置的无源元件与半导体装置30之间未安装电路部件。另外,在构成输出匹配电路60的多个无源元件中的俯视时配置于半导体装置30的外侧的无源元件(即接地连接电容器C1、C2、串联电容器C3以及串联电感器L2)中配置于离半导体装置30最近的位置的无源元件与半导体装置30之间未安装电路部件。
在串联电感器L2与半导体装置30之间未搭载不是构成输出匹配电路60的电路部件的电路部件。
接下来,对第二实施例的优异的效果进行说明。
在第二实施例中,在俯视时,输出匹配电路60的一部分与半导体装置30重叠,因此能够实现高频模块的进一步的小型化。另外,与第一实施例同样地,能够获得提高散热特性的效果以及减少传输损耗的效果。
接下来,对第二实施例的变形例进行说明。在第二实施例中,由设置于模块基板21的金属图案构成串联电感器L2,但也可以由单独的表面安装部件构成串联电感器L2。另外,在第二实施例中,接地连接电容器C1、C2以及串联电容器C3全部使用表面安装部件,但也可以一部分电容器使用频带选择开关41的内置电容。作为其它结构,也可以使用数字可调电容器作为接地连接电容器C1、C2以及串联电容器C3。
此外,优选要求高的Q值的无源元件由模块基板21内的金属图案、表面安装部件构成。不要求高的Q值的无源元件也可以设置于第一部件31。例如,与其它无源元件相比,串联电容器C3不要求高的Q值。因此,也可以将串联电容器C3形成于第一部件31。
[第三实施例]
接下来,参照图8A以及图8B,对根据第三实施例的高频模块进行说明。以下,对于与参照图6A~图7B的附图进行说明的根据第二实施例的高频模块相同的结构,省略说明。
图8A是表示输出匹配电路60的一个例子的等效电路图。在第二实施例中,使用单端型的放大电路作为高频放大电路50,但在第三实施例中使用差动放大电路。高频放大电路50具有输出差动信号的两个输出端口。输出匹配电路60包含:具有初级线圈L5和次级线圈L6的输出变压器、接地连接电容器C5以及串联电容器C6。
在两个输出端口之间连接有输出变压器的初级线圈L5。初级线圈L5的中间抽头与电源电压Vcc连接。输出变压器的次级线圈L6的一个端部经由串联电容器C6与频带选择开关41连接,并且经由接地连接电容器C5接地。次级线圈L6的另一个端部接地。
图8B是表示输出匹配电路60的构成要素的平面配置的一个例子的图。在图8B中,对模块基板21(图6B)的第一层的布线层的金属图案附加向右上倾斜的浓的阴影线,对第二层的布线层的金属图案附加向右下倾斜的淡的阴影线。由第二层的布线层的金属图案构成初级线圈L5。由第一层的布线层的金属图案形成的次级线圈L6包围初级线圈L5。此外,也可以成为在俯视时初级线圈L5和次级线圈L6大致重叠的结构,来代替次级线圈L6包围初级线圈L5的结构。接地连接电容器C5以及串联电容器C6使用单独的表面安装部件。在俯视时,初级线圈L5以及次级线圈L6各自的一部分与半导体装置30重叠。
接下来,对第三实施例的优异的效果进行说明。
在第三实施例中也与第二实施例同样地,在俯视时,输出匹配电路60的一部分与半导体装置30重叠,因此能够实现高频模块的进一步的小型化。另外,与第二实施例同样地,能够获得提高散热特性的效果以及减少传输损耗的效果。
[第四实施例]
接下来,参照图9A,对根据第四实施例的高频模块进行说明。以下,对于与参照图1A~图5D的附图进行说明的根据第一实施例的高频模块相同的结构,省略说明。
图9A是示意性地表示根据第四实施例的高频模块20的截面构造的图。在第一实施例中,使用单面安装型的印刷电路板作为模块基板21,但在第四实施例中使用双面安装型的印刷电路板。
在作为模块基板21的一个面的第一面21A安装有半导体装置30以及多个双工器70。在与第一面21A相反侧的第二面21B安装有输出匹配电路60、低噪声放大器71以及天线开关72。作为输出匹配电路60,使用集成型无源设备。此外,也可以由多个表面安装部件构成输出匹配电路60。在俯视时,输出匹配电路60与半导体装置30重叠。在由多个表面安装部件构成输出匹配电路60的情况下,多个表面安装部件中的至少一部分表面安装部件被配置为在俯视中与半导体装置30重叠。
形成于第二部件32的高频放大电路50经由从第二部件32突出的导体突起35、从模块基板21内的第一面21A到达第二面21B的布线22以及输出匹配电路60的焊料凸块65与输出匹配电路60连接。并且,输出匹配电路60经由另一个焊料凸块65、另一个布线22以及从第一部件31突出的导体突起35与频带选择开关41连接。此外,能够使用Cu柱凸块、柱、接线柱等各种构造的导体突起,来代替焊料凸块65。
多个导体柱27以相对于第二面21B大致垂直的姿势安装于模块基板21的第二面21B。安装于模块基板21的第一面21A的半导体装置30、双工器70等被模制树脂25密封。并且,安装于第二面21B的输出匹配电路60、低噪声放大器71以及天线开关72等被模制树脂26密封。多个导体柱27的前端在模制树脂26的表面露出。多个导体柱27的露出的前端面用作用于与母板等连接的电极端子。也可以在多个导体柱27各自的导体柱的露出的前端面载置由焊料构成的球凸块(也称为焊料凸块)。另外,也可以在导体柱27的露出的表面上配置Cu柱凸块、支柱等。作为其它结构,也可以使用Cu柱凸块、支柱、焊料凸块等代替导体柱27。
接下来,对第四实施例的优异的效果进行说明。
在第四实施例中,半导体装置30和输出匹配电路60隔着模块基板21安装于不同的面,在俯视时,两者重叠地配置。因此,能够进一步缩短连接半导体装置30的高频放大电路50和输出匹配电路60的布线22以及连接输出匹配电路60和频带选择开关41的布线22。在图9A中,用带箭头的曲线表示从高频放大电路50经由输出匹配电路60到达频带选择开关41的高频信号的传输路径。由于传输路径变短,因此能够减少高频信号的传输损耗,实现高效率化。并且,在第四实施例中也与第一实施例同样地,能够提高散热特性,并且能够实现小型化。
接下来,参照图9B,对根据第四实施例的变形例的高频模块20进行说明。
图9B是示意性地表示根据第四实施例的变形例的高频模块20的截面构造的图。在第四实施例(图9A)中,半导体装置30安装于模块基板21的第一面21A,输出匹配电路60安装于第二面21B、即安装在母板的状态下朝向母板侧的面。与此相对,在本变形例中,半导体装置30安装于模块基板21的第二面21B、即安装在母板的状态下朝向母板侧的面。输出匹配电路60安装于与安装有半导体装置30的第二面21B相反侧的第一面21A。在本变形例中,在俯视时,输出匹配电路60也与半导体装置30重叠。在图9B中也与图9A同样地,用带箭头的曲线表示高频信号的传输路径。
如第四实施例及其变形例所示,可以将半导体装置30以及输出匹配电路60的任意一个安装于朝向母板侧的面。在任一情况下,只要将输出匹配电路60安装于与安装有半导体装置30的面相反侧的面即可。
[第五实施例]
接下来,参照图10,对根据第五实施例的高频模块进行说明。以下,对于与根据第四实施例的高频模块20(图9A)相同的结构,省略说明。
图10是示意性地表示根据第五实施例的高频模块20的截面构造的图。在第四实施例中,由集成型无源设备、或者多个表面安装部件构成输出匹配电路60。与此相对,在第五实施例中,输出匹配电路60所包含的电感器61由模块基板21的布线层所包含的金属图案构成。电容器62使用单独的表面安装部件。构成输出匹配电路60的表面安装部件安装于与安装有半导体装置30的面相反侧的面。
在俯视时,电感器61的至少一部分与半导体装置30重叠。并且,在俯视时,电容器62的至少一部分也与半导体装置30重叠。
接下来,对第五实施例的优异的效果进行说明。在第五实施例中也与第四实施例同样地,能够实现高频模块20的小型化、低损耗化、提高散热特性。
上述的各实施例为例示,当然能够进行不同的实施例所示的结构的部分的置换或者组合。不在每个实施例依次提及多个实施例的相同的结构所带来的相同的作用效果。并且,本发明并不限定于上述的实施例。例如,本领域技术人员明确能够进行各种变更、改进、组合等。
Claims (4)
1.一种高频模块,其中,具备:
模块基板;
半导体装置,安装于上述模块基板,并包含高频放大电路和频带选择开关;以及
输出匹配电路,设置于上述模块基板,并连接在上述高频放大电路与上述频带选择开关之间,
上述频带选择开关使输入的高频信号从多个接点中所选择的一个接点输出,
上述半导体装置包含:
第一部件,包含上述频带选择开关,上述频带选择开关包含元素半导体系的半导体元件;
第二部件,与上述第一部件面接触地接合,并包含上述高频放大电路,上述高频放大电路包含化合物半导体系的半导体元件;以及
多个导体突起,配置于在俯视时包含在上述第一部件以及上述第二部件的每个部件中的位置,
上述半导体装置通过使上述第二部件与上述模块基板对置,并经由上述多个导体突起而安装于上述模块基板,
在俯视时,上述半导体装置配置在上述输出匹配电路的附近,或者上述半导体装置和构成上述输出匹配电路的至少一个无源元件重叠。
2.根据权利要求1所述的高频模块,其中,
上述输出匹配电路包含无源元件,上述无源元件由设置于上述模块基板的金属图案构成,
在俯视时,上述半导体装置与构成上述输出匹配电路的无源元件的金属图案的至少一部分重叠。
3.根据权利要求1或2所述的高频模块,其中,
上述输出匹配电路包含安装于上述模块基板的无源元件,
上述输出匹配电路所包含的无源元件安装于上述模块基板的与安装有上述半导体装置的面相反侧的面。
4.根据权利要求3所述的高频模块,其中,
在俯视时,上述半导体装置与上述输出匹配电路所包含的无源元件重叠。
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