CN111355513A - 高频模块和通信装置 - Google Patents

高频模块和通信装置 Download PDF

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Publication number
CN111355513A
CN111355513A CN201911330176.2A CN201911330176A CN111355513A CN 111355513 A CN111355513 A CN 111355513A CN 201911330176 A CN201911330176 A CN 201911330176A CN 111355513 A CN111355513 A CN 111355513A
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Prior art keywords
frequency module
noise amplifier
inductor
main surface
low noise
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CN201911330176.2A
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CN111355513B (zh
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上岛孝纪
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • H04B1/56—Circuits using the same frequency for two directions of communication with provision for simultaneous communication in two directions
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    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
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Abstract

提供一种高频模块和通信装置，该高频模块的接收灵敏度的劣化得到抑制。高频模块(1)具备：安装基板(91)；低噪声放大器(40)，其包括放大元件，放大高频信号；以及阻抗匹配电路(62)，其包括集成化的第一电感器，其中，第一电感器与低噪声放大器(40)的输入端子连接，低噪声放大器(40)与阻抗匹配电路(62)沿与安装基板(91)的主面(91a)垂直的方向进行层叠，低噪声放大器(40)与阻抗匹配电路(62)层叠而成的第一层叠体安装于主面(91a)。

Description

高频模块和通信装置
技术领域
本发明涉及一种高频模块和通信装置。
背景技术
在便携式电话等移动通信设备中，特别是，随着多频段化的进展，构成高频前端电路的电路元件的配置结构变得复杂。
专利文献1中公开了具有发送电路和接收电路的无线通信设备(高频电路)的电路结构。在该无线通信设备中，利用与天线连接的开关来切换发送电路及接收电路与天线的连接。发送电路具有功率放大器(PA)以及配置于功率放大器与开关之间的发送阻抗匹配电路。接收电路具有低噪声放大器(LNA)以及配置于低噪声放大器与开关之间的接收阻抗匹配电路。
现有技术文献
专利文献
专利文献1：日本特表2014-530543号公报
发明内容
发明要解决的问题
然而，在将专利文献1中公开的无线通信设备(高频电路)用1个模块构成为移动通信设备的紧凑的前端电路的情况下，例如，当将接收阻抗匹配电路连接到低噪声放大器的输入端子的布线长时，在该布线中产生寄生电容。由此，产生以下问题：低噪声放大器与其前级的电路元件之间的阻抗匹配不足，从低噪声放大器输出的高频接收信号的接收灵敏度劣化。
本发明是为了解决上述问题而完成的，其目的在于提供一种接收灵敏度的劣化得到抑制的高频模块和通信装置。
用于解决问题的方案
为了实现上述目的，本发明的一个方式所涉及的高频模块具备：安装基板；低噪声放大器，其包括放大元件，放大高频信号；以及第一集成型无源元件，其包括集成化的第一电感器，其中，所述第一电感器与所述低噪声放大器的输入端子连接，所述低噪声放大器与所述第一集成型无源元件沿与所述安装基板的主面垂直的方向进行层叠，所述低噪声放大器与所述第一集成型无源元件层叠而成的第一层叠体安装于所述主面。
发明的效果
根据本发明，能够提供接收灵敏度的劣化得到抑制的高频模块和通信装置。
附图说明
图1是实施方式所涉及的通信装置的电路结构图。
图2是实施方式所涉及的高频模块的截面概要图。
图3是实施方式的变形例1所涉及的高频模块的截面概要图。
图4是实施方式的变形例2所涉及的高频模块的截面概要图。
图5是实施方式的变形例3所涉及的高频模块的截面概要图。
图6是实施方式的变形例4所涉及的高频模块的截面概要图。
图7是实施方式的变形例5所涉及的高频模块的截面概要图。
附图标记说明
1、1A、1B、1C、1D、1E：高频模块；2：天线；3：RF信号处理电路(RFIC)；4：基带信号处理电路(BBIC)；5：通信装置；11、12：开关；21：双工器；21R、22R：接收滤波器；21T：发送滤波器；30：功率放大器；40：低噪声放大器；51、52、52D、61、61A、61D、62、62A、62C、62D、62E：阻抗匹配电路；80：屏蔽电极层；91：安装基板；91a、91b：主面；91G：地电极图案；92、93：树脂构件；110：输入输出端子；120：发送端子；130：接收端子；150：外部连接导体。
具体实施方式
下面，使用附图来详细说明本发明的实施方式及其变形例。此外，下面说明的实施方式及其变形例均示出总括性或具体性的例子。下面的实施方式及其变形例所示的数值、形状、材料、结构要素、结构要素的配置以及连接方式等是一个例子，其主旨并不在于限定本发明。将下面的实施方式及其变形例的结构要素中的未记载于独立权利要求的结构要素作为任意的结构要素来进行说明。另外，附图所示的结构要素的大小或者大小之比未必是严格的。
此外，在下面的实施方式中，在安装于基板上的A、B及C中，“在俯视该基板(或该基板的主面)的情况下，C配置于A与B之间”被定义为：在俯视该基板的情况下投影后的C的区域的至少一部分重叠于将在俯视该基板的情况下投影后的A的区域内的任意的点与在俯视该基板的情况下投影后的B的区域内的任意的点连结的线上。
另外，在本说明书中，表示要素之间的关系性的用语(例如“垂直”、“平行”等)和表示要素的形状的用语以及数值范围是表示实质上等同的范围的表述，例如还包括百分之几左右的差异，而不是仅表示严格意义的表述。
此外，在下面的实施方式及其变形例中，“A与B连接”被定义为：不仅指A与B接触，还包括A与B经由导体布线电连接。
(实施方式)
[1高频模块1和通信装置5的电路结构]
图1是实施方式所涉及的高频模块1的电路结构图。如该图所示，通信装置5具备高频模块1、天线2、RF(Radio Frequency：射频)信号处理电路(RFIC)3以及基带信号处理电路(BBIC)4。
RFIC 3是对利用天线2发送接收的高频信号进行处理的RF信号处理电路。具体地说，RFIC 3对经由高频模块1的接收信号路径输入的高频接收信号通过下变频等进行信号处理，将该信号处理后生成的接收信号输出到BBIC 4。另外，RFIC 3对从BBIC 4输入的发送信号通过上变频等进行信号处理，将该信号处理后生成的高频发送信号输出到高频模块1的发送信号路径。
BBIC 4是使用频率比在高频模块1中传输的高频信号的频率低的中间频带来进行信号处理的电路。由BBIC 4处理后的信号例如被用作用于图像显示的图像信号，或者被用作声音信号以借助扬声器进行通话。
另外，RFIC 3还具有基于所使用的通信频段(频带)来控制高频模块1所具有的开关11的连接的作为控制部的功能。具体地说，RFIC 3通过控制信号(未图示)来切换高频模块1所具有的开关11的连接。此外，控制部也可以设置于RFIC 3的外部，例如也可以设置于高频模块1或BBIC 4。
天线2与高频模块1的输入输出端子110连接，辐射从高频模块1输出的高频信号，另外，接收来自外部的高频信号后输出到高频模块1。
此外，在本实施方式所涉及的通信装置5中，天线2和BBIC 4不是必需的结构要素。
接着，说明高频模块1的详细结构。
如图1所示，高频模块1具备输入输出端子110、接收端子130、发送端子120、低噪声放大器40、功率放大器30、阻抗匹配电路51、52、61及62、开关11及12、接收滤波器21R及22R以及发送滤波器21T。
低噪声放大器(LNA：Low Noise Amplifier)40包括双极晶体管或场效应晶体管等放大元件，例如以低噪声优先对通信频段A及B的高频信号进行放大。低噪声放大器40配置于高频模块1的接收路径。
功率放大器(PA：Power Amplifier)30包括双极晶体管或场效应晶体管等放大元件，例如优先对频段A的高频信号进行功率放大。功率放大器30配置于高频模块1的发送路径。
低噪声放大器40和功率放大器30例如由Si系的CMOS(Complementary MetalOxide Semiconductor：互补金属氧化物半导体)、以GaAs为材料的场效应晶体管(FET)、或异质结双极型晶体管(HBT)等构成。
接收滤波器21R配置于将开关11及12连结的第一接收路径，使从输入输出端子110输入的高频接收信号中的通信频段A的接收带的高频接收信号通过。另外，接收滤波器22R配置于将开关11及12连结的第二接收路径，使从输入输出端子110输入的高频接收信号中的通信频段B的接收带的高频接收信号通过。
发送滤波器21T配置于将开关11与功率放大器30连结的发送路径，使被功率放大器30放大后的高频发送信号中的通信频段A的发送带的高频发送信号通过。
此外，上述的接收滤波器21R、22R以及发送滤波器21T例如可以是声表面波滤波器、使用了BAW(Bulk Acoustic Wave：体声波)的弹性波滤波器、LC谐振滤波器、以及电介质滤波器中的任一个，而且不限定于它们。
发送滤波器21T和接收滤波器21R构成了以通信频段A为通带的双工器21。
开关11配置于将输入输出端子110与接收滤波器22R连结的路径以及将输入输出端子110与双工器21连结的路径。通过该配置结构，开关11对用于传输通信频段A的高频信号的信号路径与输入输出端子110之间的连接以及用于传输通信频段B的高频信号的信号路径与输入输出端子110之间的连接进行切换。开关11例如由SPDT(Single Pole DoubleThrow：单刀双掷)型的开关电路构成。
开关12配置于将接收滤波器21R与低噪声放大器40连结的路径以及将接收滤波器22R与低噪声放大器40连结的路径。通过该配置结构，开关12对接收滤波器21R与低噪声放大器40之间的连接以及接收滤波器22R与低噪声放大器40之间的连接进行切换。开关12例如由SPDT型的开关电路构成。
此外，开关11及12例如可以由Si系的CMOS或GaAs构成。
阻抗匹配电路52配置于将功率放大器30与发送滤波器21T连结的路径，取得功率放大器30的输出阻抗与发送滤波器21T的输入阻抗之间的匹配。在本实施方式中，阻抗匹配电路52包括与功率放大器30连接的电感器(第三电感器)。
阻抗匹配电路62配置于将开关12与低噪声放大器40连结的路径，取得接收滤波器21R及22R的输出阻抗与低噪声放大器40的输入阻抗之间的匹配。在本实施方式中，阻抗匹配电路62包括与低噪声放大器40连接的电感器(第一电感器)。也就是说，第一电感器是用于取得在低噪声放大器40的前级配置的电路元件的输出阻抗与低噪声放大器40的输入阻抗之间的匹配的阻抗匹配元件。
阻抗匹配电路51配置于将开关11与双工器21连结的路径，取得天线2及开关11与双工器21之间的阻抗匹配。
阻抗匹配电路61配置于将开关11与接收滤波器22R连结的路径，取得天线2及开关11与接收滤波器22R之间的阻抗匹配。在本实施方式中，阻抗匹配电路61包括与开关11连接的电感器(第二电感器)。
根据高频模块1的上述电路结构，能够执行通信频段A的高频信号的发送接收以及通信频段B的高频信号的接收中的至少一方。
此外，本发明所涉及的高频模块只要至少具备实施方式所涉及的高频模块1的结构要素中的、低噪声放大器40以及与低噪声放大器40的输入端子连接的阻抗匹配电路62即可。
因而，本发明所涉及的高频模块所能够传输的通信频段的数量也是任意的，另外，是否在同一通信频段中同时传输发送信号和接收信号、以及是否在不同的通信频段之间同时传输信号也是任意的。
在此，在将构成上述高频模块1的各电路元件用1个模块构成为紧凑的前端电路的情况下，当将低噪声放大器40与阻抗匹配电路62连接的布线长时，在该布线中产生寄生电容，从而存在以下问题：低噪声放大器40与前级的电路元件(开关12、接收滤波器21R及22R)之间的阻抗匹配不足，从低噪声放大器40输出的高频接收信号的接收灵敏度劣化。
与此相对，在本实施方式所涉及的高频模块1中，具有以下结构：缩短将低噪声放大器40与阻抗匹配电路62连接的布线来抑制寄生电容的产生。下面，说明在使高频模块1小型化的同时抑制寄生电容的产生的结构。
[2高频模块1的电路元件配置结构]
图2是实施方式所涉及的高频模块1的截面概要图。如图2所示，本实施方式所涉及的高频模块1除了图1所示的电路结构以外，还具有安装基板91、树脂构件92及93以及外部连接导体150。
安装基板91具有相互背对的主面91a(第一主面)和主面91b(第二主面)，是安装构成高频模块1的电路元件和部件的基板。作为安装基板91，例如使用具有多个电介质层的层叠构造的低温共烧陶瓷(Low Temperature Co-fired Ceramics：LTCC)基板或者印刷电路板等。
阻抗匹配电路62是第一电感器集成安装于第二基板的内部或表面而成的第一集成型无源元件(第一IPD：Integrated Passive Device)。
如图2所示，低噪声放大器40与阻抗匹配电路62沿与安装基板91的主面91a垂直的方向(z轴方向)进行层叠。另外，低噪声放大器40与阻抗匹配电路62层叠而成的第一层叠体安装于主面91a。
根据高频模块1的上述结构，低噪声放大器40与阻抗匹配电路62沿与安装基板91的主面91a垂直的方向(z轴方向)进行层叠，因此能够节省安装基板91的安装面的面积。因而，能够使高频模块1小型化。另外，低噪声放大器40与阻抗匹配电路62沿z轴方向进行层叠，因此能够缩短将低噪声放大器40与阻抗匹配电路62连接的布线。由此，能够减少在上述布线中产生的寄生电容，因此能够高精度地实施低噪声放大器40与其前级的电路元件(开关12、接收滤波器21R及22R)之间的阻抗匹配。因此，能够抑制从低噪声放大器40输出的高频接收信号的接收灵敏度的劣化。
另外，在本实施方式所涉及的高频模块1中，低噪声放大器40具有第一基板，放大元件被安装于该第一基板。另一方面，阻抗匹配电路62具有第二基板，第一电感器被集成安装于该第二基板。在此，第一基板和第二基板可以由硅形成。
据此，在由低噪声放大器40和阻抗匹配电路62构成的第一层叠体中，同一材料的第一基板和第二基板进行层叠，因此能够抑制以下情况：由于热循环中的线膨胀系数的不同，低噪声放大器40与阻抗匹配电路62分离或损坏。
在上述的第一层叠体中，例如，低噪声放大器40的输入端子形成于第一基板的下表面，第一电感器的一方的端子形成于阻抗匹配电路62的上表面，低噪声放大器40的输入端子与第一电感器的上述一方的端子例如经由凸块电极进行连接。另外，第一电感器的另一方的端子形成于阻抗匹配电路62的下表面，第一电感器的上述另一方的端子与主面91a例如经由凸块电极进行连接。
此外，本实施方式中的凸块电极是由高导电性金属构成的球状的电极，例如能够列举出由Sn/Ag/Cu构成的焊锡凸块以及以Au为主成分的凸块等。另外，例如也可以是由焊锡膏形成的电极来代替凸块电极。
此外，在本说明书中，将基板的相互背对的主面中的接近安装基板91的主面记载为下表面，将远离安装基板91的主面记载为上表面。
此外，在本实施方式中，在剖视安装基板91的情况下，阻抗匹配电路62(第一集成型无源元件)配置于安装基板91与低噪声放大器40之间。
另外，在本实施方式所涉及的高频模块1中，功率放大器30安装于主面91a。另外，阻抗匹配电路52也可以由芯片状的第三电感器构成，以不与功率放大器30层叠的方式安装于主面91a。形成于功率放大器30的下表面的输入输出端子与主面91a例如经由凸块电极进行连接。此外，为了提高功率放大器30的散热性，也可以是，形成于功率放大器30的下表面的散热用电极与主面91a接合，从功率放大器30的上表面到主面91a形成有接合线。
在功率放大器30由例如由GaAs形成的HBT构成的情况下，当对功率放大器30层叠配置由硅形成的IPD时，形成GaAs和Si这样的不同的材料的芯片的层叠体。此时，在线膨胀系数互不相同的Si芯片与GaAs芯片的层叠体中，由于功率放大器30进行动作时的发热，层叠体的温度发生变化，在2个芯片的接合部分处产生应力从而产生裂纹和安装不良等问题。另外，还设想了以下情况：当功率放大器30的热传导到Si芯片时，形成于Si芯片的电路元件的特性发生变化。
与此相对，根据本实施方式所涉及的高频模块1的上述结构，阻抗匹配电路52与功率放大器30不存在层叠关系，因此能够防止在阻抗匹配电路52中产生裂纹和安装不良，另外，能够抑制功率放大器30的发热所引起的阻抗匹配电路52的特性变化。
另外，也可以是，在本实施方式所涉及的高频模块1中，开关11安装于主面91a，在俯视主面91a的情况下，开关11配置于功率放大器30与第一层叠体之间。
据此，开关11配置于构成发送电路的功率放大器30与构成接收电路的低噪声放大器40之间，因此能够抑制高输出的发送信号泄漏到低噪声放大器40，能够提高发送电路与接收电路之间的隔离度。
另外，在本实施方式所涉及的高频模块1中，阻抗匹配电路61包括第二电感器，第二电感器是集成安装于第三基板的内部或表面的第二集成型无源元件(第二IPD)。在此，如图2所示，开关11与阻抗匹配电路61也可以沿与安装基板91的主面91a垂直的方向(z轴方向)进行层叠。另外，开关11与阻抗匹配电路61层叠而成的第二层叠体也可以安装于主面91a。
由此，开关11与阻抗匹配电路61沿与安装基板91的主面91a垂直的方向(z轴方向)进行层叠，因此能够节省安装基板91的安装面的面积，因此能够使高频模块1小型化。另外，开关11与阻抗匹配电路61沿z轴方向进行层叠，因此能够缩短将开关11与阻抗匹配电路61连接的布线。由此，能够减少在上述布线中产生的寄生电容，因此能够减少通信频段B的接收路径的传输损耗。
另外，第二层叠体配置于功率放大器30与第一层叠体之间，因此第二层叠体能够切断来自功率放大器30的发送信号的泄漏成分(电磁场)，因此能够抑制来自功率放大器30的不需要的波所引起的低噪声放大器40的特性变动。
另外，也可以是，开关11由Si系的CMOS构成，第三基板由硅形成。
据此，在第二层叠体中，层叠以硅为基材的电路元件，因此能够抑制以下情况：由于热循环中的线膨胀系数的不同，开关11与阻抗匹配电路61分离或损坏。
在开关11与阻抗匹配电路61的第二层叠体中，第二电感器的端子形成于第三基板的下表面，开关11的一个端子形成于开关11的上表面，第二电感器的上述端子与开关11的上述一个端子例如经由凸块电极进行连接。另外，开关11的其它端子形成于开关11的下表面，开关11的上述其它端子与主面91a例如经由凸块电极进行连接。此外，例如也可以是由焊锡膏形成的电极来代替凸块电极。
此外，第二层叠体也可以是开关11与阻抗匹配电路51层叠而成的。据此，能够减少将开关11与阻抗匹配电路51连接的布线中产生的寄生电容，因此能够减少通信频段A的接收路径的传输损耗。
此外，在本实施方式所涉及的高频模块1中，还在安装基板91的主面91b安装有开关12、双工器21以及接收滤波器22R。另外，用于将主面91b与外部基板连接的外部连接导体150形成于主面91b上。并且，覆盖功率放大器30、第一层叠体、第二层叠体以及阻抗匹配电路52中的至少一部分的树脂构件92配置于主面91a。另外，覆盖开关12、双工器21、接收滤波器22R以及外部连接导体150中的至少一部分的树脂构件93配置于主面91b。通过配置树脂构件92及93，构成高频模块1的上述电路元件和部件的气密性、耐热性、耐水耐湿性以及绝缘性等的可靠性被强化。
外部连接导体150例如是使用Cu等金属的柱状导体、或者在形成于树脂构件93的贯通通路孔中填充的导电性膏。
树脂构件92及93例如是热固化性的环氧树脂，也可以还含有SiO2等无机填料。此外，树脂构件92及93不是本发明所涉及的高频模块所必需的结构要素。
另外，功率放大器30、第二层叠体、开关12、双工器21、接收滤波器22R以及外部连接导体150可以安装于主面91a及91b中的任一个，还可以内置于安装基板91。
[3变形例1所涉及的高频模块1A的电路元件配置结构]
另外，在本实施方式所涉及的高频模块1中，例示了电路元件和部件被分配到安装基板91的两个面(主面91a及91b)的结构，但是这些电路元件和部件也可以安装于安装基板91的单面。
图3是实施方式的变形例1所涉及的高频模块1A的截面概要图。在该图中，示出了功率放大器30、第一层叠体(低噪声放大器40和阻抗匹配电路62)、第二层叠体(开关11和阻抗匹配电路61)以及阻抗匹配电路52安装于主面91a的结构。此外，虽未进行图示，但是开关12、双工器21以及接收滤波器22R也安装于主面91a。也就是说，本变形例所涉及的高频模块1A具有构成高频模块1A的电路元件和部件安装于单面的结构。
即使是该结构，低噪声放大器40与阻抗匹配电路62也沿与安装基板91的主面91a垂直的方向(z轴方向)进行层叠，因此能够节省安装基板91的安装面的面积，能够使高频模块1A小型化。另外，低噪声放大器40与阻抗匹配电路62沿z轴方向进行层叠，因此能够缩短将低噪声放大器40与阻抗匹配电路62连接的布线。由此，能够减少在上述布线中产生的寄生电容，因此能够高精度地执行低噪声放大器40与其前级的电路元件(开关12、接收滤波器21R及22R)之间的阻抗匹配。因此，能够抑制从低噪声放大器40输出的高频接收信号的接收灵敏度的劣化。并且，构成高频模块1A的电路元件和部件安装于单面，因此能够降低高频模块1A的高度。
[4变形例2所涉及的高频模块1B的电路元件配置结构]
图4是实施方式的变形例2所涉及的高频模块1B的截面概要图。该图所示的高频模块1B与实施方式所涉及的高频模块1相比在以下方面不同：构成第一层叠体的低噪声放大器40与阻抗匹配电路62A的层叠顺序相反；功率放大器30以及阻抗匹配电路61A及62A的上表面从树脂构件暴露出来。下面，关于本变形例所涉及的高频模块1B，省略与实施方式所涉及的高频模块1相同的结构的说明，以不同的结构为中心来进行说明。
如图4所示，低噪声放大器40与阻抗匹配电路62A沿与安装基板91的主面91a垂直的方向(z轴方向)进行层叠。另外，低噪声放大器40与阻抗匹配电路62A层叠而成的第一层叠体安装于主面91a。
阻抗匹配电路62A配置于将开关12与低噪声放大器40连结的路径，取得接收滤波器21R及22R的输出阻抗与低噪声放大器40的输入阻抗之间的匹配。阻抗匹配电路62A包括与低噪声放大器40连接的电感器(第一电感器)。
阻抗匹配电路61A配置于将开关11与接收滤波器22R连结的路径，取得天线2及开关11与接收滤波器22R之间的阻抗匹配。阻抗匹配电路61A包括与开关11连接的电感器(第二电感器)。
阻抗匹配电路62A是第一电感器集成安装于第二基板的内部或表面而成的第一集成型无源元件(第一IPD)。
阻抗匹配电路61A是第二电感器集成安装于第三基板的内部或表面而成的第二集成型无源元件(第二IPD)。
如图4所示，低噪声放大器40与阻抗匹配电路62A沿与安装基板91的主面91a垂直的方向(z轴方向)进行层叠。在剖视安装基板91的情况下，低噪声放大器40配置于安装基板91与阻抗匹配电路62A之间。也就是说，阻抗匹配电路62A配置于低噪声放大器40的上方(z轴正方向)。
另外，如图4所示，开关11与阻抗匹配电路61A沿与安装基板91的主面91a垂直的方向(z轴方向)进行层叠。在剖视安装基板91的情况下，开关11配置于安装基板91与阻抗匹配电路61A之间。也就是说，阻抗匹配电路61A配置于开关11的上方(z轴正方向)。
在此，功率放大器30、阻抗匹配电路61A及62A从树脂构件92的顶面(z轴正方向侧的面)暴露出来。
在上述的第一层叠体中，低噪声放大器40的输入端子形成于第一基板的上表面，第一电感器的端子形成于阻抗匹配电路62A的下表面，低噪声放大器40的输入端子与第一电感器的上述端子例如经由凸块电极进行连接。另外，低噪声放大器40的输出端子形成于低噪声放大器40的下表面，低噪声放大器40的输出端子与主面91a例如经由凸块电极进行连接。
在上述的第二层叠体中，第二电感器的端子形成于第三基板的下表面，开关11的一个端子形成于开关11的上表面，第二电感器的端子与开关11的上述一个端子例如经由凸块电极进行连接。另外，开关11的其它端子形成于开关11的下表面，开关11的上述其它端子与主面91a例如经由凸块电极进行连接。
根据上述结构，在阻抗匹配电路61A及62A各自的上表面未形成凸块电极，因此通过将该各自的上表面配置于高频模块1B的外表面，能够研磨该外表面，能够降低高频模块1B的高度。此外，即使研磨阻抗匹配电路61A及62A等集成型无源元件的主面来使其变薄，阻抗匹配电路61A及62A等集成型无源元件的特性的变化与低噪声放大器40和开关11等有源元件的特性的变化相比也少。
[5变形例3所涉及的高频模块1C的电路元件配置结构]
图5是实施方式的变形例3所涉及的高频模块1C的截面概要图。该图所示的高频模块1C与变形例2所涉及的高频模块1B相比在以下方面不同：具有屏蔽电极层80。下面，关于本变形例所涉及的高频模块1C，省略与变形例2所涉及的高频模块1B相同的结构的说明，以不同的结构为中心来进行说明。
高频模块1C还具备屏蔽电极层80，该屏蔽电极层80以覆盖树脂构件92及93的顶面和侧面的方式形成，与安装基板91内的地电极图案91G连接。
屏蔽电极层80例如是通过溅射或蒸镀Ag等金属等的真空成膜法来形成的、或者是通过旋涂导电性膏来形成的。屏蔽电极层80与形成于安装基板91的地电极图案91G在安装基板91的侧面进行连接。
根据上述结构，能够切断从高频模块1C的外部侵入的不需要的波，因此能够抑制模块特性的变动。另外，通过使屏蔽电极层80与功率放大器30的上表面接触，来自功率放大器30的发热能够经由屏蔽电极层80放出到高频模块1C的外部，因此能够提高散热性。
[6变形例4所涉及的高频模块1D的电路元件配置结构]
图6是实施方式的变形例4所涉及的高频模块1D的截面概要图。该图所示的高频模块1D与变形例2所涉及的高频模块1B相比在以下方面不同：第一层叠体和阻抗匹配电路62C安装于主面91b，双工器21安装于主面91a。下面，关于本变形例所涉及的高频模块1D，省略与变形例2所涉及的高频模块1B相同的结构的说明，以不同的结构为中心来进行说明。
功率放大器30和阻抗匹配电路52安装于主面91a，第一层叠体(低噪声放大器40和阻抗匹配电路62A)安装于主面91b。
阻抗匹配电路62C配置于将开关12与低噪声放大器40连结的路径，取得接收滤波器21R及22R的输出阻抗与低噪声放大器40的输入阻抗之间的匹配。也就是说，在本变形例中，阻抗匹配电路62A及62C配置于将开关12与低噪声放大器40连结的路径。阻抗匹配电路62C例如是芯片状的电感器。
此外，在本变形例中，也可以没有阻抗匹配电路62C。
另外，在本变形例中，在图6的截面图中未示出接收滤波器22R，但是接收滤波器22R可以配置于主面91a及91b中的任一方。
根据上述结构，低噪声放大器40与功率放大器30分别被分配并安装到安装基板91的主面91a及91b。另外，阻抗匹配电路62A及62C与阻抗匹配电路52分别被分配并安装到安装基板91的主面91b及91a。
由此，低噪声放大器40、阻抗匹配电路62A及62C与功率放大器30及阻抗匹配电路52隔着安装基板91分开距离，因此高频模块1D内的发送接收之间的隔离度进一步提高。
并且，通过将第一层叠体的上表面与树脂构件93的表面一起进行研磨，能够在主面91a侧和主面91b侧这两方都降低高频模块1D的高度。
[7变形例5所涉及的高频模块1E的电路元件配置结构]
图7是实施方式的变形例5所涉及的高频模块1E的截面概要图。该图所示的高频模块1E与变形例4所涉及的高频模块1D相比在以下方面不同：规定了构成各阻抗匹配电路的电感器的磁通方向。下面，关于本变形例所涉及的高频模块1E，省略与变形例4所涉及的高频模块1D相同的结构的说明，以不同的结构为中心来进行说明。
阻抗匹配电路61D配置于将开关11与接收滤波器22R连结的路径，取得天线2及开关11与接收滤波器22R之间的阻抗匹配。阻抗匹配电路61D包括与开关11连接的电感器(第二电感器)。阻抗匹配电路61D是第二电感器集成安装于第三基板的内部或表面而成的第二集成型无源元件(第二IPD)。
阻抗匹配电路62E配置于将开关12与低噪声放大器40连结的路径，取得接收滤波器21R及22R的输出阻抗与低噪声放大器40的输入阻抗之间的匹配。阻抗匹配电路62E包括与低噪声放大器40连接的电感器(第一电感器)。阻抗匹配电路62E是第一电感器集成安装于第二基板的内部或表面而成的第一集成型无源元件(第一IPD)。
阻抗匹配电路62D配置于将开关12与低噪声放大器40连结的路径，取得接收滤波器21R及22R的输出阻抗与低噪声放大器40的输入阻抗之间的匹配。也就是说，在本变形例中，阻抗匹配电路62E及62D配置于将开关12与低噪声放大器40连结的路径。阻抗匹配电路62D例如是芯片状的电感器。此外，在本变形例中，也可以没有阻抗匹配电路62D。
阻抗匹配电路52D配置于将功率放大器30与发送滤波器21T连结的路径，取得功率放大器30的输出阻抗与发送滤波器21T的输入阻抗之间的匹配。在本变形例中，阻抗匹配电路52D包括与功率放大器30连接的电感器(第三电感器)。
在此，阻抗匹配电路62E的第一电感器的磁通方向和阻抗匹配电路62D的电感器的磁通方向是与主面91b垂直的方向。与此相对，阻抗匹配电路52D的第三电感器的磁通方向是与主面91a平行的方向。
阻抗匹配电路52D的第三电感器的、呈螺旋状地卷绕的线圈导体的卷绕轴为与主面91a平行的方向。另外，阻抗匹配电路62D的电感器的、呈螺旋状地卷绕的线圈导体的卷绕轴为与主面91b垂直的方向。另外，阻抗匹配电路62E的第一电感器具有螺旋状的平面线圈导体，其卷绕轴为与主面91b垂直的方向。
根据上述结构，阻抗匹配电路62E的第一电感器的磁通方向及阻抗匹配电路62D的电感器的磁通方向与阻抗匹配电路52D的第三电感器的磁通方向正交，因此它们之间的磁场耦合得到抑制。因此，能够抑制发送电路与接收电路之间的不需要的耦合，能够抑制接收信号的接收灵敏度由于来自发送电路的不需要的波而发生劣化。
在本变形例中，进一步地，阻抗匹配电路61D的第二电感器的磁通方向是与主面91a垂直的方向。阻抗匹配电路61D的第二电感器具有螺旋状的平面线圈导体，其卷绕轴为与主面91a垂直的方向。
据此，阻抗匹配电路61D的第二电感器的磁通方向与阻抗匹配电路52D的第三电感器的磁通方向正交，因此它们之间的磁场耦合得到抑制。因此，能够进一步抑制不需要的波从发送电路向接收电路侵入，因此能够抑制接收信号的接收灵敏度劣化。
此外，本变形例所涉及的各阻抗匹配电路的电感器的磁通方向的规定也能够应用于实施方式所涉及的高频模块1和变形例1～4所涉及的高频模块。即，也可以是，构成发送电路的阻抗匹配电路52的第三电感器的磁通方向是与主面91a及91b平行的方向，构成接收电路的阻抗匹配电路62、62A、62C、62D、62E的第一电感器和阻抗匹配电路61、61A、61D的第二电感器的磁通方向是与主面91a及91b垂直的方向。
(其它实施方式等)
以上，关于本发明的实施方式所涉及的高频模块和通信装置，列举实施方式及其变形例来进行了说明，但是本发明所涉及的高频模块和通信装置不限定于上述实施方式及其变形例。将上述实施方式及其变形例中的任意的结构要素进行组合来实现的其它实施方式、对上述实施方式及其变形例实施本领域技术人员在不脱离本发明的宗旨的范围内想到的各种变形来得到的变形例、内置有上述高频模块和通信装置的各种设备也包含在本发明中。
例如，在上述实施方式及其变形例所涉及的高频模块和通信装置中，也可以在附图中公开的对各电路元件以及信号路径进行连接的路径之间插入其它的电路元件和布线等。
产业上的可利用性
本发明作为配置于支持多频段的前端部的高频模块，能够广泛利用于便携式电话等通信设备。

Claims (12)

1.一种高频模块，具备：
安装基板；
低噪声放大器，其包括放大元件，放大高频信号；以及
第一集成型无源元件，其包括集成化的第一电感器，
其中，所述第一电感器与所述低噪声放大器的输入端子连接，
所述低噪声放大器与所述第一集成型无源元件沿与所述安装基板的主面垂直的方向进行层叠，所述低噪声放大器与所述第一集成型无源元件层叠而成的第一层叠体安装于所述主面。
2.根据权利要求1所述的高频模块，其特征在于，
所述低噪声放大器具有第一基板，所述放大元件被安装于所述第一基板，
所述第一集成型无源元件具有第二基板，所述第一电感器被集成安装于所述第二基板，
所述第一基板和所述第二基板由硅形成。
3.根据权利要求1或2所述的高频模块，其特征在于，
所述第一电感器是用于取得在所述低噪声放大器的前级配置的电路元件的输出阻抗与所述低噪声放大器的输入阻抗之间的匹配的阻抗匹配元件。
4.根据权利要求1～3中的任一项所述的高频模块，其特征在于，还具备：
功率放大器，其对高频信号进行功率放大；以及
第三电感器，其与所述功率放大器的输出端子连接，以不与所述功率放大器层叠的方式安装于所述主面。
5.根据权利要求4所述的高频模块，其特征在于，还具备：
输入输出端子，其输入输出高频信号；以及
开关，其对用于传输向所述低噪声放大器输入的高频信号的信号路径与所述输入输出端子之间的连接以及用于传输从所述功率放大器输出的高频信号的信号路径与所述输入输出端子之间的连接进行切换，
在俯视所述主面的情况下，所述开关配置于所述功率放大器与所述第一层叠体之间。
6.根据权利要求5所述的高频模块，其特征在于，
还具备第二集成型无源元件，所述第二集成型无源元件包括集成化的第二电感器，
所述开关与所述第二集成型无源元件沿与所述主面垂直的方向进行层叠，所述开关与所述第二集成型无源元件层叠而成的第二层叠体安装于所述安装基板。
7.根据权利要求6所述的高频模块，其特征在于，
还具备树脂构件，所述树脂构件配置于所述主面，覆盖所述功率放大器、所述第一层叠体以及所述第二层叠体中的至少一部分，
在剖视所述安装基板的情况下，所述低噪声放大器配置于所述安装基板与所述第一集成型无源元件之间，
在剖视所述安装基板的情况下，所述开关配置于所述安装基板与所述第二集成型无源元件之间，
所述功率放大器、所述第一集成型无源元件以及所述第二集成型无源元件从所述树脂构件的顶面暴露出来。
8.根据权利要求7所述的高频模块，其特征在于，
还具备屏蔽电极层，所述屏蔽电极层以覆盖所述树脂构件的顶面和侧面的方式形成，与所述安装基板内的地电极连接。
9.根据权利要求4～8中的任一项所述的高频模块，其特征在于，
所述第一电感器的磁通方向是与所述主面垂直的方向，
所述第三电感器的磁通方向是与所述主面平行的方向。
10.根据权利要求4～9中的任一项所述的高频模块，其特征在于，
所述安装基板具有相互背对的第一主面和第二主面，
所述功率放大器和所述第三电感器安装于所述第一主面，
所述第一层叠体安装于所述第二主面。
11.根据权利要求1～6中的任一项所述的高频模块，其特征在于，
在剖视所述安装基板的情况下，所述第一集成型无源元件配置于所述安装基板与所述低噪声放大器之间。
12.一种通信装置，具备：
RF信号处理电路，其对利用天线元件发送接收的高频信号进行处理；以及
根据权利要求1～11中的任一项所述的高频模块，其在所述天线元件与所述RF信号处理电路之间传递所述高频信号。
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