CN114551367B - Semiconductor device with parallel structure - Google Patents
Semiconductor device with parallel structure Download PDFInfo
- Publication number
- CN114551367B CN114551367B CN202011325784.7A CN202011325784A CN114551367B CN 114551367 B CN114551367 B CN 114551367B CN 202011325784 A CN202011325784 A CN 202011325784A CN 114551367 B CN114551367 B CN 114551367B
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- Prior art keywords
- chip
- chip set
- substrate
- connecting sheet
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 238000004806 packaging method and process Methods 0.000 claims abstract description 28
- 239000004593 Epoxy Substances 0.000 claims abstract description 23
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 17
- 238000005476 soldering Methods 0.000 claims abstract description 17
- 238000005452 bending Methods 0.000 claims abstract description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 238000003466 welding Methods 0.000 claims description 7
- 230000035882 stress Effects 0.000 abstract description 8
- 230000008646 thermal stress Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Abstract
The invention discloses a semiconductor device with a parallel structure, which comprises a chip substrate, a first chip set and a second chip set, wherein the chip substrate is coated by an epoxy packaging body; the lower electrode of the first chip set is connected with the upper surface of the second connecting sheet through a soldering tin layer, and the first connecting sheet comprises an upper lap joint end connected with the first chip set, a lower lap joint end connected with the chip substrate and a bending part used for connecting the upper lap joint end and the lower lap joint end. The invention fully utilizes the three-dimensional space, increases the thickness of the product, reduces the structural stress of the chip and the risk of damage under the thermal stress while realizing the packaging of the high-power chip.
Description
Technical Field
The invention relates to the technical field of power semiconductor products, in particular to a semiconductor device with a parallel structure.
Background
In recent years, the trend of miniaturization and light weight of power semiconductor products is more and more remarkable. For products with parallel structures, the existing packaging structure generally places chips side by side, is limited by the length and width dimensions of the products, is difficult to package chips with larger dimensions, and limits the improvement of the power density of the products.
Disclosure of Invention
The invention aims to provide a semiconductor device with a parallel structure, which fully utilizes a three-dimensional space, increases the thickness of a product, realizes the packaging of a high-power chip, and reduces the structural stress of the chip and the risk of damage under thermal stress.
In order to achieve the above purpose, the invention adopts the following technical scheme: the semiconductor device with the parallel structure comprises a chip substrate, a first chip set and a second chip set, wherein the chip substrate is covered by an epoxy packaging body, the first chip set and the second chip set are overlapped on the chip substrate, the second chip set is positioned below the first chip set, and a lower electrode of the second chip set is electrically connected with the chip substrate;
one end of the chip substrate extends outwards from the epoxy packaging body to serve as a first terminal, the other end of the chip substrate positioned in the epoxy packaging body is connected with an upper electrode of the first chip set through a first connecting sheet, and one end of the first connecting sheet, far away from the first chip set, is bent downwards and is connected with the chip substrate;
two surfaces of a second connecting sheet with one end positioned between the first chip set and the second chip set are correspondingly and electrically connected with a lower electrode of the first chip set and an upper electrode of the second chip set, the other end of the second connecting sheet is bent downwards and connected with a substrate, and one end of the substrate, which is far away from the second connecting sheet, extends outwards from the epoxy packaging body to serve as a second terminal;
the lower electrode of the second chip set is electrically connected with the chip substrate through a metal block, so that the first chip set and the second chip set are positioned at the middle part of the epoxy packaging body in the thickness direction;
the lower electrode of the first chip set is connected with the upper surface of the second connecting sheet through a soldering tin layer, and a strip-shaped groove is formed on the upper surface of the second connecting sheet and positioned on the outer side of the soldering tin layer;
the first connecting piece comprises an upper lap joint end part connected with the first chip group, a lower lap joint end part connected with the chip substrate and a bending part used for connecting the upper lap joint end part and the lower lap joint end part, and one end of the chip substrate connected with the first connecting piece is provided with an upward inclined bending part and a horizontal lap joint part used for being connected with the lower lap joint end part of the first connecting piece.
The further improved scheme in the technical scheme is as follows:
1. in the above scheme, the two side edges of the horizontal lap joint part are respectively provided with an upward flanging part, and the lower lap joint end part is connected between the two flanging parts.
2. In the above scheme, the metal block is a copper block.
3. In the above scheme, the strip-shaped groove is positioned at one side of the soldering tin layer close to the substrate.
4. In the above scheme, the first connecting piece is provided with a avoidance through hole for the second connecting piece to pass through, or the second connecting piece is provided with a avoidance through hole for the first connecting piece to pass through.
5. In the above scheme, the chip substrate is a tin-plated copper substrate.
6. In the above scheme, the first chip set and the second chip set are formed by welding at least two chips through soldering tin.
7. In the scheme, the first connecting piece and the second connecting piece are copper connecting pieces.
Due to the application of the technical scheme, compared with the prior art, the invention has the following advantages and effects:
1. the semiconductor device with the parallel structure of the invention stacks two chips or chip groups, realizes the parallel connection of circuits through the two connecting sheets, fully utilizes the three-dimensional space, increases the thickness of products, reduces the structural stress of the chips and the risk of damage under the thermal stress while realizing the encapsulation of high-power chips; further, the lower electrode of the second chip set is electrically connected with the chip substrate through a metal block, so that the first chip set and the second chip set are positioned in the middle of the thickness direction of the epoxy packaging body, the chip set is positioned in the thickness center of the packaging body, the structural stress of the product is further reduced, and the stability of the product in the use process is improved.
2. The semiconductor device with the parallel structure is characterized in that the lower electrode of the first chip set is connected with the upper surface of the second connecting sheet through the soldering tin layer, the upper surface of the second connecting sheet is provided with at least one strip-shaped groove positioned on the outer side of the soldering tin layer, and the arrangement of the groove structure can effectively prevent the chip set from generating larger position deviation in the high-temperature welding process, thereby improving the positioning precision of the chip and avoiding the risk of short circuit caused by touching the internal structure of the device together; in addition, the first connecting piece comprises an upper lap joint end part connected with the first chip group, a lower lap joint end part connected with the chip substrate and a bending part used for connecting the upper lap joint end part and the lower lap joint end part, one end of the chip substrate connected with the first connecting piece is provided with an upward inclined bending part and a horizontal lap joint part used for connecting the lower lap joint end part of the first connecting piece, and the stability of connection between the first connecting piece and the chip substrate can be improved, the structural stress of the chip group can be reduced, the position deviation of internal components such as chips or connecting pieces in the high-temperature welding process can be physically limited, and the risk of short circuit is reduced; further, the two side edges of the horizontal lap joint part are respectively provided with an upward flanging part, the lower lap joint end part is connected between the two flanging parts, and the connecting piece is limited through the two flanging parts, so that the short circuit risk caused by position deviation of the connecting piece is further reduced.
Drawings
Fig. 1 is a schematic structural diagram of a semiconductor device having a parallel structure according to the present invention;
FIG. 2 is a cross-sectional view of the structure of FIG. 1;
fig. 3 is an enlarged view of the structure at a in fig. 2.
In the above figures: 1. an epoxy encapsulation; 2. a chip substrate; 21. a first terminal; 22. an inclined bending part; 23. a horizontal overlap; 24. a burring part; 3. a first chipset; 4. a second chipset; 5. a first connecting piece; 51. upper overlapping end portions; 52. a lower overlap end; 53. a bending part; 6. a second connecting piece; 7. a substrate; 71. a second terminal; 8. a metal block; 9. a solder layer; 10. a strip-shaped groove.
Detailed Description
In the description of this patent, it should be noted that, directions or positional relationships indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., are based on directions or positional relationships shown in the drawings, are merely for convenience of description and simplification of description, and do not indicate or imply that the apparatus or element in question must have a specific direction, be configured and operated in a specific direction, and thus should not be construed as limiting the invention; the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; furthermore, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in this patent will be understood by those of ordinary skill in the art in a specific context.
Example 1: the semiconductor device with the parallel structure comprises a chip substrate 2, a first chip set 3 and a second chip set 4, wherein the chip substrate 2 is covered by an epoxy packaging body 1, the first chip set 3 and the second chip set 4 are overlapped on the chip substrate 2, the second chip set 4 is positioned below the first chip set 3, and a lower electrode of the second chip set 4 is electrically connected with the chip substrate 2;
one end of the chip substrate 2 extends outwards from the inside of the epoxy packaging body 1 to serve as a first terminal 21, the other end of the chip substrate 2 positioned in the epoxy packaging body 1 is connected with an upper electrode of the first chip set 3 through a first connecting sheet 5, and one end of the first connecting sheet 5 far away from the first chip set 3 is bent downwards and connected with the chip substrate 2;
two surfaces of a second connecting sheet 6 with one end positioned between the first chip set 3 and the second chip set 4 are correspondingly and electrically connected with a lower electrode of the first chip set 3 and an upper electrode of the second chip set 4, the other end of the second connecting sheet 6 is bent downwards and connected with a substrate 7, and one end of the substrate 7 far away from the second connecting sheet 6 extends outwards from the inside of the epoxy packaging body 1 to serve as a second terminal 71;
the lower electrode of the second chip set 4 is electrically connected with the chip substrate 2 through a metal block 8, so that the first chip set 3 and the second chip set 4 are positioned at the middle part of the epoxy packaging body 1 in the thickness direction;
the lower electrode of the first chip set 3 is connected with the upper surface of the second connecting sheet 6 through a soldering tin layer 9, and a strip-shaped groove 10 is formed on the upper surface of the second connecting sheet 6 and positioned at the outer side of the soldering tin layer 9;
the first connecting piece 5 includes an upper overlap end 51 connected to the first chip set 3, a lower overlap end 52 connected to the chip substrate 2, and a bent portion 53 for connecting the upper overlap end 51 and the lower overlap end 52, and one end of the chip substrate 2 connected to the first connecting piece 5 has an upward inclined bent portion 22 and a horizontal overlap portion 23 for connecting the lower overlap end 52 of the first connecting piece 5.
The two side edges of the horizontal lap joint part 23 are provided with an upward flanging part 24, and the lower lap joint end part 52 is connected between the two flanging parts 24; the first connecting piece 5 is provided with a clearance through hole for the second connecting piece 6 to pass through, or the second connecting piece 6 is provided with a clearance through hole for the first connecting piece 5 to pass through.
Example 2: the semiconductor device with the parallel structure comprises a chip substrate 2, a first chip set 3 and a second chip set 4, wherein the chip substrate 2 is covered by an epoxy packaging body 1, the first chip set 3 and the second chip set 4 are overlapped on the chip substrate 2, the second chip set 4 is positioned below the first chip set 3, and a lower electrode of the second chip set 4 is electrically connected with the chip substrate 2;
one end of the chip substrate 2 extends outwards from the inside of the epoxy packaging body 1 to serve as a first terminal 21, the other end of the chip substrate 2 positioned in the epoxy packaging body 1 is connected with an upper electrode of the first chip set 3 through a first connecting sheet 5, and one end of the first connecting sheet 5 far away from the first chip set 3 is bent downwards and connected with the chip substrate 2;
two surfaces of a second connecting sheet 6 with one end positioned between the first chip set 3 and the second chip set 4 are correspondingly and electrically connected with a lower electrode of the first chip set 3 and an upper electrode of the second chip set 4, the other end of the second connecting sheet 6 is bent downwards and connected with a substrate 7, and one end of the substrate 7 far away from the second connecting sheet 6 extends outwards from the inside of the epoxy packaging body 1 to serve as a second terminal 71;
the lower electrode of the second chip set 4 is electrically connected with the chip substrate 2 through a metal block 8, so that the first chip set 3 and the second chip set 4 are positioned at the middle part of the epoxy packaging body 1 in the thickness direction;
the lower electrode of the first chip set 3 is connected with the upper surface of the second connecting sheet 6 through a soldering tin layer 9, and a strip-shaped groove 10 is formed on the upper surface of the second connecting sheet 6 and positioned at the outer side of the soldering tin layer 9;
the first connecting piece 5 includes an upper overlap end 51 connected to the first chip set 3, a lower overlap end 52 connected to the chip substrate 2, and a bent portion 53 for connecting the upper overlap end 51 and the lower overlap end 52, and one end of the chip substrate 2 connected to the first connecting piece 5 has an upward inclined bent portion 22 and a horizontal overlap portion 23 for connecting the lower overlap end 52 of the first connecting piece 5.
The metal block 8 is a copper block; the strip-shaped groove 10 is positioned on one side of the soldering tin layer 9 close to the substrate 7; the chip substrate 2 is a tin-plated copper substrate; the first chip set 3 and the second chip set 4 are formed by welding at least two chips through soldering tin; the first connecting piece 5 and the second connecting piece 6 are copper connecting pieces.
When the semiconductor device with the parallel structure is adopted, two chips or chip groups are stacked and placed, and then the parallel connection of the circuits is realized through the two connecting sheets, so that the three-dimensional space is fully utilized, the thickness of a product is increased, the packaging of a high-power chip is realized, and meanwhile, the structural stress of the chip and the risk of damage under the thermal stress are reduced;
furthermore, the chip set is positioned in the thickness center of the package, so that the structural stress of the product is further reduced, and the stability of the product in the use process is improved;
in addition, the arrangement of the groove structure can effectively prevent the chip group from larger position deviation in the high-temperature welding process, thereby improving the positioning precision of the chip and avoiding the risk of short circuit caused by touching the internal structure of the device together;
in addition, through the bending and lap joint between the first connecting sheet and the chip substrate, the stability of connection between the first connecting sheet and the chip substrate can be improved, the structural stress of a chip set can be reduced, the position deviation of internal components such as a chip or a connecting sheet in the high-temperature welding process can be physically limited, and the risk of short circuit is reduced;
furthermore, the connecting piece is limited through the two flanging parts, so that the short circuit risk caused by position deviation of the connecting piece is further reduced.
The above embodiments are provided to illustrate the technical concept and features of the present invention and are intended to enable those skilled in the art to understand the content of the present invention and implement the same, and are not intended to limit the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.
Claims (8)
1. A semiconductor device of parallel structure, characterized in that: the packaging structure comprises a chip substrate (2) coated by an epoxy packaging body (1), a first chip set (3) and a second chip set (4), wherein the first chip set (3) and the second chip set (4) are superposed on the chip substrate (2), the second chip set (4) is positioned below the first chip set (3), and a lower electrode of the second chip set (4) is electrically connected with the chip substrate (2);
one end of the chip substrate (2) extends outwards from the inside of the epoxy packaging body (1) to serve as a first terminal (21), the other end of the chip substrate (2) positioned in the epoxy packaging body (1) is connected with an upper electrode of the first chip set (3) through a first connecting sheet (5), and one end of the first connecting sheet (5) far away from the first chip set (3) is bent downwards and connected with the chip substrate (2);
two surfaces of a second connecting sheet (6) with one end positioned between the first chip set (3) and the second chip set (4) are correspondingly and electrically connected with a lower electrode of the first chip set (3) and an upper electrode of the second chip set (4), the other end of the second connecting sheet (6) is bent downwards and connected with a substrate (7), and one end of the substrate (7) far away from the second connecting sheet (6) extends outwards from the inside of the epoxy packaging body (1) to serve as a second terminal (71);
the lower electrode of the second chip set (4) is electrically connected with the chip substrate (2) through a metal block (8), so that the first chip set (3) and the second chip set (4) are positioned at the middle part of the epoxy packaging body (1) in the thickness direction;
the lower electrode of the first chip set (3) is connected with the upper surface of the second connecting sheet (6) through a soldering tin layer (9), and a strip-shaped groove (10) is formed on the upper surface of the second connecting sheet (6) and positioned at the outer side of the soldering tin layer (9);
the first connecting piece (5) comprises an upper lap end part (51) connected with the first chip group (3), a lower lap end part (52) connected with the chip substrate (2) and a bending part (53) used for connecting the upper lap end part (51) and the lower lap end part (52), and one end of the chip substrate (2) connected with the first connecting piece (5) is provided with an upward inclined bending part (22) and a horizontal lap part (23) used for being connected with the lower lap end part (52) of the first connecting piece (5).
2. The semiconductor device of claim 1, wherein: the two side edges of the horizontal lap joint part (23) are respectively provided with an upward flanging part (24), and the lower lap joint end part (52) is connected between the two flanging parts (24).
3. The semiconductor device of claim 1, wherein: the metal block (8) is a copper block.
4. The semiconductor device of claim 1, wherein: the strip-shaped groove (10) is positioned on one side of the soldering tin layer (9) close to the substrate (7).
5. The semiconductor device of claim 1, wherein: the first connecting sheet (5) is provided with a avoidance through hole for the second connecting sheet (6) to pass through, or the second connecting sheet (6) is provided with a avoidance through hole for the first connecting sheet (5) to pass through.
6. The semiconductor device of claim 1 or 5, wherein: the chip substrate (2) is a tin-plated copper substrate.
7. The semiconductor device of claim 1 or 5, wherein: the first chip set (3) and the second chip set (4) are formed by welding at least two chips through soldering tin.
8. The semiconductor device of claim 1 or 5, wherein: the first connecting piece (5) and the second connecting piece (6) are copper connecting pieces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011325784.7A CN114551367B (en) | 2020-11-24 | 2020-11-24 | Semiconductor device with parallel structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011325784.7A CN114551367B (en) | 2020-11-24 | 2020-11-24 | Semiconductor device with parallel structure |
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| Publication Number | Publication Date |
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| CN114551367A CN114551367A (en) | 2022-05-27 |
| CN114551367B true CN114551367B (en) | 2024-03-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202011325784.7A Active CN114551367B (en) | 2020-11-24 | 2020-11-24 | Semiconductor device with parallel structure |
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| CN (1) | CN114551367B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015097955A1 (en) * | 2013-12-26 | 2015-07-02 | アピックヤマダ株式会社 | Lead frame, substrate for led package, reflector member, led package, light emitting device, light emitting system, method for manufacturing substrate for led package, and method for manufacturing led package |
| CN106449536A (en) * | 2016-03-25 | 2017-02-22 | 苏州固锝电子股份有限公司 | Anti-surge surface mounting semiconductor device |
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2020
- 2020-11-24 CN CN202011325784.7A patent/CN114551367B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015097955A1 (en) * | 2013-12-26 | 2015-07-02 | アピックヤマダ株式会社 | Lead frame, substrate for led package, reflector member, led package, light emitting device, light emitting system, method for manufacturing substrate for led package, and method for manufacturing led package |
| CN106449536A (en) * | 2016-03-25 | 2017-02-22 | 苏州固锝电子股份有限公司 | Anti-surge surface mounting semiconductor device |
Non-Patent Citations (1)
| Title |
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| 李莉 ; 马孝松 ; 周喜 ; .超薄芯片叠层封装器件热可靠性分析.电子元件与材料.2010,(01),全文. * |
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| CN114551367A (en) | 2022-05-27 |
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