CN215578510U - Power device of multilayer chip - Google Patents
Power device of multilayer chip Download PDFInfo
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- CN215578510U CN215578510U CN202121617135.4U CN202121617135U CN215578510U CN 215578510 U CN215578510 U CN 215578510U CN 202121617135 U CN202121617135 U CN 202121617135U CN 215578510 U CN215578510 U CN 215578510U
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- chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses a power device of a multilayer chip, which comprises a chip substrate, a connecting sheet and a chip group formed by stacking a plurality of chips, wherein the chip substrate is positioned in an epoxy packaging body, one end of the connecting sheet is a first welding part electrically connected with the chip group, the other end of the connecting sheet is a second welding part electrically connected with a lead strip, a bending part is arranged at the joint of the connecting part and the first welding part, so that the area of the connecting part close to the first welding part is higher than that of the first welding part, metal sheets are respectively arranged between the chip group and the connecting sheet and between the chip group and adjacent chips in the chip group, the area of each metal sheet is larger than that of each chip, the edge of each metal sheet is positioned on the outer side of the periphery of each chip, and the edges around the metal sheets are provided with a depressed part along the vertical direction. The utility model can reduce the stress generated by expansion, greatly reduce the damage of structural stress to the chip, improve the reliability of the product and the yield of processing, and reduce the production cost.
Description
Technical Field
The utility model relates to the field of semiconductor packaging, in particular to a power device of a multilayer chip.
Background
The high-power TVS product is mainly used for lightning surge current protection, and has higher requirements on the reliability and the power density of the product. The existing product has the following defects: the product has larger structural stress, the reliability can not meet the requirement of higher grade, and the yield is lower, which brings higher manufacturing cost.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a power device of a multilayer chip, which can reduce stress generated by expansion, greatly reduce damage of structural stress to the chip, improve the reliability of a product and the yield of processing, and reduce the production cost.
In order to achieve the purpose, the utility model adopts the technical scheme that: a power device of a multilayer chip comprises a chip substrate, a connecting sheet and a chip group, wherein the chip substrate is positioned in an epoxy packaging body, the chip group is formed by stacking a plurality of chips, and the chip group is positioned above the chip substrate and is electrically connected with the chip substrate;
one end of the connecting sheet is a first welding part electrically connected with the chip set, the other end of the connecting sheet is a second welding part electrically connected with a lead bar, the first welding part and the second welding part are connected through a connecting part with a bend, the connecting part of the connecting part and the first welding part is provided with a bend, so that the area of the connecting part close to the first welding part is higher than the first welding part, and the horizontal area of the connecting part close to the first welding part is provided with a through hole;
all be provided with a sheetmetal between chipset and connection piece, the metal base and in the chipset between the adjacent chip, the area of sheetmetal is greater than the area of chip for the edge of sheetmetal is located the outside of chip circumference, sheetmetal edge all around has a depressed part along vertical direction.
The further improved scheme in the technical scheme is as follows:
1. in the above scheme, a metal base electrically connected with the chip set and the chip substrate is arranged between the chip set and the chip substrate.
2. In the above scheme, the upper and lower surfaces of the metal base are respectively connected with the chip set and the chip substrate through solder paste.
3. In the above scheme, the metal base is a copper base.
4. In the above scheme, the upper and lower surfaces of the metal sheet are provided with the concave parts.
5. In the above scheme, the first welding portion is higher than the second welding portion, one end of the horizontal connecting area of the connecting portion is connected with the first welding portion, one end of the inclined connecting area of the connecting portion is connected with the second welding portion, and the through hole is formed in the middle of the horizontal connecting area of the connecting portion.
Due to the application of the technical scheme, compared with the prior art, the utility model has the following advantages and effects:
1. on the basis of meeting the requirement of power density, the power device of the multilayer chip can reduce the resistance of liquid epoxy during injection molding, and ensure the structural uniformity and stability of the molded epoxy packaging body, thereby ensuring the integral reliability of the product; in addition, a metal sheet is arranged between the chip group and the connecting sheet and between the chip group and the adjacent chips, the area of the metal sheet is larger than that of the chip, so that the edge of the metal sheet is positioned at the outer side of the circumferential direction of the chip, the epoxy stress can be effectively prevented from directly acting on the chip, and the stability of the performance of the chip is kept in the complex environment and long-time use process; furthermore, the edge all around of the metal sheet is provided with a concave part along the vertical direction, so that the edge of the metal sheet is thinned, the metal sheet can be effectively prevented from deviating from the edge of the chip, the epoxy can be conveniently filled, the epoxy can be filled between adjacent metal sheets and between the metal sheets and the chip completely and uniformly without holes, the stability of the insulating property is ensured, the short circuit and other conditions in the long-term use process are avoided, and the reliability of the product is further improved.
2. According to the power device of the multilayer chip, the connecting part of the connecting part and the first welding part is provided with the bend, so that the area of the connecting part close to the first welding part is higher than that of the first welding part, and the welding area of the connecting sheet and the chip group is positioned near the geometric center of the product in the horizontal direction, so that the generation of stress can be reduced, the damage of structural stress to the chip can be avoided, and the reliability of the product and the processing yield are further improved; in addition, a metal base which is respectively electrically connected with the chip group and the chip substrate is arranged between the chip group and the chip substrate, and the position of the chip group in the vertical direction is raised through the metal base, so that the chip group is positioned near the geometric center of the thickness of a product, the stress generated by thermal expansion can be reduced, the damage of the structural stress to the chip can be greatly reduced, the reliability of the product and the processing yield can be improved, and the production cost can be reduced.
Drawings
FIG. 1 is a top view of a power device with a multi-layered chip according to the present invention;
FIG. 2 is a cross-sectional side view of a power device of the multi-layered chip of the present invention;
fig. 3 is a partial structural top view of a power device of a multi-layered chip according to the present invention.
In the above drawings: 1. a chip substrate; 2. connecting sheets; 21. a first weld; 22. a second weld; 23. a connecting portion; 3. a through hole; 4. a chipset; 41. a chip; 5. an epoxy package; 6. bending; 7. a metal sheet; 71. a recessed portion; 8. a metal base; 9. and (4) leading the lines.
Detailed Description
The utility model is further described with reference to the following figures and examples:
example 1: a power device of a multilayer chip comprises a chip substrate 1 positioned in an epoxy packaging body 5, a connecting sheet 2 and a chip group 4 formed by stacking a plurality of chips 41, wherein the chip group 4 is positioned above the chip substrate 1 and is electrically connected with the chip substrate 1;
one end of the connecting sheet 2 is a first welding part 21 electrically connected with the chip group 4, the other end is a second welding part 22 electrically connected with a lead wire 9, the first welding part 21 and the second welding part 22 are connected through a connecting part 23 with a bend, the connecting part 23 and the first welding part 21 are provided with a bend 6, so that the area of the connecting part 23 close to the first welding part 21 is higher than the first welding part 21, and the horizontal area of the connecting part 23 close to the first welding part 21 is provided with a through hole 3;
a metal sheet 7 is arranged between the chip group 4 and the connecting sheet 2 and the metal base 8 and between adjacent chips 41 in the chip group 4, the area of the metal sheet 7 is larger than or approximately equal to that of the chip 41, so that the edge of the metal sheet 7 is positioned near the outer side of the periphery of the chip 41, and a concave part 71 along the vertical direction is arranged at the edge of the periphery of the metal sheet 7.
A metal base 8 which is respectively and electrically connected with the chip group 4 and the chip substrate 1 is arranged between the chip group 4 and the chip substrate 1;
the first welding portion 21 is higher than the second welding portion 22, one end of a horizontal connection region of the connecting portion 23 is connected to the first welding portion 21, one end of an inclined connection region of the connecting portion 23 is connected to the second welding portion 22, and the through hole 3 is opened in the middle of the horizontal connection region of the connecting portion 23.
Example 2: a power device of a multilayer chip comprises a chip substrate 1 positioned in an epoxy packaging body 5, a connecting sheet 2 and a chip group 4 formed by stacking a plurality of chips 41, wherein the chip group 4 is positioned above the chip substrate 1 and is electrically connected with the chip substrate 1;
one end of the connecting sheet 2 is a first welding part 21 electrically connected with the chip group 4, the other end is a second welding part 22 electrically connected with a lead wire 9, the first welding part 21 and the second welding part 22 are connected through a connecting part 23 with a bend, the connecting part 23 and the first welding part 21 are provided with a bend 6, so that the area of the connecting part 23 close to the first welding part 21 is higher than the first welding part 21, and the horizontal area of the connecting part 23 close to the first welding part 21 is provided with a through hole 3;
a metal sheet 7 is arranged between the chip group 4 and the connecting sheet 2 and the metal base 8 and between adjacent chips 41 in the chip group 4, the area of the metal sheet 7 is larger than or approximately equal to that of the chip 41, so that the edge of the metal sheet 7 is positioned near the outer side of the periphery of the chip 41, and a concave part 71 along the vertical direction is arranged at the edge of the periphery of the metal sheet 7.
The upper surface and the lower surface of the metal base 8 are respectively connected with the chip group 4 and the chip substrate 1 through soldering pastes; the metal base 8 is a copper base; the metal sheet 7 has the recessed portions 71 on both the upper and lower surfaces thereof;
one end of the lead wire 9 extends out of the epoxy packaging body 5 to be used as a pin; the chip group 4 is formed by stacking 3 chips 41.
When the power device of the multilayer chip is adopted, on the basis of meeting the requirement of power density, the resistance of liquid epoxy during injection molding can be reduced, and the structural uniformity and stability of the formed epoxy packaging body are ensured, so that the integral reliability of a product is ensured;
in addition, a metal sheet is arranged between the chip group and the connecting sheet and between the chip group and the adjacent chips, the area of the metal sheet is larger than that of the chip, so that the edge of the metal sheet is positioned at the outer side of the circumferential direction of the chip, the epoxy stress can be effectively prevented from directly acting on the chip, and the stability of the performance of the chip is kept in the complex environment and long-time use process;
furthermore, the edges of the metal sheets are provided with the concave parts along the vertical direction, so that the edges of the metal sheets are thinned, the edge of the chip can be effectively prevented from deviating from the metal sheets, the epoxy filling is facilitated, the epoxy filling between the adjacent metal sheets and between the metal sheets and the chip is full and uniform without holes, the stability of the insulating property is ensured, the situations of short circuit and the like in the long-term use process are avoided, and the reliability of the product is further improved;
in addition, the connection part of the connecting part and the first welding part is provided with a bend, so that the area of the connecting part close to the first welding part is higher than the first welding part, and the welding area of the connecting sheet and the chip set is positioned near the geometric center of the product in the horizontal direction, thereby reducing the generation of stress, avoiding the damage of structural stress to the chip, and further improving the reliability of the product and the processing yield;
in addition, a metal base which is respectively electrically connected with the chip group and the chip substrate is arranged between the chip group and the chip substrate, and the position of the chip group in the vertical direction is raised through the metal base, so that the chip group is positioned near the geometric center of the thickness of a product, the stress generated by thermal expansion can be reduced, the damage of the structural stress to the chip can be greatly reduced, the reliability of the product and the processing yield can be improved, and the production cost can be reduced.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (6)
1. A multilayer chip power device, comprising: the packaging structure comprises a chip substrate (1) positioned in an epoxy packaging body (5), a connecting sheet (2) and a chip set (4) formed by stacking a plurality of chips (41), wherein the chip set (4) is positioned above the chip substrate (1) and is electrically connected with the chip substrate (1);
one end of the connecting sheet (2) is a first welding part (21) electrically connected with the chip group (4), the other end of the connecting sheet is a second welding part (22) electrically connected with a lead bar (9), the first welding part (21) is connected with the second welding part (22) through a connecting part (23) with a bend, the connecting part (23) is provided with a bend (6) at the connecting part with the first welding part (21), so that the area of the connecting part (23) close to the first welding part (21) is higher than the first welding part (21), and a through hole (3) is formed in the horizontal area of the connecting part (23) close to the first welding part (21);
all be provided with a sheetmetal (7) between chipset (4) and connection piece (2), metal base (8) and in chipset (4) between adjacent chip (41), the area of sheetmetal (7) is greater than the area of chip (41) for the edge of sheetmetal (7) is located the outside of chip (41) circumference, sheetmetal (7) edge all around has a depressed part (71) along vertical direction.
2. The multilayer chip power device of claim 1, wherein: and a metal base (8) which is respectively and electrically connected with the chip group (4) and the chip substrate (1) is arranged between the chip group (4) and the chip substrate (1).
3. The multilayer chip power device of claim 2, wherein: the upper surface and the lower surface of the metal base (8) are respectively connected with the chip group (4) and the chip substrate (1) through soldering paste.
4. The multilayer chip power device of claim 2, wherein: the metal base (8) is a copper base.
5. The multilayer chip power device of any one of claims 1 to 4, wherein: the metal sheet (7) has the recessed portions (71) on both the upper and lower surfaces thereof.
6. The multilayer chip power device of any one of claims 1 to 4, wherein: the first welding portion (21) is higher than the second welding portion (22), one end of a horizontal connecting area of the connecting portion (23) is connected with the first welding portion (21), one end of an inclined connecting area of the connecting portion (23) is connected with the second welding portion (22), and the through hole (3) is formed in the middle of the horizontal connecting area of the connecting portion (23).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121617135.4U CN215578510U (en) | 2021-07-16 | 2021-07-16 | Power device of multilayer chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121617135.4U CN215578510U (en) | 2021-07-16 | 2021-07-16 | Power device of multilayer chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215578510U true CN215578510U (en) | 2022-01-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202121617135.4U Active CN215578510U (en) | 2021-07-16 | 2021-07-16 | Power device of multilayer chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215578510U (en) |
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2021
- 2021-07-16 CN CN202121617135.4U patent/CN215578510U/en active Active
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