CN217035628U - Power semiconductor device with miniaturized design - Google Patents
Power semiconductor device with miniaturized design Download PDFInfo
- Publication number
- CN217035628U CN217035628U CN202220677626.6U CN202220677626U CN217035628U CN 217035628 U CN217035628 U CN 217035628U CN 202220677626 U CN202220677626 U CN 202220677626U CN 217035628 U CN217035628 U CN 217035628U
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- China
- Prior art keywords
- horizontal part
- chip
- packaging body
- power semiconductor
- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The utility model discloses a power semiconductor device with miniaturized design, wherein one end of the other end of a right pin positioned outside an epoxy packaging body extends into the epoxy packaging body and is connected with a connecting sheet, the other end of a left pin positioned outside the epoxy packaging body extends into the epoxy packaging body and is connected with a chip substrate, and the connecting sheet further comprises: the chip comprises a first horizontal part electrically connected with a chip positioned on the top layer, a second horizontal part positioned right above the edge of the chip and an extension part bent downwards from one end of the second horizontal part, which is opposite to the first horizontal part, wherein the lower end of the extension part, which is far away from the second horizontal part, is connected with a right pin, the second horizontal part is higher than the first horizontal part, so that a bending part is formed between the second horizontal part and the first horizontal part, and a through hole is formed in the region, connected with the chip, of the horizontal part. The utility model can increase the thickness and uniformity of epoxy filling at the edge of the chip, ensure the yield of products and reduce the risks of electric leakage and the like in the using process.
Description
Technical Field
The utility model relates to the technical field of semiconductor packaging, in particular to a power semiconductor device with a miniaturized design.
Background
With the rapid development of integrated circuits, especially ultra-large scale integrated circuits, the size of the high power semiconductor package structure is smaller and smaller, and at the same time, the power of the chip in the high power semiconductor package structure is larger and larger, so that the heat flow density in the high power semiconductor package structure is increased. The inside structure that is multilayer chip interval copper sheet of existing product reaches the stress between the buffering chip and increases the heat dispersion's purpose, and the problem that brings from this is that product thickness is than thicker.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a power semiconductor device with a miniaturized design, which reduces the thickness of a product on the basis of ensuring the power and the performance of the product.
In order to achieve the purpose, the utility model adopts the technical scheme that: a power semiconductor device of miniaturized design, comprising: the chip comprises a chip substrate coated by an epoxy packaging body, at least 2 chips and a connecting sheet which are stacked, wherein the adjacent 2 chips are connected through a first soldering tin layer, the other end of a right pin with one end positioned outside the epoxy packaging body extends into the epoxy packaging body and is connected with the connecting sheet, and the other end of a left pin with one end positioned outside the epoxy packaging body extends into the epoxy packaging body and is connected with the chip substrate;
the connecting piece further includes: the chip comprises a first horizontal part, a second horizontal part and an extension part, wherein the first horizontal part is electrically connected with the chip on the top layer, the second horizontal part is positioned right above the edge of the chip, the extension part is bent downwards from one end, back to the first horizontal part, of the second horizontal part, the lower end, far away from the second horizontal part, of the extension part is connected with a right pin, the second horizontal part is higher than the first horizontal part, a bending part is formed between the second horizontal part and the first horizontal part, and a through hole is formed in a region, connected with the chip, of the horizontal part.
The further improved scheme in the technical scheme is as follows:
1. in the above scheme, the through hole is a circular through hole.
2. In the above solution, the through hole is located in the center of the region where the horizontal portion is connected to the chip.
3. In the scheme, the thickness of the first soldering tin layer is 0.05 mm-0.1 mm.
4. In the above scheme, the lower end of the extension part is provided with a lap joint area extending along the horizontal direction, and the lap joint area is connected with the right pin.
5. In the above scheme, the left pin and the chip substrate are of an integrated structure.
Due to the application of the technical scheme, compared with the prior art, the utility model has the following advantages and effects:
1. according to the power semiconductor device with the miniaturized design, the connecting sheet is provided with the first horizontal part electrically connected with the chip positioned on the top layer, the second horizontal part positioned right above the edge of the chip and the extending part which is bent downwards from one end of the second horizontal part, which is opposite to the first horizontal part, the lower end of the extending part, which is far away from the second horizontal part, is connected with the right pin, and the second horizontal part is higher than the first horizontal part, so that a bending part is formed between the second horizontal part and the first horizontal part, the thickness of a product is reduced on the basis of ensuring the power and the performance of the product, the condition that the chip is damaged due to the fact that the connecting sheet is in direct contact with the edge of the chip can be avoided, the thickness and the uniformity of epoxy filling at the edge of the chip can be increased, the yield of the product is ensured, and the risks such as electric leakage in the using process are reduced.
2. According to the power semiconductor device with the miniaturized design, the through hole is formed in the area where the horizontal part is connected with the chip, the thickness of local epoxy is increased through the arrangement of the through hole in the connecting piece, the risk of incomplete epoxy injection molding filling of a thin layer on the upper surface of a product is reduced, and the performance of the product is guaranteed.
Drawings
FIG. 1 is a cross-sectional elevation view of a power semiconductor device of the miniaturized design of the present invention;
FIG. 2 is an enlarged view of FIG. 1 at A;
fig. 3 is a top view of a miniaturized power semiconductor device in accordance with the present invention.
In the drawings above: 1. an epoxy package; 2. a chip substrate; 3. a chip; 41. a first solder layer; 5. a right pin; 6. a left pin; 7. a through hole; 8. connecting sheets; 81. a first horizontal portion; 82. a second horizontal portion; 83. an extension portion; 84. a bending part; 85. a lap zone.
Detailed Description
The utility model is further described below with reference to the following figures and examples:
example 1: a power semiconductor device of miniaturized design, comprising: the chip packaging structure comprises a chip substrate 2 coated by an epoxy packaging body 1, at least 2 chips 3 and a connecting sheet 8 which are stacked, wherein the adjacent 2 chips 3 are connected through a first soldering tin layer 41, the other end of a right pin 5 with one end positioned outside the epoxy packaging body 1 extends into the epoxy packaging body 1 and is connected with the connecting sheet 8, and the other end of a left pin 6 with one end positioned outside the epoxy packaging body 1 extends into the epoxy packaging body 1 and is connected with the chip substrate 2; the connecting piece 8 further comprises: the chip package structure comprises a first horizontal part 81 electrically connected with a chip 3 positioned on a top layer, a second horizontal part 82 positioned right above the edge of the chip 3 and an extension part 83 bent downwards from one end of the second horizontal part 82 opposite to the first horizontal part 81, wherein the lower end of the extension part 83 far away from the second horizontal part 82 is connected with a right pin 5, the second horizontal part 82 is higher than the first horizontal part 81, a bent part 84 is formed between the second horizontal part 82 and the first horizontal part 81, and a through hole 7 is formed in the region where the horizontal part 81 is connected with the chip 3.
The thickness of the first solder layer 41 is 0.05 mm-0.1 mm, so that structural stress between chips can be effectively buffered, and the stability of product performance is improved.
The lower end of the extension 83 has a lap zone extending in the horizontal direction, and the lap zone is connected to the right lead 5.
The left pin 6 and the chip substrate 2 are integrally formed.
Example 2: a power semiconductor device of miniaturized design, comprising: the chip packaging structure comprises a chip substrate 2 coated by an epoxy packaging body 1, at least 2 chips 3 and a connecting sheet 8 which are stacked, wherein the adjacent 2 chips 3 are connected through a first soldering tin layer 41, the other end of a right pin 5 with one end positioned outside the epoxy packaging body 1 extends into the epoxy packaging body 1 and is connected with the connecting sheet 8, and the other end of a left pin 6 with one end positioned outside the epoxy packaging body 1 extends into the epoxy packaging body 1 and is connected with the chip substrate 2; the connecting piece 8 further includes: the chip package structure comprises a first horizontal part 81 electrically connected with a chip 3 positioned on a top layer, a second horizontal part 82 positioned right above the edge of the chip 3 and an extension part 83 bent downwards from one end of the second horizontal part 82 opposite to the first horizontal part 81, wherein the lower end of the extension part 83 far away from the second horizontal part 82 is connected with a right lead 5, the second horizontal part 82 is higher than the first horizontal part 81, so that a bent part 84 is formed between the second horizontal part 82 and the first horizontal part 81, and a through hole 7 is formed in the region where the horizontal part 81 is connected with the chip 3.
The through-hole 7 is a circular through-hole.
The through-hole 7 is located at the center of the region where the horizontal portion 81 is connected to the chip 3.
The thickness of the first soldering tin layer 41 is 0.05 mm-0.1 mm, so that structural stress between chips can be effectively buffered, and the stability of product performance is improved.
The lower end of the extension 83 has a lap zone 85 extending in the horizontal direction, and the lap zone 85 is connected to the right lead 5.
When the power semiconductor device with the miniaturized design is adopted, the connecting sheet is provided with a first horizontal part electrically connected with a chip positioned on the top layer, a second horizontal part positioned right above the edge of the chip and an extending part bent downwards from one end of the second horizontal part, which is opposite to the first horizontal part, the lower end of the extending part, which is far away from the second horizontal part, is connected with a right pin, and the second horizontal part is higher than the first horizontal part, so that a bending part is formed between the second horizontal part and the first horizontal part, the thickness of a product is reduced on the basis of ensuring the power and the performance of the product, the condition that the chip is damaged due to the direct contact of the connecting sheet and the edge of the chip can be avoided, the thickness and the uniformity of epoxy filling at the edge of the chip can be increased, the yield of the product is ensured, and the risks such as electric leakage in the use process are reduced; its one end is located the other end of the right pin in the epoxy packaging body outside and stretches into in the epoxy packaging body and be connected with the connection piece, the other end that one end is located the left pin in the epoxy packaging body outside stretches into in the epoxy packaging body and with the chip base plate, horizontal part has a through-hole with regional the opening of chip connection, guaranteeing product power, on the basis of performance, the thickness of attenuate product, and through the connection piece on the setting up of through-hole increase local epoxy thickness, reduce because of the product upper surface thin layer epoxy risk that the filling is discontented of moulding plastics, guarantee the performance of product.
The above embodiments are only for illustrating the technical idea and features of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the content of the present invention and implement the present invention, and not to limit the protection scope of the present invention by this means. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (6)
1. A power semiconductor device of miniaturized design, comprising: the chip packaging structure comprises a chip substrate (2) coated by an epoxy packaging body (1), at least 2 chips (3) and a connecting sheet (8) which are stacked, wherein the adjacent 2 chips (3) are connected through a first soldering tin layer (41), the other end of a right pin (5) with one end positioned outside the epoxy packaging body (1) extends into the epoxy packaging body (1) and is connected with the connecting sheet (8), and the other end of a left pin (6) with one end positioned outside the epoxy packaging body (1) extends into the epoxy packaging body (1) and is connected with the chip substrate (2);
the method is characterized in that: the connecting piece (8) further comprises: the chip structure comprises a first horizontal part (81) electrically connected with a chip (3) on the top layer, a second horizontal part (82) located right above the edge of the chip (3) and an extension part (83) bent downwards from one end, opposite to the first horizontal part (81), of the second horizontal part (82), the lower end, away from the second horizontal part (82), of the extension part (83) is connected with a right pin (5), the second horizontal part (82) is higher than the first horizontal part (81), so that a bending part (84) is formed between the second horizontal part (82) and the first horizontal part (81), and a through hole (7) is formed in a connecting area of the horizontal part (81) and the chip (3).
2. The power semiconductor device of miniaturized design of claim 1, characterized in that: the through hole (7) is a circular through hole.
3. The power semiconductor device of miniaturized design of claim 1, characterized in that: the through hole (7) is positioned in the center of the area where the horizontal part (81) is connected with the chip (3).
4. The power semiconductor device of miniaturized design of claim 1, characterized in that: the thickness of the first soldering tin layer (41) is 0.05 mm-0.1 mm.
5. The miniaturized design of power semiconductor device of claim 1, wherein: the lower end of the extension part (83) is provided with a lap joint area (85) extending along the horizontal direction, and the lap joint area (85) is connected with the right pin (5).
6. The miniaturized design of power semiconductor device of claim 1, wherein: the left pin (6) and the chip substrate (2) are of an integrated structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220677626.6U CN217035628U (en) | 2022-03-25 | 2022-03-25 | Power semiconductor device with miniaturized design |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220677626.6U CN217035628U (en) | 2022-03-25 | 2022-03-25 | Power semiconductor device with miniaturized design |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217035628U true CN217035628U (en) | 2022-07-22 |
Family
ID=82412181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220677626.6U Active CN217035628U (en) | 2022-03-25 | 2022-03-25 | Power semiconductor device with miniaturized design |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217035628U (en) |
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2022
- 2022-03-25 CN CN202220677626.6U patent/CN217035628U/en active Active
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