CN215578513U - High power semiconductor device - Google Patents
High power semiconductor device Download PDFInfo
- Publication number
- CN215578513U CN215578513U CN202121617177.8U CN202121617177U CN215578513U CN 215578513 U CN215578513 U CN 215578513U CN 202121617177 U CN202121617177 U CN 202121617177U CN 215578513 U CN215578513 U CN 215578513U
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- China
- Prior art keywords
- chip
- chips
- sheet
- semiconductor device
- power semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses a high-power semiconductor device, which comprises a chip substrate, a connecting sheet and a chip group, wherein the chip substrate is positioned in an epoxy packaging body, the chip group is formed by stacking a plurality of chips, the chip group is positioned above the chip substrate, a metal base arranged between the chip group and the chip substrate is respectively and electrically connected with the chip group and the chip substrate, one end of the connecting sheet is electrically connected with the chip group, and the other end of the connecting sheet extends outwards from the epoxy packaging body and is used as a pin area; a metal sheet is arranged between adjacent chips, and the area of the metal sheet is larger than or approximately equal to that of the chips, so that the edge of the metal sheet is positioned near the outer side of the periphery of the chips. On the basis of meeting the requirement of power density, the utility model improves the reliability of products and the yield of processing and reduces the production cost.
Description
Technical Field
The utility model relates to the field of semiconductor packaging, in particular to a high-power semiconductor device.
Background
The high-power TVS product is mainly used for lightning surge current protection, and has higher requirements on the reliability and the power density of the product. The existing product has the following defects: the product has larger structural stress, the reliability can not meet the requirement of higher grade, and the yield is lower, which brings higher manufacturing cost.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a high-power semiconductor device, which improves the reliability of products and the processing yield and reduces the production cost on the basis of meeting the requirement of power density.
In order to achieve the purpose, the utility model adopts the technical scheme that: a high-power semiconductor device comprises a chip substrate, a connecting sheet and a chip group, wherein the chip substrate is positioned in an epoxy packaging body, the chip group is formed by stacking a plurality of chips, the chip group is positioned above the chip substrate, a metal base arranged between the chip group and the chip substrate is respectively and electrically connected with the chip group and the chip substrate, one end of the connecting sheet is electrically connected with the chip group, and the other end of the connecting sheet extends outwards from the epoxy packaging body and is used as a pin area;
a metal sheet is arranged between adjacent chips, and the area of the metal sheet is larger than that of the chips, so that the edge of the metal sheet is positioned on the outer side of the circumferential direction of the chips.
The further improved scheme in the technical scheme is as follows:
1. in the above scheme, the metal sheet is a copper sheet or a molybdenum sheet.
2. In the above scheme, the metal sheets are arranged between the chip set and the connecting sheet and between the chip set and the metal base.
3. In the above scheme, the upper and lower surfaces of the metal base are respectively connected with the chip set and the chip substrate through solder paste.
4. In the above scheme, the chip set is formed by stacking at least 3 chips.
Due to the application of the technical scheme, compared with the prior art, the utility model has the following advantages and effects:
according to the high-power semiconductor device, on the basis of meeting the requirement of power density, the position of the chip group in the vertical direction is raised through the metal base, so that the chip group is positioned near the geometric center of the thickness of a product, the stress generated by thermal expansion can be reduced, the damage of structural stress to a chip can be greatly reduced, the reliability of the product and the processing yield are improved, and the production cost is reduced; in addition, a metal sheet is arranged between adjacent chips, the area of the metal sheet is larger than that of the chips, so that the edge of the metal sheet is positioned on the outer side of the circumferential direction of the chips, the epoxy stress can be effectively prevented from directly acting on the chips, and the stability of the performance of the chips is kept in the complex environment and long-time use process.
Drawings
FIG. 1 is a top view of a high power semiconductor device according to the present invention;
FIG. 2 is a cross-sectional side view of a high power semiconductor device in accordance with the present invention;
fig. 3 is a partial structural top view of the high power semiconductor device of the present invention.
In the above drawings: 1. a chip substrate; 2. connecting sheets; 21. a pin area; 4. a chipset; 41. a chip; 5. an epoxy package; 7. a metal sheet; 8. a metal base.
Detailed Description
The utility model is further described with reference to the following figures and examples:
example 1: a high-power semiconductor device comprises a chip substrate 1, a connecting sheet 2 and a chip group 4 formed by stacking a plurality of chips 41, wherein the chip group 4 is positioned above the chip substrate 1, a metal base 8 arranged between the chip group 4 and the chip substrate 1 is respectively electrically connected with the chip group 4 and the chip substrate 1, one end of the connecting sheet 2 is electrically connected with the chip group 4, and the other end of the connecting sheet 2 extends outwards from the epoxy packaging body 5 to be used as a pin area 21;
a metal sheet 7 is disposed between adjacent chips 41, and the area of the metal sheet 7 is larger than or approximately equal to the area of the chips 41, so that the edge of the metal sheet 7 is located near the outer side of the periphery of the chips 41.
The metal sheet 7 is a molybdenum sheet; the metal sheets 7 are arranged between the chip group 4 and the connecting sheet 2 and between the chip group and the metal base 8; the chip group 4 is formed by stacking 4 chips 41.
Example 2: a high-power semiconductor device comprises a chip substrate 1, a connecting sheet 2 and a chip group 4 formed by stacking a plurality of chips 41, wherein the chip group 4 is positioned above the chip substrate 1, a metal base 8 arranged between the chip group 4 and the chip substrate 1 is respectively electrically connected with the chip group 4 and the chip substrate 1, one end of the connecting sheet 2 is electrically connected with the chip group 4, and the other end of the connecting sheet 2 extends outwards from the epoxy packaging body 5 to be used as a pin area 21;
a metal sheet 7 is arranged between adjacent chips 41, and the area of the metal sheet 7 is slightly larger than that of the chips 41, so that the edge of the metal sheet 7 is located on the outer side of the circumferential direction of the chip 41.
The metal sheet 7 is a copper sheet; the upper surface and the lower surface of the metal base 8 are respectively connected with the chip group 4 and the chip substrate 1 through soldering pastes; the chip group 4 is formed by stacking 3 chips 41.
When the high-power semiconductor device is adopted, on the basis of meeting the requirement of power density, the position of the chip group in the vertical direction is raised through the metal base, so that the chip group is positioned near the geometric center of the thickness of a product, the stress generated by thermal expansion can be reduced, the damage of structural stress to a chip can be greatly reduced, the reliability of the product and the processing yield are improved, and the production cost is reduced; in addition, a metal sheet is arranged between adjacent chips, the area of the metal sheet is larger than that of the chips, so that the edge of the metal sheet is positioned on the outer side of the circumferential direction of the chips, the epoxy stress can be effectively prevented from directly acting on the chips, and the stability of the performance of the chips is kept in the complex environment and long-time use process.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (5)
1. A high power semiconductor device, characterized by: the packaging structure comprises a chip substrate (1) positioned in an epoxy packaging body (5), a connecting sheet (2) and a chip set (4) formed by stacking a plurality of chips (41), wherein the chip set (4) is positioned above the chip substrate (1), a metal base (8) arranged between the chip set (4) and the chip substrate (1) is respectively electrically connected with the chip set (4) and the chip substrate (1), one end of the connecting sheet (2) is electrically connected with the chip set (4), and the other end of the connecting sheet (2) extends outwards from the epoxy packaging body (5) to serve as a pin area (21);
a metal sheet (7) is arranged between the adjacent chips (41), and the area of the metal sheet (7) is larger than that of the chips (41), so that the edge of the metal sheet (7) is positioned on the outer side of the periphery of the chips (41).
2. The high power semiconductor device according to claim 1, wherein: the metal sheet (7) is a copper sheet or a molybdenum sheet.
3. The high power semiconductor device according to claim 1, wherein: the metal sheets (7) are arranged between the chip set (4) and the connecting sheet (2) and between the chip set and the metal base (8).
4. The high power semiconductor device according to claim 1, wherein: the upper surface and the lower surface of the metal base (8) are respectively connected with the chip group (4) and the chip substrate (1) through soldering paste.
5. The high power semiconductor device according to claim 1, wherein: the chip group (4) is formed by stacking at least 3 chips (41).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121617177.8U CN215578513U (en) | 2021-07-16 | 2021-07-16 | High power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121617177.8U CN215578513U (en) | 2021-07-16 | 2021-07-16 | High power semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215578513U true CN215578513U (en) | 2022-01-18 |
Family
ID=79826083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202121617177.8U Active CN215578513U (en) | 2021-07-16 | 2021-07-16 | High power semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215578513U (en) |
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2021
- 2021-07-16 CN CN202121617177.8U patent/CN215578513U/en active Active
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