CN114496745A - 制造半导体装置的方法 - Google Patents

制造半导体装置的方法 Download PDF

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CN114496745A
CN114496745A CN202111210535.8A CN202111210535A CN114496745A CN 114496745 A CN114496745 A CN 114496745A CN 202111210535 A CN202111210535 A CN 202111210535A CN 114496745 A CN114496745 A CN 114496745A
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bonding layer
wafer
bonding
layer
conductive feature
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黄圣富
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Nanya Technology Corp
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Abstract

一种制造半导体装置的方法包括：在第一晶圆上形成第一接合层，并在第一接合层上形成蚀刻遮罩；使用蚀刻遮罩蚀刻第一接合层的边缘部，并暴露出第一晶圆的一部分；移除蚀刻遮罩；以及将第二晶圆固定于第一接合层。蚀刻遮罩并不只用于部分蚀刻第一接合层及第一晶圆，还用于保护接合层，使得接合层的表面能维持平滑。因此，在晶圆接合工艺中，接合层提供优异的接合效果，以便于将第二晶圆固定在第一晶圆上。

Description

制造半导体装置的方法
技术领域
本发明涉及一种制造半导体装置的方法。
背景技术
目前，三维集成电路(3D-IC)在半导体封装中具有广泛的应用及发展，其中多个半导体晶片相互堆叠，例如堆叠式封装技术(PoP)和系统级封装(SiP)封装技术。三维集成电路组件的一些优点包括所占用的空间更小以及通过减少信号互连的长度来降低功耗，进而提高产量和降低制造成本。
随着半导体技术发展，晶片与晶圆的接合或晶圆与晶圆的接合技术被应用于三维集成电路组件。举例来说，在晶圆与晶圆的接合技术中，目前已经开发了许多方法来将两个晶圆接合在一起。
因此，如何提供一种有效地晶圆接合技术，以校准晶圆与晶圆之间的位置，已成为重要课题之一。
发明内容
有鉴于此，本发明提供一种制造半导体装置的方法，包括：在第一晶圆上形成第一接合层，并在第一接合层上形成蚀刻遮罩；使用蚀刻遮罩蚀刻第一接合层的边缘部，并暴露出第一晶圆的一部分；移除蚀刻遮罩；以及将第二晶圆固定于第一接合层。
在本发明的一个或多个实施方式中，制造半导体装置的方法进一步包括：在第一晶圆上形成集成电路结构，其中集成电路结构位于第一晶圆及第一接合层之间。
在本发明的一个或多个实施方式中，集成电路结构包括基板及穿过基板的介层窗。
在本发明的一个或多个实施方式中，介层窗接触第一接合层的第一导电特征。
在本发明的一个或多个实施方式中，介层窗的宽度小于导电特征的宽度。
在本发明的一个或多个实施方式中，第一接合层包括介电层及穿过介电层的第一导电特征。
在本发明的一个或多个实施方式中，形成蚀刻遮罩包括：在第一接合层上形成光阻层；以及执行边缘修整工艺，以移除光阻层的边缘部。
在本发明的一个或多个实施方式中，将第二晶圆固定于第一接合层包括：使第二晶圆上的第二接合层接触第一接合层；以及结合第一接合层及第二接合层。
在本发明的一个或多个实施方式中，第一接合层内的第一导电特征接触第二接合层内的第二导电特征。
在本发明的一个或多个实施方式中，第一导电特征的宽度等于第二导电特征的宽度。
综上所述，蚀刻遮罩并不只用于部分蚀刻第一接合层及第一晶圆，还用于保护接合层，因此接合层的表面能维持平滑。因此，在晶圆接合(wafer-to-wafer)工艺中，第一晶圆及接合层能提供优异的接合效果。
以上所述仅用以阐述本发明所欲解决的问题、解决问题的技术手段、及其产生的功效等等，本发明的具体细节将在下文的实施方式及相关附图中详细介绍。
附图说明
为达成上述的优点和特征，将参考实施方式对上述简要描述的原理进行更具体的阐释，而具体实施方式被展现在附图中。这些附图仅例示性地描述本发明，因此不限制发明的范围。通过附图，将清楚解释本发明的原理，且附加的特征和细节将被完整描述，其中：
图1绘示为本发明一些实施方式中半导体装置的制造方法的流程图；以及
图2至图7绘示半导体装置的制造方法的各个步骤。
具体实施方式
以下将以附图揭露本发明的复数个实施方式，为明确说明起见，许多实务上的细节将在以下叙述中一并说明。然而，应了解到，这些实务上的细节不应用以限制本发明。也就是说，在本发明部分实施方式中，这些实务上的细节是非必要的。除此之外，为简化附图起见，一些现有惯用的结构与元件在附图中将以简单示意的方式绘示之。
请参考图1，图1绘示本发明一些实施方式中半导体装置的制造方法100。方法100起始于步骤110，其中步骤110包括在第一晶圆上形成第一接合层，并在第一接合层上形成蚀刻遮罩。接着，方法100进行至步骤130，其中步骤130包括使用蚀刻遮罩蚀刻第一接合层的边缘部，借此暴露出第一晶圆的一部分。接着，方法100进行至步骤150，其中步骤150包括移除蚀刻遮罩。方法100接续至步骤170，步骤170包括将第二晶圆固定于第一接合层。
图2至图7绘示本发明一些实施方式中半导体装置200的制造方法100的各个步骤截面图。图2至图4用以图形化地代表图1中的步骤110。请参考图2至图4，第一接合层230形成于第一晶圆210上，而蚀刻遮罩240形成于第一接合层上，因此第一接合层230设置于第一晶圆210及蚀刻遮罩240之间。具体而言，第一晶圆210可以为半导体基板，例如为经参杂(p型参杂或n型参杂)或未经参杂的块状半导体。在一些实施方式中，第一晶圆210为硅晶圆或其他适合的基板，例如是绝缘体上硅(semiconductor-on-insulator,SOI)基板、多层基板或梯度基板(gradient substrate)。第一晶圆210的半导体材料可包括硅(silicon)、锗(germanium)或化合物半导体，例如为碳化硅(silicon carbide)、砷化镓(galliumarsenic)、磷化镓(gallium phosphide)、磷化铟(indium phosphide)、砷化铟(indiumarsenide)、合金半导体或其组合。多种电子组件(例如为晶体管、电容)可以被使用并产生设计于第一晶圆210的结构和功能要求。在一些实施方式中，根据设计需求，第一晶圆210不具有穿透基材介层窗(through semiconductor vias)。在另外一些实施方式中，介层窗则被形成于第一晶圆210中。
在本发明的一些实施方式中，第一接合层230可包括第一介电层231和多个第一导电特征233，第一导电特征233延伸穿过第一介电层231，其中第一介电层231包覆第一导电特征233。第一介电层231包括介电材料，例如为氧化硅(silicon oxide)，第一介电层231可以被旋转涂布(spin-coating)、层压(laminating)或其他合适的沉积技术所制成，接着介电材料被图形化并形成第一介电层231，且第一介电层231具有多个开口(图未示)。举例而言，可以使用光刻及蚀刻工艺或其他适合的工艺以图形化第一介电层231。接着，在第一介电层231的多个开口中形成导电材料并形成第一导电特征233，其中第一导电特征233可以是经由电镀、沉积工艺、化学气相沉积工艺(chemical vapor deposition，CVD)、等离子体加强型化学沉积工艺(plasma-enhanced chemical vapor deposition，PECVD)、原子层沉积工艺(atomic layer deposition，ALD)或其他合适的沉积工艺，但本发明并不以此为限。
在本发明的一些实施方式中，形成蚀刻遮罩240包括：在第一接合层230上形成光阻层241；以及执行边缘修整工艺以移除光阻层241的边缘部241a。具体而言，边缘部241a包括边缘珠(edge bead)，其中包括晶圆边缘曝光工艺(wafer edge exposure，WEE)或边缘球状物移除工艺(edge bead removal，EBR)，例如为光学边缘球状物移除工艺或化学边缘球状物移除工艺，化学边缘球状物移除工艺包括将丙二醇甲醚醋酸酯(propylene glycolmethyl ether acetate，PGMEA)溶液或将乙二醇一甲基醚乙酸酯(ethyleneglycolmonomethyl ether acetate，EGMEA)溶液施加于光阻层241。蚀刻遮罩240可以为未图形化的光阻遮罩，但本发明并不以此为限。
在本发明的一些实施方式中，方法100还包括步骤120，步骤120实施于步骤130之前，其中步骤120包括将集成电路结构220形成于第一晶圆210上，且集成电路结构220设置于第一晶圆210及第一接合层230之间。具体而言，集成电路结构220包括逻辑晶片，例如中央处理器、图形化处理器或内存晶片(例如动态随机存取内存晶片或静态随机存取内存晶片等)、电源管理晶片、射频晶片、感测晶片、微机电系统晶片或其组合。在一些特定的实施方式中，记忆和/或电子控制功能可以整合在同一集成电路结构220。在一些实施方式中，集成电路结构220包括半导体基板221及多个穿透基材介层窗223(through semiconductorvia，TSV)，介层窗223则延伸穿过半导体基板221，但本发明并不以此为限。
在本发明的一些实施方式中，互连结构(interconnection structure)形成在第一晶圆210及集成电路结构220之间。在第一晶圆210内的介层窗223可通过互连结构电性连接于集成电路结构220的介层窗223。
在本发明的一些实施方式中，多个介层窗223分别电性连接于第一接合层230的多个第一导电特征233。举例而言，多个介层窗223分别接触第一接合层230的多个第一导电特征233，但本发明并不以此为限。
在本发明的一些实施方式中，每一介层窗223的宽度大于第一接合层230中每一第一导电特征233的宽度。在一些可替换的实施方式中，每一介层窗223的宽度大于每一第一导电特征233的宽度，但本发明并不以此为限。
请参考图4及图5。图4及图5可用于图形化地代表图1中的步骤130，步骤130包括使用蚀刻遮罩240以蚀刻和移除集成电路结构220的边缘部分235及第一接合层230的边缘部分235，借此暴露第一晶圆210的一部分。在本发明的一些实施方式中，边缘部分235及边缘部分235可以例如被干蚀刻的非等向性蚀刻工艺所移除。在一些实施方式中，干蚀刻可以为反应离子蚀刻工艺(reactive ion etch，RIE)、等离子体蚀刻工艺(plasma etch proces)或任何合适的蚀刻工艺，本发明并不以此为限。在一些例子中，蚀刻遮罩240可以至少保护第一接合层230不受非等向性蚀刻工艺所污染。因此，第一接合层230具有平滑表面，也就是说第一接合层230的表面上几乎没有缺陷。
请参考图5及图6，图5及图6可用于图形化地表示图1中的步骤150，其中步骤150包括移除蚀刻遮罩240。具体而言，可搭配终点检测实施平整化工艺(planarizationprocess)以移除蚀刻遮罩240，且平整化工艺可包括机械研磨工艺(mechanical grindingprocess)和/或化学机械研磨工艺(chemical mechanical polishing process，CMP)或其他合适的工艺，但本发明并不以此为限。
请参考图6及图7。图6及图7可用于图形化地表示图1中的步骤170，其中步骤170包括将第二晶圆310连接于第一接合层230，因此第一晶圆210及第二晶圆310相互连接并形成半导体装置200。第二晶圆310可以为硅晶圆、半导体基板(例如是经参杂或未经参杂的块状半导体基板)或其他合适的基板(例如，多层基板或梯度基板等)。在本发明的一些实施方式中，步骤170还包括：将第一接合层230接触第二晶圆310上的第二接合层330；以及将第一接合层230及第二接合层330相结合。第一接合层230及第二接合层330可以是使用混合键合工艺(hybrid bonding process)、熔融接合工艺(fusion bonding process)、直接接合工艺(direct bonding process)、介电接合工艺(dielectric bonding process)、金属接合工艺(metal bonding process)、焊接工艺(solder joints process)或其他合适的工艺相互结合。具体而言，可以将压力施加于第一晶圆210及第二晶圆310以稳固地相互结合，因此第一接合层230的第一导电特征233分别直接接触第二接合层330的多个第二导电特征333。举例而言，在第一介电层231与第二接合层330的第二介电层331经由介电接合(dielectric-to-dielectric bond)工艺结合之后，多个第一导电特征233与第二晶圆310的第二导电特征333经由金属接合(metal-to-metal)工艺所结合。在本发明的一些实施方式中，每一第一导电特征233的宽度对应于第二导电特征333的宽度，但本发明并不以此为限。
综上所述，蚀刻遮罩并不只用于部分蚀刻第一接合层及第一晶圆，还用于保护接合层，因此接合层的表面能维持平滑。因此，在晶圆接合工艺中，第一晶圆及接合层能提供优异的接合效果。
本发明不同实施方式已描述如上，应可理解的是不同实施方式仅作为实例来呈现，而不作为限定。在不脱离本发明的精神和范围下，可根据本文的揭露对本发明的实施方式做许多更动。因此，本发明的广度和范围不应受上述描述的实施例所限制。
【符号说明】
100:方法
110，120，130，150，170:步骤
200:半导体装置
210:第一晶圆
220:集成电路结构
221:基板
223:介层窗
230:第一接合层
231:第一介电层
233:第一导电特征
235:边缘部分
240:蚀刻遮罩
241:光阻层
241a:边缘部
310:第二晶圆
330:第二接合层
331:第二介电层
333:第二导电特征。

Claims (10)

1.一种制造半导体装置的方法，其特征在于，包括：
在第一晶圆上形成第一接合层，并在第一接合层上形成蚀刻遮罩；
使用该蚀刻遮罩蚀刻该第一接合层的边缘部，并暴露出该第一晶圆的一部分；
移除该蚀刻遮罩；以及
将第二晶圆固定于该第一接合层。
2.根据权利要求1所述的方法，其特征在于，进一步包括：
在该第一晶圆上形成集成电路结构，其中该集成电路结构位于该第一晶圆及该第一接合层之间。
3.根据权利要求2所述的方法，其特征在于，该集成电路结构包括基板及穿过该基板的介层窗。
4.根据权利要求3所述的方法，其特征在于，该介层窗接触该第一接合层的第一导电特征。
5.根据权利要求4所述的方法，其特征在于，该介层窗的宽度小于该第一导电特征的宽度。
6.根据权利要求1所述的方法，其特征在于，该第一接合层包括介电层及穿过该介电层的第一导电特征。
7.根据权利要求1所述的方法，其特征在于，形成该蚀刻遮罩包括：
在该第一接合层上形成光阻层；以及
执行边缘修整工艺，以移除该光阻层的边缘部。
8.根据权利要求1所述的方法，其特征在于，将该第二晶圆固定于该第一接合层包括：
使该第二晶圆上的第二接合层接触该第一接合层；以及
结合该第一接合层及该第二接合层。
9.根据权利要求8所述的方法，其特征在于，该第一接合层内的第一导电特征接触该第二接合层内的第二导电特征。
10.根据权利要求9所述的方法，其特征在于，该第一导电特征的宽度等于该第二导电特征的宽度。
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