TWI803013B - 製造半導體裝置的方法 - Google Patents

製造半導體裝置的方法 Download PDF

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TWI803013B
TWI803013B TW110137395A TW110137395A TWI803013B TW I803013 B TWI803013 B TW I803013B TW 110137395 A TW110137395 A TW 110137395A TW 110137395 A TW110137395 A TW 110137395A TW I803013 B TWI803013 B TW I803013B
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bonding layer
wafer
layer
conductive feature
bonding
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黃聖富
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南亞科技股份有限公司
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Abstract

一種製造半導體裝置的方法包括：在第一晶圓上形成第一接合層，並在第一接合層上形成蝕刻遮罩；使用蝕刻遮罩蝕刻第一接合層的邊緣部，並暴露出第一晶圓的一部分；移除蝕刻遮罩；以及將第二晶圓固定於第一接合層。

Description

製造半導體裝置的方法
本發明涉及一種製造半導體裝置的方法。
目前，三維積體電路 (3D-IC)在半導體封裝中具有廣泛的應用及發展，其中多個半導體晶片相互堆疊，例如堆疊式封裝技術(PoP) 和系統級封裝(SiP) 封裝技術。三維積體電路組件的一些優點包括所占用的空間更小以及通過減少信號互連的長度來降低功耗，進而提高產量和降低製造成本。
隨著半導體技術發展，晶片與晶圓的接合或晶圓與晶圓的接合技術被應用於三維積體電路組件。舉例來說，在晶圓與晶圓的接合技術中，目前已經開發了許多方法來將兩個晶圓接合在一起。
因此，如何提供一種有效地晶圓接合技術，以校準晶圓與晶圓之間的位置，已成為重要課題之一。
有鑑於此，本發明提供一種製造半導體裝置的方法，包括：在第一晶圓上形成第一接合層，並在第一接合層上形成蝕刻遮罩；使用蝕刻遮罩蝕刻第一接合層的邊緣部，並暴露出第一晶圓的一部分；移除蝕刻遮罩；以及將第二晶圓固定於第一接合層。
在本發明的一個或多個實施方式中，製造半導體裝置的方法進一步包括：在第一晶圓上形成積體電路結構，其中積體電路結構位於第一晶圓及第一接合層之間。
在本發明的一個或多個實施方式中，積體電路結構包括基板及穿過基板的介層窗。
在本發明的一個或多個實施方式中，介層窗接觸第一接合層的第一導電特徵。
在本發明的一個或多個實施方式中，介層窗的寬度小於導電特徵的寬度。
在本發明的一個或多個實施方式中，第一接合層包括介電層及穿過介電層的第一導電特徵。
在本發明的一個或多個實施方式中，形成蝕刻遮罩包括：在第一接合層上形成光阻層；以及執行邊緣修整製程，以移除光阻層的邊緣部。
在本發明的一個或多個實施方式中，將第二晶圓固定於第一接合層包括：使第二晶圓上的第二接合層接觸第一接合層；以及結合第一接合層及第二接合層。
在本發明的一個或多個實施方式中，第一接合層內的第一導電特徵接觸第二接合層內的第二導電特徵。
在本發明的一個或多個實施方式中，第一導電特徵的寬度等於第二導電特徵的寬度。
綜上所述，蝕刻遮罩並不只用於部分蝕刻第一接合層及第一晶圓，更用於保護接合層，因此接合層的表面能維持平滑。因此，在晶圓接合(wafer-to-wafer)製程中，第一晶圓及接合層能提供優異的接合效果。
以上所述僅係用以闡述本發明所欲解決的問題、解決問題的技術手段、及其產生的功效等等，本發明之具體細節將在下文的實施方式及相關圖式中詳細介紹。
以下將以圖式揭露本發明之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。除此之外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
請參考第1圖，第1圖繪示本發明一些實施方式中半導體裝置的製造方法100。方法100起始於步驟110，其中步驟110包括在第一晶圓上形成第一接合層，並在第一接合層上形成蝕刻遮罩。接著，方法100進行至步驟130，其中步驟130包括使用蝕刻遮罩蝕刻第一接合層的邊緣部，藉此暴露出第一晶圓的一部分。接著，方法100進行至步驟150，其中步驟150包括移除蝕刻遮罩。方法100接續至步驟170，步驟170包括將第二晶圓固定於第一接合層。
第2圖至第7圖繪示本發明一些實施方式中半導體裝置200的製造方法100的各個步驟截面圖。第2圖至第4圖用以圖形化地代表第1圖中的步驟110。請參考第2圖至第4圖，第一接合層230形成於第一晶圓210上，而蝕刻遮罩240形成於第一接合層230上，因此第一接合層230設置於第一晶圓210及蝕刻遮罩240之間。具體而言，第一晶圓210可以為半導體基板， 例如為經參雜(p型參雜或n型參雜)或未經參雜的塊狀半導體。在一些實施方式中，第一晶圓210為矽晶圓或其他適合的基板，例如是絕緣體上矽(semiconductor-on-insulator,SOI)基板、多層基板或梯度基板(gradient substrate)。第一晶圓210的半導體材料可包括矽(silicon)、鍺(germanium)或化合物半導體，例如為碳化矽(silicon carbide)、砷化镓(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)、合金半導體或其組合。多種電子組件(例如為電晶體、電容)可以被使用並產生設計於第一晶圓210的結構和功能要求。在一些實施方式中，根據設計需求，第一晶圓210不具有穿透基材介層窗(through semiconductor vias)。在另外一些實施方式中，介層窗則被形成於第一晶圓210中。
在本發明的一些實施方式中，第一接合層230可包括第一介電層231和多個第一導電特徵233，第一導電特徵233延伸穿過第一介電層231，其中第一介電層231包覆第一導電特徵233。第一介電層231包括介電材料，例如為氧化矽(silicon oxide)，第一介電層231可以被旋轉塗布(spin-coating)、層壓(laminating)或其他合適的沉積技術所製成，接著介電材料被圖形化並形成第一介電層231，且第一介電層 231具有多個開口(圖未示)。舉例而言，可以使用微影及蝕刻製程或其他適合的製程以圖形化第一介電層231。接著，在第一介電層231的多個開口中形成導電材料並形成第一導電特徵233，其中第一導電特徵233可以是經由電鍍、沉積製程、化學氣相沉積製程(chemical vapor deposition，CVD)、電漿加強型化學沉積製程(plasma-enhanced chemical vapor deposition，PECVD)、原子層沉積製程(atomic layer deposition，ALD)或其他合適的沉積製程，但本發明並不以此為限。
在本發明的一些實施方式中，形成蝕刻遮罩240包括：在第一接合層230上形成光阻層241；以及執行邊緣修整製程以移除光阻層241的邊緣部241a。具體而言，邊緣部241a包括邊緣珠(edge bead)，其中包括晶圓邊緣曝光製程(wafer edge exposure，WEE)或邊緣球狀物移除製程(edge bead removal，EBR)，例如為光學邊緣球狀物移除製程或化學邊緣球狀物移除製程，化學邊緣球狀物移除製程包括將丙二醇甲醚醋酸酯(propylene glycol methyl ether acetate，PGMEA)溶液或將乙二醇一甲基醚乙酸酯(ethyleneglycol monomethyl ether acetate，EGMEA)溶液施加於光阻層241。蝕刻遮罩240可以為未圖形化的光阻遮罩，但本發明並不以此為限。
在本發明的一些實施方式中，方法100更包括 步驟120，步驟120實施於步驟130之前，其中步驟120包括將積體電路結構220形成於第一晶圓210上，且積體電路結構220設置於第一晶圓210及第一接合層230之間。具體而言，積體電路結構220包括邏輯晶片，例如中央處理器、圖形化處理器或記憶體晶片(例如動態隨機存取記憶體晶片或靜態隨機存取記憶體晶片等)、電源管理晶片、射頻晶片、感測晶片、微機電系統晶片或其組合。在一些特定的實施方式中，記憶和/或電子控制功能可以整合在同一積體電路結構220。在一些實施方式中，積體電路結構220包括半導體基板221及多個穿透基材介層窗223(through semiconductor via，TSV)，介層窗223則延伸穿過半導體基板221，但本發明並不以此為限。
在本發明的一些實施方式中，互連結構(interconnection structure)形成在第一晶圓210及積體電路結構220之間。在第一晶圓210內的介層窗223可透過互連結構電性連接於積體電路結構220的介層窗223。
在本發明的一些實施方式中，多個介層窗223分別電性連接於第一接合層230的多個第一導電特徵233。舉例而言，多個介層窗223分別接觸第一接合層230的多個第一導電特徵233，但本發明並不以此為限。
在本發明的一些實施方式中，每一介層窗223 的寬度大於第一接合層230中每一第一導電特徵233的寬度。在一些可替換的實施方式中，每一介層窗223的寬度大於每一第一導電特徵233的寬度，但本發明並不以此為限。
請參考第4圖及第5圖。第4圖及第5圖可用於圖形化地代表第1圖中的步驟130，步驟130包括使用蝕刻遮罩240以蝕刻和移除積體電路結構220的邊緣部分225及第一接合層230的邊緣部分235，藉此暴露第一晶圓210的一部分。在本發明的一些實施方式中，邊緣部分225及邊緣部分235可以例如被乾蝕刻的非等向性蝕刻製程所移除。在一些實施方式中，乾蝕刻可以為反應離子蝕刻製程(reactive ion etch，RIE)、電漿蝕刻製程(plasma etch proces)或任何合適的蝕刻製程，本發明並不以此為限。在一些例子中，蝕刻遮罩240可以至少保護第一接合層230不受非等向性蝕刻製程所污染。因此，第一接合層230具有平滑表面，也就是說第一接合層230的表面上幾乎沒有缺陷。
請參考第5圖及第6圖，第5圖及第6圖可用於圖形化地表示第1圖中的步驟150，其中步驟150包括移除蝕刻遮罩240。具體而言，可搭配終點偵測實施平整化製程(planarization process)以移除蝕刻遮罩240，且平整化製程可包括機械研磨製程(mechanical grinding process)和/或化學機械研 磨製程(chemical mechanical polishing process，CMP)或其他合適的製程，但本發明並不以此為限。
請參考第6圖及第7圖。第6圖及第7圖可用於圖形化地表示第1圖中的步驟170，其中步驟170包括將第二晶圓310連接於第一接合層230，因此第一晶圓210及第二晶圓310相互連接並形成半導體裝置200。第二晶圓310可以為矽晶圓、半導體基板(例如是經參雜或未經參雜的塊狀半導體基板)或其他合適的基板(例如，多層基板或梯度基板等)。在本發明的一些實施方式中，步驟170更包括：將第一接合層230接觸第二晶圓310上的第二接合層330；以及將第一接合層230及第二接合層330相結合。第一接合層230及第二接合層330可以是使用混合鍵合製程(hybrid bonding process)、熔融接合製程(fusion bonding process)、直接接合製程(direct bonding process)、介電接合製程(dielectric bonding process)、金屬接合製程(metal bonding process)、焊接製程(solder joints process)或其他合適的製程相互結合。具體而言，可以將壓力施加於第一晶圓210及第二晶圓310以穩固地相互結合，因此第一接合層230的第一導電特徵233分別直接接觸第二接合層330的多個第二導電特徵333。舉例而言，在第一介電層231與第二接合層330的第二介電層331經由介電 接合(dielectric-to-dielectric bond)製程結合之後，多個第一導電特徵233與第二晶圓310的第二導電特徵333經由金屬接合(metal-to-metal)製程所結合。在本發明的一些實施方式中，每一第一導電特徵233的寬度對應於第二導電特徵333的寬度，但本發明並不以此為限。
綜上所述，蝕刻遮罩並不只用於部分蝕刻第一接合層及第一晶圓，更用於保護接合層，因此接合層的表面能維持平滑。因此，在晶圓接合製程中，第一晶圓及接合層能提供優異的接合效果。
本發明不同實施方式已描述如上，應可理解的是不同實施方式僅作為實例來呈現，而不作為限定。在不脫離本發明的精神和範圍下，可根據本文的揭露對本發明的實施方式做許多更動。因此，本發明的廣度和範圍不應受上述描述的實施例所限制。
100:方法
110，120，130，150，170:步驟
200:半導體裝置
210:第一晶圓
220:積體電路結構
221:基板
223:介層窗
225:邊緣部分
230:第一接合層
231:第一介電層
233:第一導電特徵
235:邊緣部分
240:蝕刻遮罩
241:光阻層
241a:邊緣部
310:第二晶圓
330:第二接合層
331:第二介電層
333:第二導電特徵
為達成上述的優點和特徵，將參考實施方式對上述簡要描述的原理進行更具體的闡釋，而具體實施方式被展現在附圖中。這些附圖僅例示性地描述本發明，因此不限制發明的範圍。通過附圖，將清楚解釋本發明的原理，且附加的特徵和細節將被完整描述，其中： 第1圖繪示為本發明一些實施方式中半導體裝置的製造方法的流程圖；以及 第2圖至第7圖繪示半導體裝置的製造方法的各個步驟。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
100:方法
110，120，130，150，170:步驟

Claims (10)

  1. 一種製造半導體裝置的方法，包括：在第一晶圓上形成包含第一導電特徵的第一接合層；在包含第一導電特徵的第一接合層上形成蝕刻遮罩；使用該蝕刻遮罩蝕刻該第一接合層的邊緣部，並暴露出該第一晶圓的一部分；移除該蝕刻遮罩；以及將第二晶圓固定於該第一接合層。
  2. 如請求項1所述之方法，進一步包括：在該第一晶圓上形成積體電路結構，其中該積體電路結構位於該第一晶圓及該第一接合層之間。
  3. 如請求項2所述之方法，其中該積體電路結構包括基板及穿過該基板的介層窗。
  4. 如請求項3所述之方法，其中該介層窗接觸該第一接合層的該第一導電特徵。
  5. 如請求項4所述之方法，其中該介層窗的寬度小於該第一導電特徵的寬度。
  6. 如請求項1所述之方法，其中該第一接合層包括介電層及穿過該介電層的第一導電特徵。
  7. 如請求項1所述之方法，其中形成該蝕刻遮罩包括：在該第一接合層上形成光阻層；以及執行邊緣修整製程，以移除該光阻層的邊緣部。
  8. 如請求項1所述之方法，其中將該第二晶圓固定於該第一接合層包括：使該第二晶圓上的第二接合層接觸該第一接合層；以及結合該第一接合層及該第二接合層。
  9. 如請求項8所述之方法，其中該第一接合層內的第一導電特徵接觸該第二接合層內的第二導電特徵。
  10. 如請求項9所述之方法，其中該第一導電特徵的寬度等於該第二導電特徵的寬度。
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