CN114342057A - 遮盘 - Google Patents

遮盘 Download PDF

Info

Publication number
CN114342057A
CN114342057A CN202080062271.3A CN202080062271A CN114342057A CN 114342057 A CN114342057 A CN 114342057A CN 202080062271 A CN202080062271 A CN 202080062271A CN 114342057 A CN114342057 A CN 114342057A
Authority
CN
China
Prior art keywords
substrate
chamber
processing
plasma
getter material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202080062271.3A
Other languages
English (en)
Inventor
张康
魏俊琪
欧岳生
K·波
和田优一
A·朱普迪
S·巴布
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of CN114342057A publication Critical patent/CN114342057A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/56—Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
    • C23C14/564—Means for minimising impurities in the coating chamber such as dust, moisture, residual gases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H01L2021/60045—Pre-treatment step of the bump connectors prior to bonding
    • H01L2021/60052—Oxide removing step, e.g. flux, rosin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0381—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Mechanical Engineering (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Physical Vapour Deposition (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

描述用于物理气相沉积(PVD)的包括钛(Ti)、钡(Ba)、或铈(Ce)中的一者或多者的遮盘，所述遮盘允许粘贴以在基板的蚀刻期间最小化释气和控制缺陷。所述遮盘合并集气剂材料，所述集气剂材料对于包括O2、CO、CO2、和水的反应气体分子具有高度选择性。

Description

遮盘
技术领域
本公开内容的实施例总体上涉及电子装置。更具体地，本公开内容的实施例涉及晶片级封装或芯片倒装封装中的凸点下金属化(under bump metallization)。
先前技术
在半导体制造演化的过程中，已经利用不同的封装技术。用于电子装置的晶片级制造和芯片倒装封装技术在小型化方案的最前线。
半导体封装的目标为达到增加速度、降低功率、较佳装置功能性、和降低花费的更短的电子路径。需要凸点下金属化(UBM)以使用焊料凸起将晶片连接至基板以用于芯片倒装封装。集成电路(IC)的UBM接合通常为铝或铜的垫。这是对于电子封装的可靠性的必要工艺步骤。
数种选择能够达成凸点下金属化(UBM)。与电镀相结合的干式真空溅射方法是最普遍使用的方法且涉及在高温蒸镀系统中被溅射的多个金属层。许多IC接合垫的最终层通常包括铝、铝/硅、铝/硅/铜、或铜。由于引线接合技术形成穿过通常存在的氧化物层的可接受的连接，所以铝适用于常规引线接合互连。然而，铝不是可焊接的、可润湿的、或可接合至使用在再流中的凸起和焊接材料。UBM层产生良好接合至铝垫、气密地密封铝、以及防止潜在的金属扩散进入IC封装中。
当铝暴露于环境时，铝几乎立即氧化，所以UBM工艺中的第一个挑战是从铝IC垫移除原生的氧化物层。因此，在UBM工艺中，预清洁步骤是必要的，以在阻挡层的沉积之前移除金属接触垫的原生氧化物。然而，在预清洁工艺期间，释气分子和物种将会产生，且因此再污染干净的金属表面并且造成将会影响集成电路性能的高的接触电阻。
因此，有着对于改进的用于芯片倒装封装和晶片级封装的凸点下金属化方法的需求。
发明内容
本公开内容的一个或多个实施例涉及处理方法。所述方法包括在处理腔室的壁上沉积一厚度的集气剂(getter)材料；以及在处理腔室中使用等离子体蚀刻基板以移除原生氧化物并形成经清洁的基板，其中蚀刻基板释放化学地结合至集气剂材料的释气分子。
本公开内容的额外实施例涉及处理工具。处理工具包括：在其中具有基板支撑件的预清洁腔室；缓冲站；配置以进出预清洁腔室和缓冲站的机器人；以及连接至预清洁腔室、缓冲站、和机器人的控制器，控制器具有选自以下项的一个或多个配置：沉积集气剂材料、蚀刻基板、或沉积阻挡层。
本公开内容的进一步实施例涉及包括指令的非暂态计算机可读介质，当由处理腔室的控制器执行指令时，非暂态计算机可读介质致使处理腔室执行以下操作：在处理腔室的壁上沉积集气剂材料；以及在处理腔室中使用等离子体蚀刻基板。
附图说明
通过参照实施例，某些实施例示于附图中，可获得简短总结于上的本公开内容的更具体的说明，以使得本公开内容的上述特征可被详细理解。然而，将注意到附图仅示出了本公开内容的典型实施例，且因此不被视为限制本公开内容的范围，这是因为本公开内容可容许其他等效的实施例。
图1描绘根据一个或多个实施例的处理方法的流程图；
图2描绘根据一个或多个实施例的处理腔室；
图3描绘根据一个或多个实施例的处理腔室；
图4描绘根据一个或多个实施例的处理腔室；且
图5描绘根据一个或多个实施例的处理工具。
具体实施方式
在描述本公开内容的若干示例性实施例之前，将理解，本公开内容并不局限于在之后的说明书中所述的架构或工艺步骤的细节。本公开内容能够为其他实施例且以各种方式实践或执行。
示出于附图中的许多细节、尺度、角度以及其他特征仅示出特定的实施例。因此，在不背离本公开内容的精神和范围的情况下，其他实施例可以具有其他细节、部件、尺度、角度和特征。另外，本公开内容的进一步实施例可在没有之后所述的若干细节的情况下实践。
当在本说明书及所附的权利要求中使用时，用语“基板”指称在其上进行工艺的表面或表面的一部分。除非在上下文中另外清楚地指明，本领域技术人员将理解到，基板也可仅指称所述基板的一部分。此外，对于在基板上的沉积的引用可以意指裸基板和具有沉积或形成在其上的一个或多个膜或特征的基板两者。
本文所使用的“基板”指称膜处理在制造工艺期间在其上被执行的任何基板或形成在基板上的材料表面。例如，在其上可执行处理的基板表面包括材料，诸如硅、氧化硅、应变硅、绝缘体上硅(SOI)、碳掺杂氧化硅、非晶硅、掺杂硅、锗、砷化镓、玻璃、蓝宝石、以及任何其他材料，诸如金属、金属氮化物、金属合金、以及其他导电材料，这取决于应用。在不受限制的情况下，基板包括半导体晶片。基板可暴露于预处理工艺以抛光、蚀刻、还原、氧化、羟基化、退火、UV固化、电子束固化和/或烘烤基板表面。除了直接在基板本身的表面上的膜处理之外，在本公开内容中，公开的任何膜处理步骤也可对形成于基板上的下方层执行，如之后更详细说明的，而用语“基板表面”意欲包括如上下文所指示的此下方层。因此，例如，在膜/层或部分的膜/层已经沉积在基板表面上的情况下，新沉积的膜/层的暴露的表面成为基板表面。
在本说明书及所附的权利要求中使用时，用语“反应化合物”、“反应气体”、“反应物种”、“前驱物”、“工艺气体”等可互换地使用以意指具有能在表面反应(例如，化学吸附、氧化、还原)中与基板表面或者基板表面上的材料进行反应的物种的物质。例如，第一“反应气体”可简单地吸附于基板的表面上并且能够用于与第二反应气体的进一步的化学反应。
已经投入极大的努力以降低在凸点下金属化(UBM)期间的聚合物的释气，诸如温度控制和RF功率调整，等等。在一个或多个实施例中，通过粘贴方法将钛(Ti)、钡(Ba)、或铈(Ce)中的一者或多者覆盖处理腔室的内屏蔽件或壁有助于吸收释气分子。在此使用时，用语“粘粘”指称集气剂材料的溅射，使得材料粘附于处理腔室的壁，从而在壁上形成集气剂材料的层。
在一个或多个实施例中，处理腔室中的释气分子的浓度可有利地被显著地降低。因此，在一个或多个实施例中，金属接触表面的再污染被最小化，从而有助于保持低接触电阻以为了更佳的电子装置性能。
本公开内容的实施例提供用于物理气相沉积(PVD)的包括钛(Ti)、钡(Ba)、或铈(Ce)中的一者或多者的遮盘，所述遮盘允许粘贴以在基板的蚀刻期间最小化释气和控制缺陷。一个或多个实施例提供改进的和/或增加的工艺套件的使用寿命。
在一个或多个实施例中，已经观察到将集气剂材料粘粘于例如预清洁腔室的处理腔室上/处理腔室中，使释气分子浓度减少达至少两个数量级。此观察到的结果优于其他方法，诸如增加泵送速度和改进气体传导性。
本公开内容的实施例并入集气剂材料，此集气剂材料对于诸如氧(O2)、一氧化碳(CO)、二氧化碳(CO2)和水(H2O)之类的反应气体分子具有高度选择性。这些反应气体分子对于PVD沉积装置中的金属接触电阻来说是有害的。某些实施例有利地提供钛(Ti)、钡(Ba)、或铈(Ce)遮盘，钛(Ti)、钡(Ba)、或铈(Ce)遮盘最小化屏蔽释气，延长屏蔽套件寿命，防止再污染金属表面，作为集气剂材料，在处理期间吸收包括氧(O2)、一氧化碳(CO)、二氧化碳(CO2)和水(H2O)的释气分子，能够承受高温，和/或在处理期间具有最小的翘曲。
本公开内容的实施例不需要腔室硬件修改，而是利用包含或包括集气剂材料的遮盘。在一个或多个实施例中，遮盘移送至处理腔室，且RF功率用于执行溅射工艺，从而将集气剂材料溅射在处理腔室的侧部上。在一个或多个实施例中，遮盘对于诸如氩(Ar)和氦(He)之类的惰性气体是不敏感的，并且因此惰性气体分子对预清洁工艺中的物理等离子体溅射效应具有有限的影响。
参照图1至图4，一个或多个实施例涉及处理基板的方法100。示出在图1中的方法是物理气相沉积(PVD)工艺的代表图。在这里使用时，用语“物理气相沉积”或替换地“溅射”指称在半导体集成电路的制造中的金属和相关材料的沉积工艺。溅射的使用已延伸至在诸如通孔或其他的垂直互连结构之类的高深宽比孔洞的侧壁上沉积金属层。可使用DC溅射或RF溅射中的任一者完成等离子体溅射。等离子体溅射通常包括定位在溅射靶材的背部处的磁控管，此磁控管包括两个磁体，所述两个磁体的相反极通过磁轭在其背部磁性地耦接，以投射磁场进入处理空间以增加等离子体的密度且增强来自靶材前面的溅射速率。使用在磁控管中的磁体通常对于DC溅射为封闭回路而对于RF溅射为开放回路。
在等离子体增强基板处理系统(诸如物理气相沉积(PVD)腔室)中，带有高磁场和高DC功率的高功率密度PVD溅射可产生高能量于溅射靶材处，且导致溅射靶材的表面温度大幅提升。通过使靶材背板接触冷却流体以冷却溅射靶材。在如商业上通常实施的等离子体溅射中，将被溅射沉积的材料的靶材被密封至包含将被涂布的晶片的真空腔室。惰性气体(例如氩(Ar))被允许进到此腔室。当数百伏特的负DC偏压施加于靶材，同时腔室壁或屏蔽件保持接地时，惰性气体被激发成等离子体。带正电荷的惰性气体离子被吸引至高能量的负偏压靶材且从靶材溅射靶材原子。
在一个或多个实施例中，在操作10处，集气剂材料204沉积在处理腔室200的至少一个壁上。在一个或多个实施例中，集气剂材料204在处理腔室200的至少一个壁上沉积到厚度202。在一个或多个实施例中，厚度202大于或等于10nm，包括约10nm至约100μM的范围。在一个或多个实施例中，集气剂材料206包括钛(Ti)、钡(Ba)、或铈(Ce)中的一者或多者。在一个或多个实施例中，通过溅射遮盘206来获得集气剂材料204。在一个或多个实施例中，溅射工艺包括将遮盘206暴露于等离子体208。在一个或多个实施例中，等离子体208包括惰性等离子体。在某些实施例中，等离子体208包括氩(Ar)或氦(He)中的一者或多者。
在一个或多个实施例中，等离子体208可远程地产生或在处理腔室200内产生。在一个或多个实施例中，等离子体208是感应耦合等离子体(ICP)或电容耦合等离子体(CCP)。可使用任何合适功率并取决于例如反应物或其他工艺条件。在某些实施例中，等离子体208以范围为约10W至约3000W的等离子体功率来产生。在某些实施例中，等离子体208以小于或等于约3000W、小于或等于约2000W、小于或等于约1000W、小于或等于约500W、或小于或等于约250W的等离子体功率来产生。
在一个或多个实施例中，遮盘206包括钛(Ti)、钡(Ba)、或铈(Ce)中的一者或多者。在特定实施例中，遮盘206包括钛(Ti)，且当溅射时，释放包括钛(Ti)的集气剂材料204，使得钛沉积在处理腔室200的至少一个壁上。
在一个或多个实施例中，在操作20处，遮盘206接着被移动或移送至缓冲站。在某些实施例中，缓冲站位于处理腔室200内。在其他实施例中，缓冲站位于邻近腔室中。在一个或多个实施例中，遮盘206通过机器人来移送。在一个或多个实施例中，在操作30处，基板209接着定位在处理腔室200内。
在一个或多个实施例中，基板209包括硅层210、氧化物层212、金属层214、聚合物层216、或原生氧化物层218中的一者或多者。在一个或多个实施例中，氧化物层212包括氧化铝层。在一个或多个实施例中，金属层214包括铝(Al)或铜(Cu)中的一者或多者。在一个或多个实施例中，聚合物层216包括聚酰亚胺或者聚苯并恶唑中的一者或多者。
在一个或多个实施例中，在操作40处，基板209在处理腔室200中被蚀刻。在一个或多个实施例中，通过等离子体208蚀刻基板209。在一个或多个实施例中，等离子体208包括惰性等离子体。在某些实施例中，等离子体208包括氩(Ar)或氦(He)中的一者或多者。在某些实施例中，等离子体208与用以在处理腔室的至少一个侧壁上溅射集气剂材料204的等离子体相同。在其他实施例中，等离子体208不同于用以溅射集气剂材料204的等离子体。
不欲被理论所局限，在基板209的聚合物层216的蚀刻时，基板209释放释气分子，例如220、222、224、226。在一个或多个实施例中，释气分子被沉积在处理腔室200的侧部上的集气剂材料204所吸收。在一个或多个实施例中，释气分子包括氧(O2)、一氧化碳(CO)、二氧化碳(CO2)或水(H2O)中的一者或多者。如图4所示，因为集气剂材料能够吸收释气分子，处理腔室中的释气分子的浓度被显著地降低，并且因此基板206的金属接触表面214的再污染被最小化，以便保持低接触电阻以为了更佳的电子装置性能。
在一个或多个实施例中，来自基板209的释气分子的数量被降低至小于或等于来自不包含集气剂材料的处理腔室中的基板的释气分子的约10％。在一个或多个特定的实施例中，来自基板209的释气一氧化碳(CO)的量被降低至小于或等于来自不包含集气剂材料的处理腔室中的基板的释气一氧化碳(CO)的约10％。
图5示出根据本公开内容的一个或多个实施例的处理工具300。图5所示的实施例仅为一种可能配置的代表图且不应视作限制本公开内容的范围。例如，在某些实施例中，处理工具300拥有与所示实施例不同数量的处理腔室302、缓冲站310和/或机器人308配置中的一者或多者。
示例性处理工具300包括例如预清洁腔室之类的处理腔室302，所述处理腔室302具有多个侧部。所示出的处理腔室302具有第一侧部303a、第二侧部303b、第三侧部303c以及第四侧部303d。虽然示出了四个侧部，但本领域技术人员将理解，对于处理腔室302，可存在任何合适数量的侧部，这取决于例如处理工具300的整体的配置。在某些实施例中，处理腔室302具有三个侧部、四个侧部、五个侧部、六个侧部、七个侧部或八个侧部。
处理腔室302具有定位在处理腔室302中的机器人308。机器人308可为能够在处理期间移动晶片的任何合适机器人。在某些实施例中，机器人308具有第一臂309a和第二臂309b。第一臂309a和第二臂309b可相对于其他臂独立地移动。第一臂309a和第二臂309b可在x-y平面中和/或沿z轴移动。在某些实施例中，机器人308包括第三臂(未示出)或第四臂(未示出)。每个臂可相对于其他臂独立地移动。
处理工具300也可包括连接至处理腔室302的第一侧部303a的一个或多个缓冲站310。缓冲站310可执行相同或不同的功能。例如，缓冲站可固持经处理并返回起始盒的一盒晶片，或缓冲站中的一者可固持在处理之后被移动至其他缓冲站的未处理的晶片。在某些实施例中，缓冲站中的一者或多者经配置以在处理之前和/或处理之后预处理、预加热或清洁晶片。
处理工具300也可包括在处理腔室302和缓冲站310之间的一个或多个狭缝阀312。狭缝阀312可开启与关闭以隔离处理腔室302内的内部容积。例如，若处理腔室302在处理期间将产生等离子体，则将狭缝阀关闭对于处理腔室来说是有益的，以防止散逸等离子体损害移送站中的机器人。
机器人308可用于使晶片或盒移动进出缓冲站310。晶片或盒可通过机器人308而在处理工具300内移动。在一个或多个实施例中，机器人308将遮盘移动进出处理腔室302至缓冲站310。
可以提供控制器314并耦接至处理工具300的各种部件以控制这些部件的操作。控制器314可为控制整个处理工具300的单个控制器，或控制处理工具300的个别部分的多个控制器。例如，处理工具300可包括用于处理腔室302、缓冲站310、以及机器人308中的各者的分开的控制器。
在某些实施例中，处理腔室302进一步包括连接至多个实质上共平面的支撑表面304的控制器314。在一个或多个实施例中，控制器314控制基板支撑组件304的移动速度。
在某些实施例中，控制器314包括中央处理单元(CPU)316、存储器318、输入/输出(I/O)320、以及支持电路322。控制器314可直接地控制处理工具300，或经由与特定处理腔室和/或支撑系统部件相关联的计算机(或控制器)控制处理工具300。
控制器314可为任何形式的通用计算机处理器中的任一者，其可被使用在用于控制各种腔室与子处理器的工业环境中。存储器318或控制器314的计算机可读介质可为容易可用的存储器中的一者或多者，诸如本地或远程的随机存取存储器(RAM)、只读存储器(ROM)、软盘、硬盘、光学存储介质(例如，光盘或数字视频盘)、随身盘、或任何其他形式的数字存储。存储器318可保持可由处理器(CPU 316)操作的指令集以控制处理工具300的参数和部件。
支持电路322耦接至CPU 316，用于以常规方式支持处理器。这些电路包括高速缓存、电源、时钟电路、输入/输出电路系统和子系统等等。一个或多个工艺可存储于存储器318中作为软件例程，当通过处理器执行或实行软件例程时，使处理器以本文所述的方式控制处理工具300或个别处理腔室的操作。此软件例程也可由第二CPU(未示出)存储和/或执行，所述第二CPU位于由CPU 316所控制的硬件的远端。
本公开内容的某些或所有的工艺和方法也可被执行在硬件中。因此，工艺可被实施在软件中并使用计算机系统执行在硬件中，如例如专用集成电路或其他类型的硬件实现，或如软件和硬件的组合。当由处理器执行时，软件例程将通用计算机转变为控制腔室操作以使得执行工艺的特定目的计算机(控制器)。
在某些实施例中，控制器314具有一个或多个配置以执行个别工艺或子工艺以执行所述方法。控制器314可连接至中间部件并且经配置以操作中间部件，以执行所述方法的功能。例如，控制器314可连接至并且经配置以控制气体阀、致动器、电机、狭缝阀、真空控制或其他部件中的一者或多者。
贯穿本说明书中的对“一个实施例(one embodiment)”、“某些实施例”、“一个或多个实施例”、或“一实施例(an embodiment)”的引用意指结合所述实施例描述的特定特征、结构、材料或特性被包括在本公开内容的至少一个实施例中。因此，在贯穿本说明书中的各种地方出现的诸如“在一个或多个实施例中”、“在某些实施例中”、“在一个实施例中(inoneembodiment)”、或“在一实施例中(in an embodiment)”的短语不一定指称本公开内容的相同的实施例。此外，在一个或多个实施例中，特定特征、结构、材料、或特性以任何合适的方式组合。
虽然本公开内容在此已参照特定实施例而说明，但是本领域技术人员将理解，所述实施例仅为本公开内容的原理与应用的示例。在不背离本公开内容的精神和范围的情况下，对于本领域技术人员来说，可对本公开内容的方法及设备进行各种修改及变化将是明显的。因此，本公开内容可包括在所附的权利要求和其等效方案的范围内的修改和变化。
权利要求书(按照条约第19条的修改)
1.一种处理方法，所述方法包括：
在处理腔室的壁上沉积一厚度的集气剂材料，所述集气剂材料包括中的一者或多者；以及
在所述处理腔室中使用等离子体蚀刻基板，以移除原生氧化物并且形成经清洁的基板，
其中蚀刻所述基板释放释气分子，所述释气分子化学地结合至所述集气剂材料。
2.如权利要求1所述的方法，进一步包括在所述经清洁的基板上沉积阻挡层。
3.如权利要求2所述的方法，其中所述阻挡层包括钛(Ti)或铜(Cu)中的一者或多者。
4.如权利要求1所述的方法，其中所述集气剂材料包括钛、钡或铈中的一者或多者。
5.如权利要求1所述的方法，其中沉积所述集气剂材料包括溅射工艺。
6.如权利要求5所述的方法，其中所述溅射工艺包括将遮盘暴露于等离子体。
7.如权利要求6所述的方法，其中所述遮盘包括钛、钡或铈中的一者或多者。
8.如权利要求6所述的方法，进一步包括将所述遮盘移动至缓冲站和将所述基板定位在所述处理腔室中。
9.如权利要求1所述的方法，其中所述释气分子包括氧(O2)、一氧化碳(CO)、二氧化碳(CO2)或水(H2O)中的一者或多者。
10.如权利要求1所述的方法，其中所述集气剂材料的所述厚度大于或等于约10nm。
11.如权利要求1所述的方法，其中所述等离子体包括氩(Ar)或氦(He)中的一者或多者。
12.如权利要求1所述的方法，其中所述基板包括铝(Al)、铜(Cu)、氧化物层或聚合物层中的一者或多者。
13.如权利要求1所述的方法，其中来自所述基板的CO释气的量减少至小于或等于来自无所述集气剂材料的处理腔室中的基板的CO释气的约10％。
14.一种处理工具，包括：
预清洁腔室，所述预清洁腔室具有在所述预清洁腔室中的基板支撑件；
缓冲站；
机器人，所述机器人经配置以进出所述预清洁腔室和所述缓冲站；以及
控制器，所述控制器连接至所述预清洁腔室、所述缓冲站和所述机器人，所述控制器具有选自以下项的一个或多个配置：沉积集气剂材料、蚀刻基板、或者沉积阻挡层。
15.如权利要求14所述的处理工具，其中所述缓冲站在所述预清洁腔室内。
16.如权利要求14所述的处理工具，其中所述缓冲站在相邻于所述预清洁腔室的腔室中。
17.如权利要求14所述的处理工具，进一步包括至少一个狭缝阀，用于进出所述预清洁腔室和所述缓冲站。
18.如权利要求14所述的处理工具，其中所述控制器包括中央处理单元(CPU)、存储器、输入/输出(I/O)、或支持电路中的一者或多者。
19.一种非暂态计算机可读介质，所述非暂态计算机可读介质包括多个指令，所述多个指令在由处理腔室的控制器执行时使所述处理腔室执行以下操作：
在所述处理腔室的壁上沉积集气剂材料，所述集气剂材料包括中的一者或多者；以及
在所述处理腔室中使用等离子体蚀刻基板。
20.如权利要求19所述的非暂态计算机可读介质，其中沉积集气剂材料包括将包括所述集气剂材料的遮盘暴露于等离子体和溅射所述集气剂材料。

Claims (20)

1.一种处理方法，所述方法包括：
在处理腔室的壁上沉积一厚度的集气剂材料；以及
在所述处理腔室中使用等离子体蚀刻基板，以移除原生氧化物并且形成经清洁的基板，
其中蚀刻所述基板释放释气分子，所述释气分子化学地结合至所述集气剂材料。
2.如权利要求1所述的方法，进一步包括在所述经清洁的基板上沉积阻挡层。
3.如权利要求2所述的方法，其中所述阻挡层包括钛(Ti)或铜(Cu)中的一者或多者。
4.如权利要求1所述的方法，其中所述集气剂材料包括钛、钡或铈中的一者或多者。
5.如权利要求1所述的方法，其中沉积所述集气剂材料包括溅射工艺。
6.如权利要求5所述的方法，其中所述溅射工艺包括将遮盘暴露于等离子体。
7.如权利要求6所述的方法，其中所述遮盘包括钛、钡或铈中的一者或多者。
8.如权利要求6所述的方法，进一步包括将所述遮盘移动至缓冲站和将所述基板定位在所述处理腔室中。
9.如权利要求1所述的方法，其中所述释气分子包括氧(O2)、一氧化碳(CO)、二氧化碳(CO2)或水(H2O)中的一者或多者。
10.如权利要求1所述的方法，其中所述集气剂材料的所述厚度大于或等于约10nm。
11.如权利要求1所述的方法，其中所述等离子体包括氩(Ar)或氦(He)中的一者或多者。
12.如权利要求1所述的方法，其中所述基板包括铝(Al)、铜(Cu)、氧化物层或聚合物层中的一者或多者。
13.如权利要求1所述的方法，其中来自所述基板的CO释气的量减少至小于或等于来自无所述集气剂材料的处理腔室中的基板的CO释气的约10％。
14.一种处理工具，包括：
预清洁腔室，所述预清洁腔室具有在所述预清洁腔室中的基板支撑件；
缓冲站；
机器人，所述机器人经配置以进出所述预清洁腔室和所述缓冲站；以及
控制器，所述控制器连接至所述预清洁腔室、所述缓冲站和所述机器人，所述控制器具有选自以下项的一个或多个配置：沉积集气剂材料、蚀刻基板、或者沉积阻挡层。
15.如权利要求14所述的处理工具，其中所述缓冲站在所述预清洁腔室内。
16.如权利要求14所述的处理工具，其中所述缓冲站在相邻于所述预清洁腔室的腔室中。
17.如权利要求14所述的处理工具，进一步包括至少一个狭缝阀，用于进出所述预清洁腔室和所述缓冲站。
18.如权利要求14所述的处理工具，其中所述控制器包括中央处理单元(CPU)、存储器、输入/输出(I/O)、或支持电路中的一者或多者。
19.一种非暂态计算机可读介质，所述非暂态计算机可读介质包括多个指令，所述多个指令在由处理腔室的控制器执行时使所述处理腔室执行以下操作：
在所述处理腔室的壁上沉积集气剂材料；以及
在所述处理腔室中使用等离子体蚀刻基板。
20.如权利要求19所述的非暂态计算机可读介质，其中沉积集气剂材料包括将包括所述集气剂材料的遮盘暴露于等离子体和溅射所述集气剂材料。
CN202080062271.3A 2019-09-06 2020-09-03 遮盘 Pending CN114342057A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201962896819P 2019-09-06 2019-09-06
US62/896,819 2019-09-06
PCT/US2020/049184 WO2021046208A1 (en) 2019-09-06 2020-09-03 Shutter disk

Publications (1)

Publication Number Publication Date
CN114342057A true CN114342057A (zh) 2022-04-12

Family

ID=74850186

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202080062271.3A Pending CN114342057A (zh) 2019-09-06 2020-09-03 遮盘

Country Status (6)

Country Link
US (3) US11171017B2 (zh)
JP (1) JP2023523663A (zh)
KR (1) KR20220054437A (zh)
CN (1) CN114342057A (zh)
TW (1) TW202117044A (zh)
WO (1) WO2021046208A1 (zh)

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4022939A (en) * 1975-12-18 1977-05-10 Western Electric Company, Inc. Synchronous shielding in vacuum deposition system
DE69632969T2 (de) 1995-03-20 2005-07-28 Unitive International Ltd. Verfahren zum Bilden von Loterhebungen und Loterhebungsstruktur
US5961791A (en) 1997-02-26 1999-10-05 Motorola, Inc. Process for fabricating a semiconductor device
US20040040855A1 (en) 2002-08-28 2004-03-04 Victor Batinovich Method for low-cost redistribution and under-bump metallization for flip-chip and wafer-level BGA silicon device packages
JP2004273961A (ja) 2003-03-12 2004-09-30 Ebara Corp 金属配線形成基板の洗浄処理装置
ITMI20041443A1 (it) 2004-07-19 2004-10-19 Getters Spa Processo per la produzione di schermi al plasma con materiale getter distribuito e schermi cosi'ottenuti
US20120132522A1 (en) * 2007-07-19 2012-05-31 Innovative Micro Technology Deposition/bonding chamber for encapsulated microdevices and method of use
US8008166B2 (en) * 2007-07-26 2011-08-30 Applied Materials, Inc. Method and apparatus for cleaning a substrate surface
JP5331610B2 (ja) * 2008-12-03 2013-10-30 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US8786081B2 (en) 2011-07-27 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device for circuit routing by way of under-bump metallization
US9252002B2 (en) * 2012-07-17 2016-02-02 Applied Materials, Inc. Two piece shutter disk assembly for a substrate process chamber
US9147558B2 (en) * 2013-01-16 2015-09-29 Applied Materials, Inc. Finned shutter disk for a substrate process chamber
US9673071B2 (en) * 2014-10-23 2017-06-06 Lam Research Corporation Buffer station for thermal control of semiconductor substrates transferred therethrough and method of transferring semiconductor substrates
GB201420935D0 (en) * 2014-11-25 2015-01-07 Spts Technologies Ltd Plasma etching apparatus
US10510545B2 (en) * 2016-06-20 2019-12-17 Applied Materials, Inc. Hydrogenation and nitridization processes for modifying effective oxide thickness of a film
TW201819665A (zh) * 2016-09-10 2018-06-01 美商應用材料股份有限公司 用於選擇性沉積之選擇性改良的原位預清潔

Also Published As

Publication number Publication date
US11171017B2 (en) 2021-11-09
US20220028702A1 (en) 2022-01-27
JP2023523663A (ja) 2023-06-07
US11862480B2 (en) 2024-01-02
US20240087913A1 (en) 2024-03-14
TW202117044A (zh) 2021-05-01
WO2021046208A1 (en) 2021-03-11
US20210074552A1 (en) 2021-03-11
KR20220054437A (ko) 2022-05-02

Similar Documents

Publication Publication Date Title
JP2024016261A (ja) 半導体装置
JP5522979B2 (ja) 成膜方法及び処理システム
JP2009102740A (ja) 金属膜堆積方法および超臨界乾燥／クリーニングモジュールを含む金属堆積クラスタツール
KR20120101653A (ko) 기판을 프로세싱하기 위한 방법 및 장치
JP2008218659A (ja) 半導体装置の製造方法、半導体製造装置及びプログラム
US20120111925A1 (en) Reducing Formation Of Oxide On Solder
US20140251945A1 (en) Method of etching metal layer
US9269562B2 (en) In situ chamber clean with inert hydrogen helium mixture during wafer process
JP3996804B2 (ja) 半導体素子の銅薄膜堆積装置
US6908865B2 (en) Method and apparatus for cleaning substrates
US10141195B2 (en) Substrate processing method
KR20170026165A (ko) 반도체 장치의 제조 방법 및 기억 매체
US11862480B2 (en) Shutter disk
US20230197550A1 (en) Passivation layer for a semiconductor device and method for manufacturing the same
JP7465287B2 (ja) 自己形成バリア層を備えた低誘電率誘電体
TW201347089A (zh) 半導體裝置之製造方法、記憶媒體及半導體裝置
US10643889B2 (en) Pre-treatment method to improve selectivity in a selective deposition process
TWI840569B (zh) 低k介電質之自形成阻障層
KR20210007030A (ko) 아연 도핑에 의한 금속 라이너 패시베이션 및 접착 향상
US20230062974A1 (en) Cleaning chamber for metal oxide removal
US20200312683A1 (en) Substrate support pedestal
TWI821805B (zh) 反向選擇性蝕刻終止層
US20210043432A1 (en) Substrate support system
TW202338909A (zh) 損傷之氮化矽的選擇性鈍化
CN114709167A (zh) 半导体器件及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination