CN114334958A - 半导体结构与其形成方法 - Google Patents
半导体结构与其形成方法 Download PDFInfo
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- CN114334958A CN114334958A CN202110843753.9A CN202110843753A CN114334958A CN 114334958 A CN114334958 A CN 114334958A CN 202110843753 A CN202110843753 A CN 202110843753A CN 114334958 A CN114334958 A CN 114334958A
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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Abstract
此处提供半导体结构与其形成方法。在一实施例中,半导体结构包括多个第一通道组件,位于背侧介电层上;多个第二通道组件,位于背侧介电层上;硅化物结构,位于背侧介电层上;以及源极/漏极结构,位于硅化物结构上并延伸于第一通道组件与第二通道组件之间。硅化物结构延伸穿过背侧介电层的所有深度。
Description
技术领域
本发明实施例一般关于具有背侧源极/漏极接点的半导体装置的形成方法,更特别关于硅化物所组成的背侧源极/漏极接点的形成方法。
背景技术
半导体集成电路产业已经历指数成长。集成电路材料与设计的技术进展,使每一代的集成电路比前一代具有更小且更复杂的电路。在集成电路演进中,功能密度(比如单位芯片面积的内连线装置数目)通常随着几何尺寸(比如采用的制作制程所能产生的最小构件或线路)缩小而增加。尺寸缩小的制程通常有利于增加产能与降低相关成本。尺寸缩小亦会增加处理与制造集成电路的复杂度。
举例来说,随着集成电路技术制程朝着较小的技术节点进展,已导入多栅极装置以增加栅极-通道耦合、减少关闭状态电流、并减少短通道效应而改善栅极控制。多栅极装置通常可视作具有栅极结构或其部分位于通道区的多侧上的装置。鳍状场效晶体管与多桥通道晶体管为多栅极装置的例子,其为高效能与低漏电流应用的泛用及有力候选。鳍状场效晶体管具有隆起的通道,且栅极包覆通道的多侧(比如栅极包覆自基板延伸的半导体材料的鳍状物的顶部与侧壁)。多桥通道晶体管的栅极结构可部分或完全延伸于通道区周围,以接触通道区的两侧或更多侧。由于栅极结构围绕通道区,多桥通道晶体管亦可视作围绕栅极晶体管或全绕式栅极晶体管。多桥通道晶体管的通道区可由纳米线、纳米片、其他纳米结构、及/或其他合适结构所形成。多桥通道晶体管因通道区的形状而可改称作纳米片晶体管或纳米线晶体管。
随着多栅极装置的尺寸缩小,封装所有接点结构至基板的一侧上的作法的挑战性越来越高。为了增加封装密度,可刻意移动一些线路结构如电源线(亦可视作电源轨)至基板背侧。形成背侧源极/漏极接点的一些制程可能损伤源极/漏极结构。因此虽然现存的背侧电源轨的行程制程通常适用于其发展目的,但不能符合所有方面的需求。
发明内容
本发明一例示性的实施例关于半导体结构。半导体结构包括多个第一通道组件,位于背侧介电层上;多个第二通道组件,位于背侧介电层上;硅化物结构,位于背侧介电层上;以及源极/漏极结构,位于硅化物结构上并延伸于第一通道组件与第二通道组件之间。硅化物结构延伸穿过背侧介电层的所有深度。
本发明另一例示性的实施例关于半导体结构。半导体结构包括背侧金属线路;硅化物结构,位于背侧金属线路上并接触背侧金属线路;源极/漏极结构,位于硅化物结构上;接点蚀刻停止层,位于源极/漏极结构上;以及介电层,位于接点蚀刻停止层上。
本发明又一例示性的实施例关于半导体结构的形成方法。方法包括:接收工件,其包括:鳍状结构位于基板上,且鳍状结构包括多个通道层,以及第一虚置栅极堆叠与第二虚置栅极堆叠位于鳍状结构上。方法还包括形成源极开口于第一虚置栅极堆叠与第二虚置栅极堆叠之间的鳍状结构中,以露出鳍状结构的侧壁;使源极开口延伸至基板中,以形成延伸的源极开口;形成半导体插塞于延伸的源极开口中;形成源极结构于延伸的源极开口中的半导体插塞与通道层的露出侧壁上;平坦化基板以露出半导体插塞;在平坦化基板之后,将基板置换成背侧介电层;沉积金属层于背侧介电层与露出的半导体插塞上;以及进行退火制程使金属层与露出的半导体插塞之间产生硅化反应。
附图说明
图1是本发明一或多个实施例中,具有背侧源极/漏极接点的半导体装置的形成方法的流程图。
图2至图25是本发明一或多个实施例中,在图1的方法的制作制程时的工件的部分剖视图。
其中,附图标记说明如下:
I-I':剖面
W1:第一宽度
W2:第二宽度
100:方法
102,104,106,108,110,112,114,116,118,120,122,124,126,128,130:步骤
200:工件
202:基板
203:隔离结构
204:鳍状结构
204C:通道区
204D:漏极区
204S:源极区
206:牺牲层
208:通道层
210:虚置栅极堆叠
211:虚置介电层
212:虚置栅极层
213:氧化硅层
214:氮化硅层
215:栅极顶部硬遮罩层
216:栅极间隔物层
218:内侧间隔物结构
220:第一遮罩膜
222D:漏极开口
222S:源极开口
224:半导体插塞
226:第一外延层
228:第二外延层
230:源极结构
231:第二遮罩膜
232:第三外延层
234:第四外延层
236:漏极结构
240:接点蚀刻停止层
242:第一层间介电层
250:栅极结构
252:凹陷
254:锥形凹陷
255:硬遮罩层
256:硬遮罩结构
258:保护衬垫层
260:背侧介电层
262:硅化物前驱物
264:背侧源极接点
266:背侧电源轨
268:绝缘层
300:硅化前的布植制程
400:第一退火制程
500:第二退火制程
2020:侧壁部分
2080:通道组件
2220:延伸的源极开口
具体实施方式
下述详细描述可搭配图式说明,以利理解本发明的各方面。值得注意的是,各种结构仅用于说明目的而未按比例绘制,如本业常态。实际上为了清楚说明,可任意增加或减少各种结构的尺寸。
下述内容提供的不同实施例或例子可实施本发明实施例的不同结构。特定构件与排列的实施例是用以简化本公开而非局限本发明。举例来说,形成第一构件于第二构件上的叙述包含两者直接接触,或两者之间隔有其他额外构件而非直接接触。此外,本发明的多种实例可重复采用相同标号以求简洁,但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。
此外,空间性的相对用语如「下方」、「其下」、「下侧」、「上方」、「上侧」、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件,而非局限于图示方向。元件亦可转动90°或其他角度,因此方向性用语仅用以说明图示中的方向。
此外,当数值或数值范围的描述有「约」、「近似」、或类似用语时,旨在涵盖合理范围内的数值,如本技术领域中具有通常知识者考量到制造过程中产生的固有变化。举例来说,基于与制造具有与数值相关的已知制造容许范围,数值或范围涵盖包括所述数目的合理范围,例如在所述数目的+/-10%以内。举例来说,材料层的厚度为约5nm且本技术领域中具有通常知识者已知沉积材料层的制造容许范围为15%时,其包含的尺寸范围为4.25nm至5.75nm。
本发明实施例一般关于具有背侧源极/漏极接点的半导体装置的形成方法,更特别关于硅化物所组成的背侧源极/漏极接点的形成方法。
现有的基板上的晶体管的源极/漏极接点与栅极接点,可连接晶体管的源极/漏极结构至基板前侧上的内连线结构。随着集成电路装置的尺寸缩小,源极/漏极接点和栅极接点之间的紧密间距会减少这些接点的制程容许范围,并增加接点之间的寄生电容。背侧电源轨结构为解决接点拥挤的现代解方。在一些现有制程中,形成源极/漏极结构与前侧源极/漏极接点之后,可翻转基板并自基板背侧蚀刻背侧接点开口。由于形成背侧接点开口的步骤蚀刻并露出源极/漏极结构,此步骤可能有损伤源极/漏极结构的风险。损伤源极/漏极结构可能会增加接点电阻,并可能非预期地释放原本应施加至通道组件上的应力。
本发明实施例提供多桥通道晶体管所用的背侧源极/漏极接点的形成方法。在方法的一例中,提供工件。工件包括鳍状结构位于基板上,以及虚置栅极堆叠位于鳍状结构的通道区上。采用虚置栅极堆叠作为蚀刻遮罩,并使鳍状结构的源极区与漏极区凹陷以形成源极开口与漏极开口。源极开口可进一步选择性地延伸至基板中,以形成延伸的源极开口。沉积半导体插塞于延伸的源极开口中,并沉积源极结构于半导体插塞上。在形成源极结构之后,沉积漏极结构于漏极开口中。接着上下翻转工件使工件的背侧朝上。在平坦化基板背侧以露出半导体插塞之后,可形成硬遮罩结构于露出的半导体插塞上。接着移除基板并置换成背侧介电层。接着沉积硅化物前驱物于半导体插塞与背侧介电层上。接着进行退火制程以造成硅化物前驱物与半导体插塞之间的硅化反应。硅化反应可使半导体插塞转变成背侧源极接点,其组成为金属硅化物。由于本发明实施例形成背侧源极接点的方法不需移除半导体插塞并自背侧露出源极结构,因此没有损伤源极结构的相关风险。
本发明多种实施例将搭配图式详细说明。在此考量下,图1为本发明一些实施例中,形成半导体装置的方法100的流程图。方法100仅为举例而非局限本发明实施例至方法100实际记载的内容。在方法100之前、之中、与之后可提供额外步骤,且方法的额外实施例可置换、省略、或调换一些所述步骤。此处不详述所有步骤以简化说明。方法100将搭配图2至图25说明如下,其为工件200在一实施例的方法100的不同制作阶段的部分剖视图。由于制作制程的结果为制作工件200成半导体装置,因此工件200可依内容需求而视作半导体装置。此外,本发明实施例采用类似标号标示类似结构,除非另外说明。
如图1及图2所示,方法100的步骤102接收工件200。在所述实施例中,工件200包括基板202与鳍状结构204位于基板202上。鳍状结构204的长度方向沿着X方向延伸,且可分成通道区204C、源极区204S、与漏极区204D。在图2中,工件200亦包含虚置栅极堆叠210位于鳍状结构204的通道区204C上。图2显示两个虚置栅极堆叠210,但工件200可包含更多的虚置栅极堆叠210。基板202可为半导体基板如硅基板。基板202亦可包含其他半导体材料如锗、碳化硅、硅锗、或钻石。可自交错的半导体层的垂直堆叠与基板202的一部分形成鳍状结构204,且形成方法可采用微影与蚀刻步骤的组合。在一些例子中,图案化鳍状结构204的方法可采用双重图案化或多重图案化制程,其产生的图案间距小于采用单一的直接光微影制程所得的图案间距。蚀刻制程可包含干蚀刻、湿蚀刻、反应性离子蚀刻、及/或其他合适制程。在所述实施例中,交错的半导体层的垂直堆叠可包含多个通道层208与多个牺牲层206。多个通道层208与多个牺牲层206可交错。在一些实施例中,多个通道层208可包含硅,而多个牺牲层206可包含硅锗。通道层208与牺牲层206可外延沉积于基板202上,其形成方法可采用分子束外延、气相外延、超高真空化学气相沉积、及/或其他合适的外延成长制程。
虽然未图示于图2中,隔离结构203(如图23所示)亦形成于鳍状结构204周围,以隔离鳍状结构204与相邻的鳍状结构。在一些实施例中,隔离结构沉积于定义鳍状结构204所用的沟槽中。这些沟槽可延伸穿过通道层208与牺牲层206并止于基板202中。隔离结构亦可视作浅沟槽隔离结构。在一制程的例子中,沉积隔离结构所用的介电材料于工件200上,且沉积方法可采用化学气相沉积、次压化学气相沉积、可流动的化学气相沉积、物理气相沉积、旋转涂布、及/或其他合适制程。接着可平坦化沉积的介电材料并使其凹陷,直到鳍状结构204隆起高于隔离结构。隔离结构所用的介电材料可包含氧化硅、氮氧化硅、氟硅酸盐玻璃、低介电常数的介电层、上述的组合、及/或其他合适材料。
在一些实施例中,采用栅极置换制程(或栅极后制制程),其中虚置栅极堆叠210作为功能栅极结构所用的占位物。其他制程与设置亦属可能。为了形成虚置栅极堆叠210,可沉积虚置介电层211、虚置栅极层212、与栅极顶部硬遮罩层215于工件200上。沉积这些层状物的方法可采用低压化学气相沉积、化学气相沉积、等离子体辅助化学气相沉积、物理气相沉积、热氧化、电子束蒸镀、其他合适的沉积技术、或上述的组合。虚置介电层211可包含氧化硅。虚置栅极层212可包含多晶硅。栅极顶部遮罩层215可为多层结构,其包含氧化硅层213与氮化硅层214。采用光微影与蚀刻制程,可图案化栅极顶部硬遮罩层215。光微影制程可包含涂布光阻(如旋转涂布)、软烘烤、对准光罩、曝光后烘烤、显影光阻、冲洗、干燥(旋干及/或硬烘烤)、其他合适的微影技术、及/或上述的组合。蚀刻制程可包含干蚀刻(如反应性离子蚀刻)、湿蚀刻、及/或其他蚀刻方法。之后采用图案化的栅极顶部硬遮罩层215作为蚀刻遮罩,接着蚀刻虚置介电层211与虚置栅极层212以形成虚置栅极堆叠210。如图2所示,虚置栅极堆叠210之下的鳍状结构204的部分为通道区204C。通道区204C与虚置栅极堆叠210亦定义不与虚置栅极堆叠210垂直重叠的源极区204S与漏极区204D。每一通道区204C沿着X方向位于源极区204S与漏极区204D之间。
如图2所示,工件200亦包含沿着虚置栅极堆叠210的侧壁与鳍状结构204的上表面的栅极间隔物层216。在一些实施例中,形成栅极间隔物层216的方法包括顺应性沉积一或多个介电层于工件200上。在一制程的例子中,可采用化学气相沉积、次压化学气相沉积、或原子层沉积以沉积栅极间隔物层216所用的一或多个介电层。一或多个介电层可包含氧化硅、氮化硅、碳化硅、氮氧化硅、碳氮化硅、碳氧化硅、碳氮氧化硅、及/或上述的组合。
如图1及图3所示,方法100的步骤104使鳍状结构204的源极区204S与漏极区204D凹陷,以形成源极开口222S与漏极开口222D。在沉积栅极间隔物层216之后,虚置栅极堆叠210与沿着虚置栅极堆叠的侧壁的栅极间隔物层216可作为蚀刻制程的蚀刻遮罩,而蚀刻制程可非等向蚀刻鳍状结构204的源极区204S与漏极区204D。非等向蚀刻源极区204S与漏极区204D,以分别形成源极开口222S与漏极开口222D。步骤104的蚀刻制程可为干蚀刻制程或合适的蚀刻制程。蚀刻制程的例子可实施含氧气体、氢气、含氟气体(如四氟化碳、六氟化硫、二氟甲烷、氟仿、及/或六氟乙烷)、含氯气体(如氯气、氯仿、四氯化碳、及/或三氯化硼)、含溴气体(如溴化氢及/或溴仿)、含碘气体、其他合适气体及/或等离子体、及/或上述的组合。在图3所示的实施例中,源极开口222S与及极开口222D延伸穿过通道层208与牺牲层206的垂直堆叠。在一些实施方式中(未图示),源极开口222S与漏极开口222D可部分延伸至基板202中。源极开口222S与漏极开口222D中露出通道层208与牺牲层206的侧壁。
如图1及图3所示,方法100的步骤106形成内侧间隔物结构218。在形成源极开口222S与漏极开口222D之后,可使源极开口222S与漏极开口222D中露出的牺牲层206选择性地部分凹陷,以形成内侧间隔物凹陷(之后填入图3中的内侧间隔物结构218),且实质上不蚀刻露出的通道层208。在一实施例中,当通道层208基本上由硅组成,且牺牲层206基本上由硅锗组成时,使牺牲层206选择性部分凹陷的制程可采用选择性等向蚀刻制程(如选择性干蚀刻制程或选择性湿蚀刻制程),而牺牲层206的凹陷量可由蚀刻制程的时间控制。选择性干蚀刻制程可采用一或多种氟为主的蚀刻剂,比如氟气或碳氢氟化物。选择性湿蚀刻制程可包含氢氧化铵、过氧化氢、与水的混合物的蚀刻。在形成内侧间隔物凹陷之后,可沉积内侧间隔物材料于工件200上,包括沉积于内侧间隔物凹陷中。内侧间隔物材料层可包含氧化硅、氮化硅、碳氧化硅、碳氮氧化硅、碳氮化硅、金属氮化物、或合适的介电材料。接着回蚀刻沉积的内侧间隔物材料层,以移除通道层208的侧壁上的多余内侧间隔物材料层,进而形成内侧间隔物结构218,如图3所示。在一些实施例中,步骤106的回蚀刻制程可为干蚀刻制程,其可采用含氧气体、氢气、氮气、含氟气体(如四氟化碳、六氟化硫、二氟甲烷、氟仿、及/或六氟乙烷)、含氯气体(如氯气、氯仿、四氯化碳、及/或三氯化硼)、含溴气体(如溴化氢及/或溴仿)、含碘气体(如三氟碘化碳)、其他合适气体及/或等离子体、及/或上述的组合。
如图1及图4所示,方法100的步骤108的源极开口222S选择性延伸至基板202中,以形成延伸的源极开口2220。步骤108可形成第一遮罩膜220于工件200上,如图4所示。第一遮罩膜220可为硬遮罩层。第一遮罩膜220可包含氧化硅、氮化硅、氮氧化硅、碳氮氧化硅、碳化硅、或碳氧化硅。在制程的一例中,采用化学气相沉积或原子层沉积以沉积介电材料于工件上而形成第一遮罩膜220,接着采用旋转涂布或合适制程以沉积光阻层于第一遮罩膜220上。采用光微影制程图案化光阻层,以形成图案化的光阻层。接着采用图案化的光阻层作为蚀刻制程中的蚀刻遮罩,并进行蚀刻制程以图案化第一遮罩膜220。如图4所示,图案化的第一遮罩膜220可覆盖并保护漏极开口222D,并露出源极开口222S。接着进行非等向蚀刻制程,以进一步延伸源极开口222S至基板202中,以形成延伸的源极开口2220。在一些实施例中,延伸的源极开口2220延伸至基板202中的距离可介于约15nm至约35nm之间。在一些实施例中,步骤108的非等向蚀刻制程可为干蚀刻制程,其可采用含氧气体、氢气、含氟气体(如四氟化碳、六氟化硫、二氟甲烷、氟仿、及/或六氟乙烷)、含氯气体(如氯气、氯仿、四氯化碳、及/或三氯化硼)、含溴气体(如溴化氢及/或溴仿)、含碘气体、其他合适的气体及/或等离子体、及/或上述的组合。
如图1及图5所示,方法100的步骤110可形成半导体插塞224于延伸的源极开口2220中。在第一遮罩膜220仍覆盖漏极开口222D的侧壁时,可采用分子束外延、气相外延、超高真空化学气相沉积、及/或其他合适的外延成长制程以沉积半导体插塞224所用的半导体材料于延伸的源极开口2220中。在制程的一例中,半导体材料不只沉积于延伸的源极开口2220中的基板202的露出表面上,亦沉积于通道层208的露出侧壁上。接着进行回蚀刻制程以移除沉积在通道层208的侧壁上的半导体材料,以形成半导体插塞224,如图5所示。虽然图式中的半导体插塞224的上表面平坦,但其可凹陷如回蚀刻制程的结果。回蚀刻制程可包含干蚀刻制程、湿蚀刻制程、或上述的组合。在一些实施例中,可进行回蚀刻制程使半导体插塞224的上表面沿着Z方向低于基板202的上表面。半导体插塞224的组成可为硅锗。为了提供半导体插塞224的蚀刻选择性,半导体插塞224的锗浓度可高于源极结构230的锗浓度(见图7如下述)。举例来说,在需要n型多桥通道晶体管时,源极结构230的组成为硅且实质上不含锗,而半导体插塞224的组成为硅锗且具有约15%至45%的锗。在需要p型多桥通道晶体管时,源极结构230的组成为硅锗且具有约15%至约30%的锗,而半导体插塞224的组成为硅锗且具有约35%至45%的锗。
如图1、图6、及图7所示,方法100的步骤112形成源极结构230于延伸的源极开口2220中,以接触通道层208的侧壁。在一些实施例中,源极结构230包括第一外延层226与第二外延层228位于第一外延层226上。由于第二外延层228与通道层208的侧壁隔有第一外延层226,第一外延层226亦可视作外侧层,而第二外延层228亦可视作内侧层。先以图6进行说明。在一些实施例中,第一外延层226的沉积方法可采用外延沉积制程如气相外延、超高真空化学气相沉积、分子束外延、及/或其他合适制程。外延成长制程可采用气体及/或液体的前驱物,其可选择性地与通道层208与半导体插塞224的半导体组成作用。第一外延层226沉积于通道层208的露出表面以及半导体插塞224的表面上。在一些例子中,过成长的第一外延层226可能会延伸于内侧间隔物结构218上。如此一来,第一外延层226可直接接触内侧间隔物结构218。因此第一外延层226耦接至通道层208。接着以图7作说明。接着采用外延沉积制程如气相外延、超高真空化学气相沉积、分子束外延、及/或其他合适制程以沉积第二外延层228于第一外延层226上。外延成长制程可采用气体及/或液体前驱物,其可选择性地与第一外延层226的半导体组成作用。在所述实施例中,第二外延层228可与通道层208隔有第一外延层226。第一外延层226与第二外延层228可一起视作源极结构230。
第一外延层226与第二外延层228可为n型或p型,端视之后形成的多桥通道晶体管的导电型态而定,n型外延层的例子可包含硅、掺杂磷的硅(如磷化硅)、掺杂砷的硅(如砷化硅)、掺杂锑的硅(如锑化硅)、或其他合适材料,其可在外延制程时导入n型掺质如磷、砷、或锑以原位掺杂。p型外延层的例子可包含锗、掺杂镓的硅锗(如硅锗镓)、掺杂硼的硅锗(如硼化硅锗)、或其他合适材料,其可在外延制程时导入p型掺质如硼或镓以原位掺杂。当给定的多桥通道晶体管的第一外延层226与第二外延层228为相同导电型态时,其可具有不同的掺杂浓度以降低接点电阻。举例来说,在需要n型多桥通道晶体管时,第一外延层226与第二外延层228可包含掺杂磷的硅(如磷化硅),且第二外延层228中的磷掺杂浓度大于第一外延层226中的磷掺杂浓度。在需要p型多桥通道晶体管时,第一外延层226与第二外延层228可包含掺杂硼的硅锗(如硼化硅锗),且第二外延层228中的硼掺杂浓度大于第一外延层226中的硼掺杂浓度。
如上所述,源极结构230(特别是第一外延层226)的锗浓度小于半导体插塞224的锗浓度。举例来说,在需要n型多桥通道晶体管时,第一外延层226的组成为硅且实质上不含锗,而半导体插塞224的组成为硅锗且具有约15%至45%的锗。在需要p型多桥通道晶体管时,第一外延层226的组成为硅锗且具有约15%至约30%的锗,而半导体插塞224的组成为硅锗且具有约35%至45%的锗。
如图1及图8所示,方法100的步骤114形成漏极结构236于漏极区204D上。步骤114形成第二遮罩膜231于工件200上,如图8所示。第二遮罩膜231可为图案化的硬遮罩层。第二遮罩膜231可包含氧化硅、氮化硅、氮氧化硅、碳氮氧化硅、碳化硅、或碳氧化硅。在制程的例子中,采用化学气相沉积或原子层沉积以沉积介电材料于工件上而形成第二遮罩膜231,接着采用旋转涂布或合适制程以沉积光阻层于第二遮罩膜231上。接着采用光微影制程以图案化光阻层而形成图案化的光阻层。接着以图案化的光阻层作为蚀刻制程中的蚀刻遮罩,并进行蚀刻制程以图案化第二遮罩膜231。如图8所示,在露出漏极开口222D时,以图案化的第二遮罩膜231覆盖或保护源极结构230。
在一些实施例中,漏极结构236包括第三外延层232与第四外延层234位于第三外延层232上。由于第四外延层234与通道层208的侧壁隔有第三外延层232,第三外延层232亦可视作外侧层,而第四外延层234亦可视作内侧层。第三外延层232的形成方法与组成可与第一外延层226的形成方法与组成类似。在一些实施例中,第三外延层232的沉积方法可采用外延沉积制程,比如气相外延、超高真空化学气相沉积、分子束外延、及/或其他合适制程。外延成长制程可采用气体及/或液体前驱物,其可选择性地与通道层208与基板202的半导体组成作用。第三外延层232沉积于通道层208的露出表面与基板202的表面上。在一些例子中,过成长的第三外延层232可延伸于内侧间隔物结构218上。如此一来,第三外延层232可直接接触内侧间隔物结构218。因此第三外延层232耦接至通道层208。接着采用外延沉积制程如气相外延、超高真空化学气相沉积、分子束外延、及/或其他合适制程,以沉积第四外延层234于第三外延层232上。外延成长制程可采用气体及/或液体前驱物,其可选择性地与第三外延层232的半导体组成作用。在所述实施例中,第四外延层234可与通道层208隔有第三外延层232。第三外延层232与第四外延层234可一起视作漏极结构236。
第三外延层232与第四外延层234可为n型或p型,端视之后形成的多桥通道晶体管的导电型态而定,n型外延层的例子可包含硅、掺杂磷的硅(如磷化硅)、掺杂砷的硅(如砷化硅)、掺杂锑的硅(如锑化硅)、或其他合适材料,其可在外延制程时导入n型掺质如磷、砷、或锑以原位掺杂。p型外延层的例子可包含锗、掺杂镓的硅锗(如硅锗镓)、掺杂硼的硅锗(如硼化硅锗)、或其他合适材料,其可在外延制程时导入p型掺质如硼或镓以原位掺杂。在给定的多桥通道晶体管的第三外延层232与第四外延层234为相同导电型态时,其可具有不同的掺杂浓度以降低接点电阻。举例来说,当需要n型多桥通道晶体管时,第三外延层232与第四外延层234可包含掺杂磷的硅(如磷化硅),且第四外延层234中的磷掺杂浓度大于第三外延层232中的磷掺杂浓度。当需要p型多桥通道晶体管时,第三外延层232与第四外延层234可包含掺杂硼的硅锗(如硼化硅锗),且第四外延层234中的硼掺杂浓度大于第三外延层232中的硼掺杂浓度。
如图1及图9所示,方法100的步骤116沉积接点蚀刻停止层240与第一层间介电层242。接点蚀刻停止层240可包含氮化硅、氮氧化硅、及/或本技术领域已知的其他材料,且其形成方法可为原子层沉积、等离子体辅助化学气相沉积制程、及/或其他合适的沉积或氧化制程。如图9所示,接点蚀刻停止层240可沉积于源极结构230(包含第一外延层226与第二外延层228)与漏极结构236(包含第三外延层232与第四外延层234)的上表面上,以及栅极间隔物层216的侧壁上。在沉积接点蚀刻停止层240之后,以等离子体辅助化学气相沉积制程或其他合适的沉积技术沉积第一层间介电层242于工件200上。第一层间介电层242的材料可包含四乙氧基硅烷的氧化物、未掺杂的硅酸盐玻璃、或掺杂氧化硅(如硼磷硅酸盐玻璃、氟硅酸盐玻璃、磷硅酸盐玻璃、或硼硅酸盐玻璃)、及/或其他合适的介电材料。在一些实施例中,形成第一层间介电层242之后可退火工件200,以改善第一层间介电层242的完整性。
如图1及图10所示,方法100的步骤118将虚置栅极堆叠210置换成栅极结构250。为了移除多余材料并露出虚置栅极堆叠210的上表面,可对工件200进行平坦化制程如化学机械研磨制程。由于露出虚置栅极堆叠210,步骤118之后可移除虚置栅极堆叠210。移除虚置栅极堆叠210的方法可包含一或多道蚀刻制程,其对虚置栅极堆叠210的材料具有选择性。举例来说,移除虚置栅极堆叠210的方法可采用选择性湿蚀刻、选择性干蚀刻、或上述的组合。在移除虚置栅极堆叠210之后,可露出通道区204C中的通道层208与牺牲层206的侧壁与上表面。在移除虚置栅极堆叠210之后,可选择性移除通道区204C中的牺牲层206,以释放通道层208而作为通道组件2080。在制程的一些例子中,可采用选择性干蚀刻制程或选择性湿蚀刻制程移除牺牲层206。选择性干蚀刻制程可采用一或多种氟为主的蚀刻剂如氟气或碳氢氟化物。选择性湿蚀刻制程可包含氢氧化铵、过氧化氢、与水的混合物的蚀刻。
步骤118亦沉积栅极结构250于通道区204C中。如图10所示,沉积每一栅极结构250以包覆每一通道组件2080。每一栅极结构250可包含界面层、栅极介电层位于界面层上、与栅极层位于栅极介电层上。在一些实施例中,界面层包括氧化硅且可形成于预清洁制程中。预清洁制程的例子可采用RCA的标准清洁液-1(氢氧化铵、过氧化氢、与水的混合物)及/或RCA的标准清洁液-2(氯化氢、过氧或氢、与水的混合物)。栅极介电层亦可视作高介电常数的介电层,因其介电常数大于氧化硅的介电常数(约3.9)。栅极介电层沉积于界面层上的方法可采用原子层沉积、化学气相沉积、及/或其他合适方法。栅极介电层可包含氧化铪。栅极介电层可改为包含其他高介电常数的介电层,比如氧化钛、氧化锆铪、氧化钽、氧化铪硅、二氧化锆、氧化锆硅、氧化镧、氧化铝、氧化锆、氧化钇、钛酸锶、钛酸钡、氧化钡锆、氧化铪镧、氧化镧硅、氧化铝硅、氧化铪钽、氧化铪钛、钛酸钡锶、氮化硅、氮氧化硅、上述的组合、或其他合适材料。
接着沉积栅极层于栅极介电层上,且沉积方法可采用原子层沉积、物理气相沉积、化学气相沉积、电子束蒸镀、或其他合适方法。栅极层可包含单层或多层结构,比如具有选定功函数以增进装置效能的金属层(功函数金属层)、衬垫层、湿润层、第一粘着层、金属合金、或金属硅化物的多种组合。举例来说,栅极层可包含氮化钛、钛铝、氮化钛铝、氮化钽、钽铝、氮化钽铝、碳化钽铝、碳氮化钽、铝、钨、镍、钛、钌、钴、铂、碳化钽、氮化钽硅、铜、其他耐火金属、其他合适的金属材料、或上述的组合。此外,半导体装置如工件200包括n型多桥通道晶体管与p型多桥通道晶体管时,可分开形成n型多桥通道晶体管与p型多桥通道晶体管所用的不同栅极层,其可包含不同的功函数金属层(比如提供不同的n型与p型的功函数金属层)。在一些例子中,可对工件200进行化学机械研磨制程,以提供平坦的上表面。
如图1、图11、及图12所示,方法100的步骤120翻转工件200并平坦化基板202。可对背侧朝上的工件200进行步骤120。在翻转工件200的制程例子中,可将载板接合至工件200的前侧或形成于工件200的前侧上的内连线结构(未图示)。接着翻转具有载板的工件200。在一些例子中,将载板接合至工件200的方法可为熔融接合、采用粘着层、或上述的组合。在一些例子中,载板的组成可为半导体材料(如硅)、蓝宝石、玻璃、聚合物材料、或其他合适材料。在采用熔融接合的实施例中,载板包含底部氧化物层,而工件200(或其上的内连线结构,若存在)包含顶部氧化物层。在处理底部氧化物层与顶部氧化物层之后,可使其彼此对压接触以在室温或升温下直接接合。在将载板接合至工件200(或内连线结构,若存在)之后,可上下翻转工件200,如图11所示。在翻转工件200之后,可采用化学机械研磨制程平坦化工件200的背侧,直到露出隔离结构与半导体插塞224,如图12所示。
如图1及图13所示,方法100的步骤122可回蚀刻半导体插塞224。在一些实施例中,步骤122的回蚀刻可采用等向蚀刻制程。举例来说,步骤122的回蚀刻可包含氢氧化铵、过氧化氢、与水的混合物蚀刻,其蚀刻硅锗的速率大于蚀刻硅的速率。如图13所示,步骤122的回蚀刻可形成凹陷252。
如图1、图14、图15、及图16所示,方法100的步骤124形成硬遮罩结构256于半导体插塞224上。步骤124可包含使顶部角落圆润化的制程(如图14所示)、沉积硬遮罩层255(如图15所示)、以及回蚀刻硬遮罩层255以形成硬遮罩结构256(如图16所示)。如图14所示,一些实施例可进行斜向布植与等离子体蚀刻使凹陷252的顶部角落圆润化,进而形成锥形凹陷254。锥形凹陷254包括的侧壁可沿着锥形凹陷254至基板202的深度倾斜。形成锥形凹陷254的方法可视作顶部角落的圆润化制程。如图15所示,沉积硬遮罩层255于工件200的背侧上,包括沉积于锥形凹陷254与基板202上。在一些实施例中,硬遮罩层255的沉积方法可采用等离子体辅助化学气相沉积、化学气相沉积、原子层沉积、等离子体辅助原子层沉积、或合适的沉积方法。硬遮罩层255可包含氮化硅、碳氮化硅、碳化硅、或金属氧化物。接着回蚀刻沉积的硬遮罩层255,直到露出基板202,如图16所示。回蚀刻硬遮罩层255的结果,是形成硬遮罩结构256于锥形凹陷254中。硬遮罩结构256可延续锥形凹陷254的轮廓,且可包含锥形侧壁。
如图1、图17、及图18所示,方法100的步骤126将基板202置换成背侧介电层260。置换制程包括移除基板202,以及沉积背侧介电层260于移除基板202处。如图17所示,由于硬遮罩结构256保护半导体插塞224,可进行非等向蚀刻制程以蚀刻移除硬遮罩结构256未保护的基板202。非等向蚀刻制程的例子可采用含氟气体(如四氟化碳、六氟化硫、二氟甲烷、氟仿、及/或六氟乙烷)、含氯气体(如氯气、氯仿、四氯化碳、及/或三氯化硼)、含溴气体(如溴化氢及/或溴仿)、含碘气体、卤素氟化物气体的混合物、其他合适气体、及/或上述的组合的等离子体。在一些例子中,可选择非等向蚀刻制程的化学剂,使其蚀刻介电材料与栅极结构250的速率较低。如图17所示,进行非等向蚀刻制程,直到露出栅极结构250。在一些实施例中,由于硬遮罩结构256的锥形侧壁,基板202的侧壁部分2020可维持非等向蚀刻制程的结果。
如图18所示,移除基板202之后可沉积背侧介电层260于工件200的背侧上,且沉积方法可为可流动的化学气相沉积、化学气相沉积、等离子体辅助化学气相沉积、旋转涂布、或合适的制程。背侧介电层260可包含氧化硅,或与第一层间介电层242类似的组成。在形成背侧介电层260之后,可由化学机械研磨制程平坦化工件200的背侧,以移除硬遮罩结构256并露出侧壁部分2020与半导体插塞224的表面,如图18所示。在图18所示的一些实施例中,沉积背侧介电层260之前可沉积保护衬垫层258于工件200的背侧上,包括沉积于侧壁部分2020、栅极结构250、最底部的内侧间隔物结构218、与漏极结构236上。在一些实施例中,保护衬垫层258可包含氮化硅或碳氮化硅,且其沉积方法可采用化学气相沉积、原子层沉积、或合适的沉积技术。
如图1与图19至图22所示,方法100的步骤128使半导体插塞224转变成背侧源极接点264。步骤128可包含进行硅化前的布植制程300(如图19所示)、沉积硅化物前驱物262于工件200上(如图20所示)、进行第一退火制程400(如图21所示)、移除多余的硅化物前驱物(如图22所示)、与进行第二退火制程500(如图22所示)。如图19所示,硅化前的布植制程300可布植半导体物种如锗于半导体插塞224与侧壁部分2020中,以提供更一致的锗分布以利形成硅化物。在一些实施例中,在硅化前的布植制程300之后,可对工件200进行预清洁制程。预清洁制程可采用氩气、氢气、氨、三氟化氮、或上述的组合的等离子体,其有助于自工件200的背侧移除不想要的碎屑。
在硅化前的布植制程300与预清洁制程之后,可沉积硅化物前驱物262于工件200的背侧上以接触半导体插塞224与侧壁部分2020,如图20所示。在一些实施例中,硅化物前驱物262可包含金属,其可与硅反应形成金属硅化物。在一些例子中,硅化物前驱物262可包含镍、铂、或钛。在一些实施例中,硅化物前驱物262包括镍,因为镍在硅中具有高扩散性,且最终的镍硅化物其导电特性。在一些实施方式中,硅化物前驱物262的沉积方法可采用物理气相沉积或化学气相沉积。如图20所示,沉积的硅化物前驱物262直接接触背侧介电层260、保护衬垫层258、侧壁部分2020、与半导体插塞224。
如图21所示,在沉积硅化物前驱物262之后,可进行第一退火制程400使硅化物前驱物262与半导体插塞224及侧壁部分2020之间产生硅化反应。在一些实施例中,第一退火制程400可为快速热退火制程、雷射峰值退火制程、快闪退火制程、或炉退火制程。第一退火制程400的退火温度可介于约200℃至约300℃之间。选择退火温度以利硅化物前驱物262扩散至半导体插塞224与侧壁部分2020,可促进硅化物前驱物262与半导体插塞224及侧壁部分2020之间的硅化反应。第一退火制程400可使非导电的半导体插塞224转换成导电的背侧源极接点264。背侧源极接点264可包含镍硅化物、铂硅化物、或钛硅化物,以及锗。
如图22所示,步骤128亦包括在第一退火制程400之后,移除多余的硅化物前驱物262。在一些实施例中,可由湿蚀刻制程移除多余的硅化物前驱物262,直到露出背侧介电层260与背侧源极接点264。此处的湿蚀刻制程包含的化学剂可对硅化物前驱物262具有选择性。在一些例子中,湿蚀刻制程可采用过氧化氢、氢氟酸、硝酸、氯化氢、硫酸、或三氯化铁溶液。自工件200的背侧露出背侧源极接点264,且可进行第二退火制程500以增加背侧源极接点264中的金属硅化物其更导电的相,以活化背侧源极接点264。举例来说,当背侧源极接点264的组成为镍硅化物时,可进行第二退火制程500以增加更导电(电阻较低)的镍硅化物、二镍硅化物、或镍二硅化物相。在一些实施例中,第二退火制程500可为快速热退火制程、雷射峰值退火制程、快闪退火制程、或炉退火制程。第二退火制程500的退火温度可大于第一退火制程的退火温度。在一些例子中,第二退火制程500的温度可介于约300℃至约400℃之间。
如图1、图23、图24、及图25所示,方法100的步骤130形成背侧电源轨266。图24显示图23中的源极区204S沿着剖面I-I'的剖视图。图25显示图23中的工件200翻转之后的剖视图。背侧电源轨266可埋置于图24所示的绝缘层268中。在一些实施例中,绝缘层268的组成可与第一层间介电层242类似,且可沉积于工件200的背侧上,包括沉积于背侧介电层260、保护衬垫层258、隔离结构、与背侧源极接点264上,且其沉积方法可采用旋转涂布、可流动的化学气相沉积、或化学气相沉积。接着可图案化电源轨沟槽于绝缘层268中。接着可沉积阻障层与金属填充材料于电源轨沟槽中,以形成背侧电源轨266。在一些实施例中,背侧电源轨266中的阻障层可包含氮化钛、氮化钽、氮化钴、氮化镍、或氮化钨,且背侧电源轨266中的金属填充材料可包含钛、钌、铜、镍、钴、钨、钽、或钼。阻障层与金属填充层的沉积方法可采用物理气相沉积、化学气相沉积、原子层沉积、或无电镀。可进行平坦化制程如化学机械研磨制程,以移除绝缘层上的多余材料。背侧电源轨266直接接触并电性耦接至背侧源极接点264,如图23、24、及25所示。
如图23、图24、及图25所示,一些实施例的背侧源极接点264的侧壁沿着保护衬垫层258而实质上平直,但背侧源极接点264的侧壁可为气球状或侧向膨胀至隔离结构203中。此侧向膨胀为步骤108形成延伸的源极开口2220时的侧向侵蚀或蚀刻结果。在一些例子中,形成延伸的源极开口2220的步骤亦蚀刻隔离结构203,并使延伸的源极开口2220侧向膨胀至隔离结构203中。半导体插塞224沉积至延伸的源极开口2220中,因此延续了气球状或侧向膨胀的形状。半导体插塞224之后可转换成背侧源极接点264。图22及图23亦显示背侧源极接点264如何接合相邻的结构。如图22所示,背侧源极接点264直接接触保护衬垫层258,但与背侧介电层260分开。如图23所示,背侧源极接点264直接接触隔离结构203。保护衬垫层258不延伸于背侧源极接点264与隔离结构203之间。
如图25所示,源极结构230包括沿着X方向的第一宽度W1,而背侧源极接点264包括沿着X方向的第二宽度W2。由于不只由半导体插塞224,亦可由侧壁部分2020转变成背侧源极接点264,第二宽度W2大于第一宽度W1。在一些例子中,第一宽度W1可介于约12nm至约16nm之间,而第二宽度W2可介于约16nm至约22nm之间。在图25所示的一些实施例中,背侧源极接点264可接触最底部的内侧间隔物结构218(较靠近背侧介电层260)。
本发明实施例可提供优点。本发明实施例的方法形成金属硅化物的背侧源极接点,而不具有损伤源极/漏极结构的风险。采用本发明实施例的方法形成背侧源极接点,可沉积半导体插塞至延伸至工件基板中的延伸的源极开口中。在自基板背侧露出半导体插塞,并将基板置换成背侧介电层之后,可将半导体插塞转换成导电的背侧源极接点。在整个过程中,不会移除半导体插塞且不自背侧暴露源极/漏极结构置蚀刻剂。本发明实施例的方法因此可避免损伤源极/漏极结构的可能性。
本发明一例示性的实施例关于半导体结构。半导体结构包括多个第一通道组件,位于背侧介电层上;多个第二通道组件,位于背侧介电层上;硅化物结构,位于背侧介电层上;以及源极/漏极结构,位于硅化物结构上并延伸于第一通道组件与第二通道组件之间。硅化物结构延伸穿过背侧介电层的所有深度。
在一些实施例中,半导体结构还包括:背侧金属线路,位于背侧介电层之下。硅化物结构延伸于背侧金属线路与源极/漏极结构之间。在一些实施方式中,硅化物结构包括镍硅化物、铂硅化物、或钛硅化物。在一些例子中,半导体结构还包括介电衬垫层位于硅化物结构与背侧介电层之间。在一些实施例中,介电衬垫层包括氮化硅或碳氮化硅,而背侧介电层包括氧化硅。在一些实施例中,半导体结构还包括隔离结构,与背侧介电层相邻。隔离结构接触硅化物结构。在一些例子中,源极/漏极结构沿着一方向延伸于多个第一通道组件与多个第二通道组件之间,硅化物结构包括沿着该方向的第一宽度,且源极/漏极结构包括沿着该方向的第二宽度。第一宽度大于第二宽度。在一些实施例中,半导体结构还包括多个内侧间隔物结构,与第一通道组件交错。硅化物结构接触多个内侧间隔物结构的最底部的内侧间隔物结构。
本发明另一例示性的实施例关于半导体结构。半导体结构包括背侧金属线路;硅化物结构,位于背侧金属线路上并接触背侧金属线路;源极/漏极结构,位于硅化物结构上;接点蚀刻停止层,位于源极/漏极结构上;以及介电层,位于接点蚀刻停止层上。
在一些实施例中,硅化物结构包括镍硅化物、铂硅化物、或钛硅化物。在一些实施方式中,接点蚀刻停止层包括氮化硅或碳氮化硅,且其中介电层包括氧化硅。在一些实施例中,源极/漏极结构包括:外侧外延层;以及内侧外延层,位于外侧外延层上。在一些实施方式中,源极/漏极结构沿着一方向延伸于多个第一通道组件与多个第二通道组件之间。在一些例子中,硅化物结构包括沿着该方向的第一宽度,源极/漏极结构包括沿着该方向的第二宽度,且第一宽度大于第二宽度。在一些实施例中,硅化物结构包括硅与锗。
本发明又一例示性的实施例关于半导体结构的形成方法。方法包括:接收工件,其包括:鳍状结构位于基板上,且鳍状结构包括多个通道层,以及第一虚置栅极堆叠与第二虚置栅极堆叠位于鳍状结构上。方法还包括形成源极开口于第一虚置栅极堆叠与第二虚置栅极堆叠之间的鳍状结构中,以露出鳍状结构的侧壁;使源极开口延伸至基板中,以形成延伸的源极开口;形成半导体插塞于延伸的源极开口中;形成源极结构于延伸的源极开口中的半导体插塞与通道层的露出侧壁上;平坦化基板以露出半导体插塞;在平坦化基板之后,将基板置换成背侧介电层;沉积金属层于背侧介电层与露出的半导体插塞上;以及进行退火制程使金属层与露出的半导体插塞之间产生硅化反应。
在一些实施例中,半导体插塞包括硅锗。在一些实施方式中,金属层包括镍、铂、或钛。在一些例子中,置换基板的步骤包括:回蚀刻露出的半导体插塞;形成硬遮罩结构于回蚀刻的半导体插塞上;以及采用硬遮罩结构作为蚀刻遮罩并非等向蚀刻基板。在一些例子中,非等向蚀刻步骤保留基板的一部分,其沿着回蚀刻的半导体插塞的侧壁,其中退火制程进一步造成金属层与基板的部分之间的硅化反应。
上述实施例的特征有利于本技术领域中具有通常知识者理解本发明。本技术领域中具有通常知识者应理解可采用本发明作基础,设计并变化其他制程与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中具有通常知识者亦应理解,这些等效置换并未脱离本发明精神与范畴,并可在未脱离本发明的精神与范畴的前提下进行改变、替换、或更动。
Claims (10)
1.一种半导体结构,包括:
多个第一通道组件,位于一背侧介电层上;
多个第二通道组件,位于该背侧介电层上;
一硅化物结构,位于该背侧介电层上;以及
一源极/漏极结构,位于该硅化物结构上并延伸于所述第一通道组件与所述第二通道组件之间,
其中该硅化物结构延伸穿过该背侧介电层的所有深度。
2.如权利要求1所述的半导体结构,还包括:
一背侧金属线路,位于该背侧介电层之下,其中该硅化物结构延伸于该背侧金属线路与该源极/漏极结构之间。
3.如权利要求1所述的半导体结构,还包括:
一介电衬垫层位于该硅化物结构与该背侧介电层之间。
4.如权利要求1所述的半导体结构,
其中该源极/漏极结构沿着一方向延伸于多个第一通道组件与多个第二通道组件之间,
其中该硅化物结构包括沿着该方向的一第一宽度,
其中该源极/漏极结构包括沿着该方向的一第二宽度,
其中该第一宽度大于该第二宽度。
5.一种半导体结构,包括:
一背侧金属线路;
一硅化物结构,位于该背侧金属线路上并接触该背侧金属线路;
一源极/漏极结构,位于该硅化物结构上;
一接点蚀刻停止层,位于该源极/漏极结构上;以及
一介电层,位于该接点蚀刻停止层上。
6.如权利要求5所述的半导体结构,其中该源极/漏极结构沿着一方向延伸于多个第一通道组件与多个第二通道组件之间。
7.如权利要求6所述的半导体结构,
其中该硅化物结构包括沿着该方向的一第一宽度,
其中该源极/漏极结构包括沿着该方向的一第二宽度,
其中该第一宽度大于该第二宽度。
8.一种半导体结构的形成方法,包括:
接收一工件,其包括:
一鳍状结构位于一基板上,且该鳍状结构包括多个通道层,以及
一第一虚置栅极堆叠与一第二虚置栅极堆叠位于该鳍状结构上;
形成一源极开口于该第一虚置栅极堆叠与该第二虚置栅极堆叠之间的该鳍状结构中,以露出该鳍状结构的侧壁;
使该源极开口延伸至该基板中,以形成一延伸的源极开口;
形成一半导体插塞于该延伸的源极开口中;
形成一源极结构于该延伸的源极开口中的该半导体插塞与该通道层的露出侧壁上;
平坦化该基板以露出该半导体插塞;
在平坦化该基板之后,将该基板置换成一背侧介电层;
沉积一金属层于该背侧介电层与露出的该半导体插塞上;以及
进行一退火制程使该金属层与露出的该半导体插塞之间产生硅化反应。
9.如权利要求8所述的半导体结构的形成方法,其中置换该基板的步骤包括:
回蚀刻露出的该半导体插塞;
形成一硬遮罩结构于回蚀刻的该半导体插塞上;以及
采用该硬遮罩结构作为一蚀刻遮罩并非等向蚀刻该基板。
10.如权利要求9所述的半导体结构的形成方法,
其中非等向蚀刻步骤保留该基板的一部分,其沿着回蚀刻的该半导体插塞的侧壁,
其中该退火制程进一步造成该金属层与该基板的该部分之间的硅化反应。
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