TW202234640A - 半導體器件的觸點及其形成方法 - Google Patents
半導體器件的觸點及其形成方法 Download PDFInfo
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- TW202234640A TW202234640A TW110136093A TW110136093A TW202234640A TW 202234640 A TW202234640 A TW 202234640A TW 110136093 A TW110136093 A TW 110136093A TW 110136093 A TW110136093 A TW 110136093A TW 202234640 A TW202234640 A TW 202234640A
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Classifications
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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Abstract
根據本發明的一些實施例,一種半導體器件包括一基板上之一第一閘極電極、該第一閘極電極上之一第一導電觸點、該第一導電觸點上之一蝕刻停止層(ESL),及延伸穿過該ESL之一第二導電觸點。該第一導電觸點具有一第一寬度。該第二導電觸點具有一第二寬度,該第二寬度小於該第一寬度。該ESL懸在該第二導電觸點之一部分上。該第二導電觸點之一凸底面實體地接觸該第一導電觸點之一凹頂面。
Description
本發明實施例係有關半導體器件的觸點及其形成方法。
半導體器件用於諸如(例如)個人電腦、蜂巢式電話、數位相機及其他電子設備之各種電子應用中。半導體器件通常藉由在一半導體基板上循序沈積絕緣或介電層、導電層及半導體材料層及使用微影圖案化各種材料層以在其上形成電路組件及元件來製造。
半導體工業藉由不斷減小最小特徵大小來不斷提高各種電子組件(例如電晶體、二極體、電阻器、電容器等等)之整合密度,其允許更多組件整合至一給定面積中。
根據本發明的一實施例,一種半導體器件包括:一第一閘極電極,其位於一基板上;一第二閘極電極,其位於該基板上;一第一導電觸點,其位於該第一閘極電極上,該第一導電觸點具有一第一高度及一第一寬度;一第二導電觸點,其位於該第二閘極電極上,該第二導電觸點具有一第二高度及一第二寬度,該第二高度小於該第一高度,該第二寬度大於該第一寬度;一蝕刻停止層(ESL),其位於該第一導電觸點及該第二導電觸點上;一第三導電觸點,其延伸穿過該ESL,該ESL懸在該第三導電觸點之一部分上,該第三導電觸點之一凸底面實體接觸該第一導電觸點之一凹頂面,該第三導電觸點具有量測於該ESL之一底面處之一第三寬度;及一第四導電觸點,其延伸穿過該ESL,該ESL懸在該第四導電觸點之一部分上,該第四導電觸點之一凸底面實體接觸該第二導電觸點之一凹頂面,該第四導電觸點具有量測於該ESL之該底面處之一第四寬度,該第四寬度大於該第三寬度。
根據本發明的一實施例,一種半導體器件包括:一第一通道區域,其位於一半導體基板上;一第二通道區域,其位於該半導體基板上;一第一閘極結構,其位於該第一通道區域上,該第一閘極結構包括一第一閘極電極,該第一閘極電極具有一第一高度;一第二閘極結構,其位於該第二通道區域上,該第二閘極結構包括一第二閘極電極,該第二閘極電極具有一第二高度,該第二高度大於該第一高度;一第一介電層,其位於該第一閘極結構及該第二閘極結構上;一第一導電觸點,其位於該第一閘極電極上,該第一導電觸點延伸至該第一介電層之一頂面;一第二導電觸點,其位於該第二閘極電極上,該第二導電觸點延伸至該第一介電層之該頂面;一蝕刻停止層(ESL),其位於該第一介電層上,該ESL覆蓋該第一導電觸點之一部分及該第二導電觸點之一部分;一第三導電觸點,其包括:一第一底部部分,其位於該ESL之一下表面下方,在一俯視圖中,該第一底部部分由該第一導電觸點包圍,該第一底部部分在該ESL之該下表面下方延伸,該第一底部部分具有一第三寬度;及一第一頂部部分,其位於該ESL之該下表面上方;及一第四導電觸點,其包括:一第二底部部分,其位於該ESL之該下表面下方,在該俯視圖中,該第二底部部分由該第二導電觸點包圍,該第二底部部分在該ESL之該下表面下方延伸,該第二底部部分具有一第四寬度,該第四寬度大於該第三寬度;及一第二頂部部分,其位於該ESL之該下表面上方。
根據本發明的一實施例,一種形成一半導體器件之方法包括:在一第一閘極電極及一第二閘極電極上沈積一第一介電層,該第一閘極電極及該第二閘極電極自一基板延伸;穿過該第一介電層形成一第一導電材料,該第一導電材料之一第一部分具有一第一高度及一第一寬度,該第一導電材料之一第二部分具有一第二高度及一第二寬度,該第一高度大於該第二高度,該第二寬度大於該第一寬度;在該第一導電材料及該第一介電層上方形成一蝕刻停止層(ESL);在該ESL上沈積一第二介電層;穿過該第二介電層及該ESL蝕刻一第一開口,該第一開口延伸至該第一導電材料之該第一部分中,在一俯視圖中,該第一開口由該第一導電材料之該第二部分包圍,該ESL懸在該第一開口之一部分上;穿過該第二介電層及該ESL蝕刻一第二開口,該第二開口延伸至該第一導電材料之該第二部分中,在該俯視圖中,該第二開口由該第一導電材料包圍,該ESL懸在該第一開口之一部分上;及用一第二導電材料填充該第一開口及該第二開口。
以下揭露提供用於實施本發明之不同特徵之諸多不同實施例或實例。下文將描述組件及配置之特定實例以簡化本揭露。當然,此等僅為實例且不意在限制。例如,在以下描述中,使一第一構件形成於一第二構件上方或一第二構件上可包含其中形成直接接觸之該第一構件及該第二構件之實施例,且亦可包含其中額外構件可形成於該第一構件與該第二構件之間使得該第一構件及該第二構件可不直接接觸之實施例。另外,本揭露可在各種實例中重複元件符號及/或字母。此重複係為了簡單及清楚且其本身不指示所討論之各種實施例及/或組態之間的一關係。
此外,為便於描述,空間相對術語(諸如「下面」、「下方」、「下」、「上方」、「上」及其類似者)在本文中可用於描述一元件或構件與另一(些)元件或構件之關係,如圖中所繪示。空間相對術語除涵蓋圖中所描繪之定向之外,亦意欲涵蓋器件在使用或操作中之不同定向。可依其他方式定向設備(旋轉90度或依其他定向),且亦可因此解譯本文中所使用之空間相對描述詞。
根據一些實施例,提供一半導體器件之一互連結構及其形成方法。在一些實施例中,一閘極觸點形成於一閘極結構上。隨後,一接觸插塞形成於閘極觸點上。接觸插塞具有小於閘極觸點之一寬度,且包括一鉚釘形狀之接觸插塞之一底部部分在閘極觸點之一頂面下方延伸。接觸插塞之底部部分之鉚釘形狀可用於減少由來自對接觸插塞執行之一CMP之漿料對閘極觸點之非期望蝕刻。具有比接觸插塞更大之一寬度之閘極觸點可用於允許接觸插塞之底部部分之鉚釘形狀更寬及更淺,其可減少非期望接觸電阻且提高高頻寬記憶體之良率增益。
圖1繪示根據一些實施例之一FinFET之一實例之三維圖。FinFET包括一基板50 (例如一半導體基板)上之一鰭片52。隔離區域56放置於基板50中,且鰭片52在鄰近隔離區域56上方及自鄰近隔離區域56之間突出。儘管隔離區域56經描述/繪示為與基板50分離,但如本文中所使用,術語「基板」可用於係指僅半導體基板或包含隔離區域之一半導體基板。另外,儘管鰭片52繪示為基板50之一單一連續材料,但鰭片52及/或基板50可包括一單一材料或複數個材料。在此背景中,鰭片52係指在鄰近隔離區域56之間延伸之部分。
一閘極介電層92沿側壁且位於鰭片52之一頂面上方,且一閘極電極94位於閘極介電層92上方。源極/汲極區域82相對於閘極介電層92及閘極電極94放置於鰭片52之對置側中。圖1進一步繪示用於後圖中之參考剖面。剖面A-A沿閘極電極94之一縱向軸線且在(例如)垂直於FinFET之源極/汲極區域82之間的電流方向之一方向上。剖面B-B垂直於剖面A-A且沿鰭片52之一縱向軸線且在(例如) FinFET之源極/汲極區域82之間的一電流之一方向上。剖面C-C平行於剖面A-A且延伸穿過FinFET之一源極/汲極區域。為清楚起見,後續圖係指此等參考剖面。
本文中所討論之一些實施例係在使用一後閘極程序形成之FinFET之背景中討論。在其他實施例中,可使用一先閘極程序。此外,一些實施例考量用於平面器件中之態樣,諸如平面FET、奈米結構(例如奈米片、奈米線、環繞式閘極或其類似者)場效電晶體(NSFET)或其類似者。
圖2至圖20B係根據一些實施例之製造FinFET之中間階段之剖面圖。除多個鰭片/FinFET之外,圖2至圖7B繪示圖1中所繪示之參考剖面A-A。除多個鰭片/FinFET之外,圖8A、圖9A、圖10A、圖11A、圖12A、圖13A、圖14A、圖15A、圖16A及圖17A沿圖1中所繪示之參考剖面A-A繪示,且圖8B、圖9B、圖10B、圖11B、圖12B、圖13B、圖14B、圖14C、圖15B、圖16B、圖16C、圖16D、圖17B、圖17C、圖17D、圖18A、圖18B、圖19A、圖19B、圖20A及圖20B沿圖1中所繪示之一類似剖面B-B繪示。除多個鰭片/FinFET之外,圖10C及圖10D沿圖1中所繪示之參考剖面C-C繪示。
在圖2中,提供一基板50。基板50可為一半導體基板,諸如一塊體半導體、一絕緣體上半導體(SOI)基板或其類似者,其可經摻雜(例如,摻雜有一p型或n型摻雜劑)或未摻雜。基板50可為一晶圓,諸如一矽晶圓。一般而言,一SOI基板係形成於一絕緣體層上之一半導體材料之一層。絕緣體層可為(例如)埋藏氧化物(BOX)層、氧化矽層或其類似者。絕緣體層提供於一基板上,通常為一矽或玻璃基板。亦可使用其他基板,諸如一多層或梯度基板。在一些實施例中,基板50之半導體材料可包含:矽;鍺;一化合物半導體,其包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦;一合金半導體,其包含矽鍺、磷化砷鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦及/或磷化鎵銦砷;或其等之組合。
基板50具有一n型區域50N及一p型區域50P。n型區域50N可用於形成n型器件,諸如NMOS電晶體,例如n型FinFET。p型區域50P可用於形成p型器件,諸如PMOS電晶體,例如p型FinFET。n型區域50N可與p型區域50P實體分離(如由分隔線20所繪示),且任何數目個器件特徵(例如其他主動器件、摻雜區域、隔離結構等等)可放置於n型區域50N與p型區域50P之間。
在圖3中,鰭片52形成於基板50中。鰭片52係半導體條。在一些實施例中,鰭片52可藉由在基板50中蝕刻溝槽來形成於基板50中。蝕刻可為任何可接受蝕刻程序,諸如反應性離子蝕刻(RIE)、中性束蝕刻(NBE)、類似者或其等之一組合。蝕刻可為各向異性的。
鰭片可藉由任何適合方法圖案化。例如,鰭片52可使用一或多個光微影程序圖案化,其包含雙重圖案化或多重圖案化程序。一般而言,雙重圖案化或多重圖案化程序組合光微影及自對準程序以允許產生具有(例如)比可原本使用一單一直接光微影程序獲得之節距更小之節距之圖案。例如,在一個實施例中,一犧牲層形成於一基板上方且使用一光微影程序圖案化。間隔件使用一自對準程序形成於圖案化犧牲層旁邊。接著移除犧牲層,且接著可使用剩餘間隔件來圖案化鰭片。在一些實施例中,遮罩(或其他層)可留在鰭片52上。
在圖4中,一絕緣材料54形成於基板50上方且在鄰近鰭片52之間。絕緣材料54可為氧化物(諸如氧化矽)、氮化物、類似者或其等之一組合,且可藉由一高密度電漿化學氣相沈積(HDP-CVD)、一可流動CVD (FCVD)(例如一遠端電漿系統中之一基於CVD之材料沈積及後固化以使其轉換成另一材料,諸如氧化物)、類似物或其等之一組合。可使用藉由任何可接受程序形成之其他絕緣材料。在所繪示之實施例中,絕緣材料54係藉由一FCVD程序形成之氧化矽。一旦形成絕緣材料,則可執行一退火程序。在一實施例中,絕緣材料54經形成使得過量絕緣材料54覆蓋鰭片52。儘管絕緣材料54繪示為一單一層,但一些實施例可利用多個層。例如,在一些實施例中,可首先沿基板50及鰭片52之一表面形成一襯層(未展示)。其後,可在襯層上方形成一填充材料,諸如上文所討論之填充材料。
在圖5中,一移除程序應用於絕緣材料54以移除鰭片52上方之過量絕緣材料54。在一些實施例中,可利用一平坦化程序,諸如一化學機械拋光(CMP)、一回蝕程序、其等之組合或其類似者。平坦化程序暴露鰭片52,使得在平坦化程序完成之後,鰭片52及絕緣材料54之頂面齊平。在其中一遮罩留在鰭片52上之實施例中,平坦化程序可暴露遮罩或移除遮罩,使得在平坦化程序完成之後,遮罩或鰭片52之頂面分別與絕緣材料54齊平。
在圖6中,絕緣材料54經凹進以形成淺溝槽隔離(STI)區域56。絕緣材料54經凹進使得n型區域50N及p型區域50P中之鰭片52之上部分自鄰近STI區域56之間突出。此外,STI區域56之頂面可具有如一平面(如所繪示)、一凸面、一凹面(諸如凹陷)或其等之一組合。STI區域56之頂面可藉由一適當蝕刻形成為平坦、凸出及/或凹入。STI區域56可使用一可接受蝕刻程序(諸如對絕緣材料54之材料有選擇性之蝕刻程序(例如,以比鰭片52之材料更快之一速率蝕刻絕緣材料54之材料))凹進。例如,可使用使用(例如)稀氫氟(dHF)酸之氧化物移除。
相對於圖2至圖6描述之程序僅為可如何形成鰭片52之一個實例。在一些實施例中,鰭片可藉由一磊晶生長程序形成。例如,一介電層可形成於基板50之一頂面上方,且溝槽可穿過介電層蝕刻以暴露下伏基板50。同質磊晶結構可磊晶生長於溝槽中,且介電層可經凹進使得同質磊晶結構自介電層突出以形成鰭片。另外,在一些實施例中,異質磊晶結構可用於鰭片52。例如,圖5中之鰭片52可凹進,且不同於鰭片52之一材料可磊晶生長於凹進鰭片52上方。在此等實施例中,鰭片52包括凹進材料及放置於凹進材料上方之磊晶生長材料。在一更進一步實施例中,一介電層可形成於基板50之一頂面上方,且溝槽可穿過介電層蝕刻。接著,異質磊晶結構可使用不同於基板50之一材料磊晶生長於溝槽中,且介電層可經凹進使得異質磊晶結構自介電層突出以形成鰭片52。在其中磊晶生長同質磊晶或異質磊晶結構之一些實施例中,磊晶生長材料可在生長期間原位摻雜(其可避免先前及隨後植入),但原位及植入摻雜可一起使用。
此外,在n型區域50N (例如一NMOS區域)中磊晶生長不同於p型區域50P (例如一PMOS區域)中之材料之一材料可為有利的。在各種實施例中,鰭片52之上部分可由矽鍺(Si
xGe
1-x,其中x可在0至1之範圍內)、碳化矽、純鍺或實質上純鍺、III-V族化合物半導體、II-VI族化合物半導體或其類似者形成。例如,可用於形成III-V族化合物半導體之材料包含(但不限於)砷化銦、砷化鋁、砷化鎵、磷化銦、氮化鎵、砷化銦鎵、砷化銦鋁、銻化鎵、銻化鋁、磷化鋁、磷化鎵及其類似者。
此外,在圖6中,適當井(未展示)可形成於鰭片52及/或基板50中。在一些實施例中,一P井可形成於n型區域50N中,且一N井可形成於p型區域50P中。在一些實施例中,一P井或一N井形成於n型區域50N及p型區域50P兩者中。
在具有不同井類型之實施例中,用於n型區域50N及p型區域50P之不同植入步驟可使用一光阻劑及/或其他遮罩(未展示)達成。例如,一光阻劑可形成於n型區域50N中之鰭片52及STI區域56上方。光阻劑經圖案化以暴露基板50之p型區域50P。光阻劑可藉由使用一旋塗技術形成且可使用可接受光微影技術圖案化。一旦圖案化光阻劑,則在p型區域50P中執行一n型雜質植入,且光阻劑可充當一遮罩以實質上防止n型雜質植入至n型區域50N中。n型雜質可為植入區域中達等於或小於10
18cm
-3之一濃度(諸如在約10
16cm
-3至約10
18cm
-3之間)之磷、砷、銻或其類似者。在植入之後,移除光阻劑,諸如藉由一可接受灰化程序。
在p型區域50P之植入之後,一光阻劑形成於p型區域50P中之鰭片52及STI區域56上方。光阻劑經圖案化以暴露基板50之n型區域50N。光阻劑可藉由使用一旋塗技術形成且可使用可接受光微影技術圖案化。一旦圖案化光阻劑,則可在n型區域50N中執行一p型雜質植入,且光阻劑可充當一遮罩以實質上防止p型雜質植入至p型區域50P中。p型雜質可為植入區域中達等於或小於10
18cm
-3之一濃度(諸如在約10
16cm
-3至約10
18cm
-3之間)之硼、氟化硼、銦或其類似者。在植入之後,移除光阻劑,諸如藉由一可接受灰化程序。
在n型區域50N及p型區域50P之植入之後,可執行一退火以修復植入損壞且活化所植入之p型及/或n型雜質。在一些實施例中,可在生長期間原位摻雜磊晶鰭片之生長材料(其可避免植入),但原位及植入摻雜可一起使用。
在圖7A及圖7B中,用於形成虛設閘極之層係形成於鰭片52上。圖7A繪示其中可隨後形成相對較小閘極結構(參閱下文圖14B)之一第一閘極區域100A,且圖7B繪示其中可隨後形成相對較大閘極結構(參閱下文圖14B)之一第二閘極區域100B。隨後形成之閘極結構的大小差異可歸因於(例如)CMP在具有不同圖案密度之區域中的負載效應或凹陷效應。第一閘極區域100A及第二閘極區域100B可係實體地分離。第一閘極區域100A及第二閘極區域100B可各含有各自n型區域50N及p型區域50P。
參考圖7A及圖7B,一虛設介電層60經形成於鰭片52上。虛設介電層60可為(例如)氧化矽、氮化矽、其等之一組合,或其類似者,且可根據可接受技術來沈積或熱生長。應注意,僅出於繪示目的,虛設介電層60係展示為僅覆蓋鰭片52。在一些實施例中,虛設介電層60可經沈積使得虛設介電層60覆蓋STI區域56以在STI區域上方及隨後形成之虛設閘極層(參閱下文)與STI區域56之間延伸。
仍參考圖7A及圖7B,一虛設閘極層62A經形成於第一閘極區域100A中之虛設介電層60上方,且一虛設閘極層62B經形成於第二閘極區域100B中之虛設介電層60上方。虛設閘極層62A及62B可係沈積於虛設介電層60上方且接著經平坦化,諸如藉由各自CMP程序。在一些實施例中,虛設閘極層62A經形成且經平坦化至110 nm至130 nm之一範圍內之一高度H1,且虛設閘極層62B經形成且經平坦化至110 nm至130 nm之一範圍內之一高度H2。在其他實施例中,虛設閘極層62A及62B經形成至約相同高度。虛設閘極層62A及62B可為一導電或非導電材料,且可係選自包含非晶矽、多晶矽(polysilicon)、多晶矽鍺(poly-SiGe)、金屬氮化物、金屬矽化物、金屬氧化物及金屬之一群組。虛設閘極層62A及62B可係藉由物理氣相沈積(PVD)、CVD、濺射沈積或用於沈積選定材料之其他技術來沈積。虛設閘極層62A及62B可係由相對於隔離區域(例如STI區域56及/或虛設介電層60)之蝕刻具有一高蝕刻選擇性的其他材料製成。
進一步參考圖7A及圖7B,一遮罩層64形成於虛設閘極層62A及62B上方。遮罩層64可包含(例如)氮化矽、氮氧化矽或其類似者之一或多個層。在此實例中,一單一遮罩層64跨n型區域50N及p型區域50P形成。在一些實施例中,遮罩層64可在第一閘極區域100A及第二閘極區域100B中形成至不同厚度。
圖8A至圖20F繪示實施例器件之製造中之各種額外步驟。圖8A至圖20F繪示n型區域50N及p型區域50P之任一者中之特徵。例如,圖8A至圖20F中所繪示之結構可應用於n型區域50N及p型區域50P兩者。n型區域50N及p型區域50P之結構差異(若存在)描述於伴隨各圖之文字中。圖8A、圖9A、圖10A、圖10C、圖10D、圖11A、圖12A、圖13A、圖14A、圖15A、圖16A及圖17A繪示第一閘極區域100A及第二閘極區域100B中之特徵,圖8A、圖9A、圖10A、圖11A、圖12A、圖13A、圖14A、圖15A、圖16A及圖17A中所繪示之結構亦可應用於第一閘極區域100A及第二閘極區域100B兩者。第一閘極區域100A及第二閘極區域100B之結構差異(若存在)描述於伴隨各圖之文字中。圖8B、圖9B、圖10B、圖11B、圖12B、圖13B、圖14B、圖15B、圖16B及圖17B繪示由一分隔線22分離之第一閘極區域100A及第二閘極區域100B。
在圖8A及圖8B中,遮罩層64 (參閱圖7)可使用可接受光微影及蝕刻技術圖案化以形成遮罩74。遮罩74之圖案接著可轉印至虛設閘極層62。在一些實施例(未繪示)中,遮罩74之圖案亦可藉由一可接受蝕刻技術轉印至虛設介電層60以分別在第一閘極區域100A及第二閘極區域100B中形成虛設閘極72A及72B。虛設閘極72A及72B可統稱為虛設閘極72,如圖8A及圖8A之後的後續圖中所繪示。虛設閘極72A及72B覆蓋鰭片52之各自通道區域58。遮罩74之圖案可用於實體分離虛設閘極72A及72B之各者與相鄰虛設閘極。虛設閘極72A及72B亦可具有實質上垂直於各自磊晶鰭片52之縱向方向之一縱向方向。在一些實施例中,虛設閘極72A經圖案化以具有8 nm至36 nm之一範圍內之寬度W1且虛設閘極閘極72B經圖案化以具有72 nm至240 nm之一範圍內之寬度W2。
此外,在圖8A及圖8B中,閘極密封間隔件80可形成於虛設閘極72A及72B、遮罩74及/或鰭片52之暴露表面上。一熱氧化或一沈積及接著一各向異性蝕刻可形成閘極密封間隔件80。閘極密封間隔件80可由氧化矽、氮化矽、氮氧化矽或其類似者形成。
在形成閘極密封間隔件80之後,可執行輕摻雜源極/汲極(LDD)區域(未明確繪示)之植入。在具有不同器件類型之實施例中,類似於上文圖6中討論之植入,一遮罩(諸如一光阻劑)可形成於n型區域50N上方,同時暴露p型區域50P,且適當類型(例如p型)雜質可植入至p型區域50P中之暴露鰭片52中。接著可移除遮罩。隨後,一遮罩(諸如一光阻劑)可形成於p型區域50P上方,同時暴露n型區域50N,且適當類型雜質(例如n型)可植入至n型區域50N中之暴露鰭片52中。接著可移除遮罩。n型雜質可為先前討論之n型雜質之任何者,且p型雜質可為先前討論之p型雜質之任何者。輕摻雜源極/汲極區域可具有自約10
15cm
-3至約10
19cm
-3之一雜質濃度。一退火可用於修復植入損壞且活化植入雜質。
在圖9A及圖9B中,閘極間隔件86沿虛設閘極72A及72B及遮罩74之側壁形成於閘極密封間隔件80上。閘極間隔件86可藉由共形地沈積一絕緣材料且隨後各向異性地蝕刻絕緣材料來形成。閘極間隔件86之絕緣材料可為氧化矽、氮化矽、氮氧化矽、碳氮化矽、其等之一組合或其類似者。
應注意,上述揭露內容大體上描述形成間隔件及LDD區域之一程序。可使用其他程序及序列。例如,可利用更少或額外間隔件,可利用不同步驟序列(例如,在形成閘極間隔件86之前可不蝕刻閘極密封間隔件80以產生「L形」閘極密封間隔件),可形成及移除間隔件,及/或其類似者。此外,n型及p型器件可使用一不同結構及步驟形成。例如,用於n型器件之LDD區域可在形成閘極密封間隔件80之前形成,而用於p型器件之LDD區域可在形成閘極密封間隔件80之後形成。
在圖10A及圖10B中,磊晶源極/汲極區域82形成於鰭片52中。磊晶源極/汲極區域82形成於鰭片52中,使得各虛設閘極72A及72B放置於各自鄰近對磊晶源極/汲極區域82之間。在一些實施例中,磊晶源極/汲極區域82可延伸至鰭片52中且亦可穿透鰭片52。在一些實施例中,閘極間隔件86用於分離磊晶源極/汲極區域82與虛設閘極72A及72B達一適當橫向距離,使得磊晶源極/汲極區域82不使所得FinFET之隨後形成之閘極短路。磊晶源極/汲極區域82之一材料可經選擇以在各自通道區域58中施加應力,藉此提高效能。
n型區域50N中之磊晶源極/汲極區域82可藉由遮罩p型區域50P且蝕刻n型區域50N中之鰭片52之源極/汲極區域以在鰭片52中形成凹槽來形成。接著,n型區域50N中之磊晶源極/汲極區域82磊晶生長於凹槽中。磊晶源極/汲極區域82可包含任何可接受材料,諸如適合於n型FinFET。例如,若鰭片52係矽,則n型區域50N中之磊晶源極/汲極區域82可包含在通道區域58中施加一拉伸應變之材料,諸如矽、碳化矽、摻磷碳化矽、磷化矽或其類似者。n型區域50N中之磊晶源極/汲極區域82可具有自鰭片52之各自表面凸起之表面且可具有小平面。
p型區域50P中之磊晶源極/汲極區域82可藉由遮罩n型區域50N且蝕刻p型區域50P中之鰭片52之源極/汲極區域以在鰭片52中形成凹槽來形成。接著,p型區域50P中之磊晶源極/汲極區域82磊晶生長於凹槽中。磊晶源極/汲極區域82可包含任何可接受材料,諸如適合於p型FinFET。例如,若鰭片52係矽,則p型區域50P中之磊晶源極/汲極區域82可包括在通道區域58中施加一壓縮應變之材料,諸如矽鍺、摻硼矽鍺、鍺、鍺錫或其類似者。p型區域50P中之磊晶源極/汲極區域82可具有自鰭片52之各自表面凸起之表面且可具有小平面。
磊晶源極/汲極區域82及/或鰭片52可植入摻雜劑以形成源極/汲極區域(類似於先前討論之用於形成輕摻雜源極/汲極區域之程序),接著進行一退火。源極/汲極區域可具有約10
19cm
-3至約10
21cm
-3之間的一雜質濃度。用於源極/汲極區域之n型及/或p型雜質可為先前討論之雜質之任何者。在一些實施例中,磊晶源極/汲極區域82可在生長期間原位摻雜。
由於用於在n型區域50N及p型區域50P中形成磊晶源極/汲極區域82之磊晶程序,磊晶源極/汲極區域之上表面具有橫向向外擴展超過鰭片52之側壁之小平面。在一些實施例中,此等小平面引起一相同FinFET之相鄰源極/汲極區域82合併,如由圖10C所繪示。在其他實施例中,在完成磊晶程序之後,相鄰源極/汲極區域82保持分離,如由圖10D所繪示。在圖10C及圖10D所繪示之實施例中,閘極間隔件86形成為覆蓋在STI區域56上方延伸之鰭片52之側壁之一部分,藉此阻斷磊晶生長。在一些其他實施例中,用於形成閘極間隔件86之間隔件蝕刻可經調整以移除間隔件材料以允許磊晶生長區域延伸至STI區域56之表面。
在圖11A及圖11B中,一第一層間介電質(ILD) 88沈積於圖10A及圖10B中所繪示之結構上方。第一ILD 88可由一介電材料形成,且可藉由任何適合方法(諸如CVD、電漿增強CVD (PECVD)或FCVD)沈積。介電材料可包含磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、摻硼磷矽酸鹽玻璃(BPSG)、未摻雜矽酸鹽玻璃(USG)或其類似者。可使用藉由任何可接受程序形成之其他絕緣材料。在一些實施例中,一第一接觸蝕刻停止層(CESL) 87放置於第一ILD 88與磊晶源極/汲極區域82、遮罩74及閘極間隔件86之間。第一CESL 87可包括一介電材料,諸如氮化矽、氧化矽、氮氧化矽或其類似者,其具有比上覆第一ILD 88之材料更低之一蝕刻速率。
在圖12A及圖12B中,可執行一平坦化程序(諸如一CMP)以使第一ILD 88之頂面與虛設閘極72或遮罩74之頂面齊平。平坦化程序亦可移除虛設閘極72上之遮罩74及沿遮罩74之側壁之閘極密封間隔件80及閘極間隔件86之部分。在平坦化程序之後,虛設閘極72、閘極密封間隔件80、閘極間隔件86及第一ILD 88之頂面齊平。因此,虛設閘極72之頂面透過第一ILD 88暴露。在一些實施例中,遮罩74可保留,在該情況中,平坦化程序使第一ILD 88之頂面與遮罩74之頂面齊平。
在平坦化之後,虛設閘極72A可具有15 nm至19 nm之一範圍內之一高度H3且虛設閘極72B可具有18 nm至28 nm之一範圍內之一高度H4。在一些實施例中,虛設閘極72A及72B在平坦化之前具有一類似高度且虛設閘極72B之高度H4在平坦化之後大於虛設閘極72A之高度H3,其可歸因於(例如)對虛設閘極72A之更大凹陷效應,諸如來自更大圖案密度。
在圖13A及圖13B中,虛設閘極72A及72B及遮罩74 (若存在)在一(若干)蝕刻步驟中移除以形成凹槽90A及90B。亦可移除凹槽90A及90B中虛設介電層60之部分。在一些實施例中,僅移除虛設閘極72A及72B,而虛設介電層60保留且由凹槽90A及90B暴露。在一些實施例中,虛設介電層60自一晶粒之一第一區域(例如一核心邏輯區域)中之凹槽90A及90B移除且保留於晶粒之一第二區域(例如一輸入/輸出區域)中之凹槽90A及90B中。在一些實施例中,虛設閘極72A及72B藉由一各向異性乾式蝕刻程序移除。例如,蝕刻程序可包含使用(若干)反應氣體之一乾式蝕刻程序,其選擇性蝕刻虛設閘極72A及72B且幾乎不蝕刻第一ILD 88或閘極間隔件86。各凹槽90A及90B暴露及/或上覆於一各自鰭片52之一通道區域58。各通道區域58放置於鄰近對磊晶源極/汲極區域82之間。在移除期間,當蝕刻虛設閘極72A及72B時,虛設介電層60可用作一蝕刻停止層。虛設介電層60接著可視情況在移除虛設閘極72A及72B之後移除。
在圖14A及圖14B中,形成閘極介電層92A及92B (統稱為閘極介電層92)及閘極電極94A及94B (統稱為閘極電極94)用於替換閘極。圖14C繪示圖14B之區域89之一詳細圖。為形成閘極介電層92,一或多個層沈積於凹槽90A及90B中,諸如在鰭片52之頂面及側壁上及在閘極密封間隔件80/閘極間隔件86之側壁上。閘極介電層92亦可形成於第一ILD 88之頂面上。在一些實施例中,閘極介電層92包括一或多個介電層,諸如氧化矽、氮化矽、金屬氧化物、金屬矽酸鹽或其類似者之一或多個層。例如,在一些實施例中,閘極介電層92包含藉由熱或化學氧化形成之氧化矽之一界面層及一上覆高k介電材料,諸如鉿、鋁、鋯、鑭、錳、鋇、鈦、鉛及其等之組合之金屬氧化物或矽酸鹽。閘極介電層92可包含具有大於約7.0之一k值之一介電層。閘極介電層92之形成方法可包含分子束沈積(MBD)、ALD、PECVD及其類似者。在其中虛設介電層60之部分留在凹槽90A及90B中之實施例中,閘極介電層92包含虛設介電層60之一材料(例如SiO
2)。
閘極電極94分別沈積於閘極介電層92上方,且填充凹槽90之剩餘部分。閘極電極94可包含一含金屬材料,諸如氮化鈦、氧化鈦、氮化鉭、碳化鉭、鈷、釕、鋁、鎢、其等之組合或其等之多個層。例如,儘管圖14B中繪示一單層閘極電極94B,但閘極電極94B可包括任何數目個襯層91、任何數目個功函數調諧層93及一填充材料95,如由圖14C所繪示。在填充凹槽90A及90B之後,可執行一平坦化程序(諸如一CMP)以移除閘極介電層92之過量部分及閘極電極94之材料,該等過量部分位於第一ILD 88之頂面上方。閘極電極94及閘極介電層92之材料之剩餘部分因此形成所得FinFET之替換閘極。閘極電極94及閘極介電層92可統稱為一「閘極堆疊」。閘極及閘極堆疊可沿鰭片52之一通道區域58之側壁延伸。
在n型區域50N及p型區域50P中形成閘極介電層92可同時發生,使得各區域中之閘極介電層92由相同材料形成,且閘極電極94之形成可同時發生,使得各區域中之閘極電極94由相同材料形成。在一些實施例中,各區域中之閘極介電層92可藉由不同程序形成,使得閘極介電層92可為不同材料,及/或各區域中之閘極電極94可藉由不同程序形成,使得閘極電極94可為不同材料。當使用不同程序時,可使用各種遮罩步驟來遮罩及暴露適當區域。
在圖15A及圖15B中,閘極遮罩96A及96B (統稱為閘極遮罩96)形成於閘極堆疊(包含一閘極介電層92及一對應閘極電極94)上方,且閘極遮罩96可放置於閘極間隔件86之對置部分之間。在一些實施例中,形成閘極遮罩96包含使閘極堆疊凹進,使得一凹槽直接形成於閘極堆疊上方及閘極間隔件86之對置部分之間。包括介電材料(諸如氮化矽、氮氧化矽或其類似者)之一或多個層之一閘極遮罩96填充於凹槽中,接著進行一平坦化程序以移除在第一ILD 88上方延伸之介電材料之過量部分。
在第一閘極區域100A中,在形成閘極遮罩96A之後,閘極電極94A可具有8 nm至11 nm之一範圍內之一高度H5及8 nm至36 nm之一範圍內之一寬度W3。閘極遮罩96A可具有0.5 nm至2 nm之一範圍內之一高度H6。在第二閘極區域100B中,在形成閘極遮罩96B之後,閘極電極94B可具有72 nm至103 nm之一範圍內之一高度H7及72 nm至240 nm之一範圍內之一寬度W4。閘極遮罩96B可具有0.5 nm至2 nm之一範圍內之一高度H8。
亦如圖15A及圖15B中所繪示,一第二ILD 108沈積於第一ILD 88上方。在一些實施例中,第二ILD 108係藉由一可流動CVD方法形成之一可流動膜。在一些實施例中,第二ILD 108由一介電材料(諸如PSG、BSG、BPSG、USG或其類似者)形成,且可藉由任何適合方法(諸如CVD及PECVD)沈積。隨後形成之閘極觸點110 (圖16A及圖16B)穿透第二ILD 108及閘極遮罩96以接觸凹進閘極電極94之頂面。
在圖16A、圖16B及圖16C中,根據一些實施例,閘極觸點110A及110B (統稱為閘極觸點110)及源極/汲極觸點112穿過第二ILD 108及第一ILD 88形成,且圖16C繪示圖16B中所展示之區域118之一詳細圖且圖16D繪示圖16B中所展示之區域119之一詳細圖。用於源極/汲極觸點112之開口穿過第一ILD 88及第二ILD 108形成。開口可使用可接受光微影及蝕刻技術形成。一襯層(未展示)(諸如一擴散阻障層、一黏著層或其類似者)及一導電材料可形成於開口中。襯層可包含鈦、氮化鈦、鉭、氮化鉭或其類似者。導電材料可為銅、銅合金、銀、金、鎢、鈷、鋁、鎳或其類似者。可執行一平坦化程序(諸如一CMP)以自第二ILD 108之一表面移除過量材料。剩餘襯層及導電材料形成源極/汲極觸點112。可執行一退火程序以在磊晶源極/汲極區域82與源極/汲極觸點112之間的界面處形成矽化物。源極/汲極觸點112實體及電耦合至磊晶源極/汲極區域82。
用於閘極觸點110A及110B之開口分別係穿過第二ILD 108及閘極遮罩96A及96B而形成。開口可係使用可接受之光微影及蝕刻技術來形成。在形成用於閘極觸點110A及110B之開口之後,開口首先內襯有各自襯層109A及109B。襯層109A及109B係形成於開口之底面及側壁上方且可在閘極電極94A及94B、閘極遮罩96A及96B、源極/汲極觸點112及第二ILD 108之暴露表面上方延伸。襯層109A及109B包括TaN、Ta、TiN、Ti、Co或其類似者或其等之組合的一或多個層,且可藉由任何適合方法(例如CVD、PECVD、PVD、ALD、PEALD、ECP、無電式電鍍及其類似者)來沈積。在一些實施例中,襯層109A及109B包括Ti底層及TiN頂層。在一些實施例中,一膠層(未繪示)係在形成襯層109A及109B之前形成於開口中。膠層可為TiSi且可具有9 nm至10 nm之一厚度。
在形成襯層109A及109B之後,分別用於閘極觸點110A及110B之導電填充材料111A及111B經形成於開口中。導電填充材料111A及111B可為鈷、銅、銅合金、銀、金、鎢、鋁、鎳,或其類似者。可執行一平坦化程序(諸如一CMP)以自第二ILD 108之一表面移除過量材料。剩餘襯層109A及109B及導電填充材料111A及111B形成閘極觸點110A及110B,且分別實體及電耦合至閘極電極94A及94B。
閘極觸點110A可係形成至22 nm至26 nm之一範圍內之一高度H9及16 nm至37 nm之一範圍內之一寬度W5。閘極觸點110B可係形成至16 nm至20 nm之一範圍內之一高度H10。閘極觸點110B可具有比閘極觸點110A之高度H9更小之一高度H10,其可歸因於閘極觸點110A係形成於一更高閘極電極94B上。
閘極觸點110B可係形成至42 nm至38 nm之一範圍內之一寬度W6,其可用於隨後在閘極觸點110B之一頂面中形成具有一鉚釘形狀輪廓之一凹槽(參閱下文圖19B)。較小高度H10可導致在隨後形成具有一鉚釘形狀輪廓之凹槽中過度蝕刻閘極觸點110B。較寬寬度W6可導致凹槽具有一較寬寬度及一較淺深度,其可用於減少閘極觸點110B之過度蝕刻。在一些實施例中,寬度W6與寬度W5之一比率在1.2至2.6之一範圍內,且高度H10與高度H9之一比率在1.2至1.6之一範圍內。
具有小於42 nm之一寬度W6之閘極觸點110B可係不利的,因為其會導致在隨後形成具有一鉚釘形狀輪廓之凹槽時過度蝕刻閘極觸點110B。具有大於38 nm之一寬度W6之閘極觸點110B可係不利的,因為其會導致閘極觸點110B之一較短高度。
源極/汲極觸點112及閘極觸點110可在不同程序中形成,或可在相同程序中形成。儘管展示為形成於相同剖面中,但應瞭解,源極/汲極觸點112及閘極觸點110之各者可形成於不同剖面中,其可避免觸點短路。
在圖17A至圖17D中,形成一第二接觸蝕刻停止層(CESL) 114及一金屬間介電質(IMD) 116。圖17C繪示圖17B之區域118之一詳細圖,且圖17D繪示圖17B之區域119之一詳細圖。第二CESL 114形成於第二ILD 108、閘極觸點110及源極/汲極觸點112之頂面上。第二CESL 114可包括或為氮化矽、碳氮化矽、碳氧化矽、氮化碳、氧化鋁、類似者或其等之一組合,且可藉由CVD、電漿增強CVD (PECVD)、ALD或另一沈積技術沈積。
IMD 116形成於第二CESL 114上且可包括或為二氧化矽、低k介電材料、氮氧化矽、PSG、BSG、BPSG、USG、FSG、OSG、SiO
xC
y、旋塗玻璃、旋塗聚合物、矽碳材料、TEOS、其等之一化合物、其等之一複合物、類似者或其等之一組合。IMD 116可藉由旋塗、CVD、可流動CVD (FCVD)、PECVD、PVD或另一沈積技術沈積。
在圖17C及圖17D之後,圖18A及圖18B分別繪示穿過IMD 116及第二CESL 114至閘極觸點110A及110B形成開口124A及124B。IMD 116及第二CESL 114可經圖案化以形成開口124A及124B,例如使用光微影及一或多個蝕刻程序。蝕刻程序可為一乾式蝕刻且可包含一反應性離子蝕刻(RIE)、中性束蝕刻(NBE)、電感耦合電漿(ICP)蝕刻、電容耦合電漿(CCP)蝕刻、離子束蝕刻(IBE)、類似者或其等之一組合。蝕刻程序可為各向異性的。在一些實施例中,蝕刻程序可包含使用一第一氣體之一電漿,第一氣體包括四氟化碳(CF
4)、甲烷(CH
4)、六氟乙烷(C
2F
6)、八氟丙烷(C
3F
8)、氟仿(CHF
3)、二氟甲烷(CH
2F
2)、氟甲烷(CH
3F)、氟化碳(例如C
xF
y,其中x可在自1至5之一範圍內且y可在自4至8之一範圍內)、類似者或其等之一組合。電漿可進一步使用一第二氣體,其包括氮氣(N
2)、氫氣(H
2)、氧氣(O
2)、氬氣(Ar)、氙氣(Xe)、氦氣(He)、一氧化碳(CO)、二氧化碳(CO
2)、羰基硫(COS)、類似者或其等之一組合。可在蝕刻程序期間視情況供應一惰性氣體。在一些實施例中,開口124A形成至17 nm至23 nm之一範圍內之一寬度W7,且開口124B形成至37 nm至43 nm之一範圍內之一寬度W8。
圖18A及圖18B分別進一步繪示在閘極觸點110A及110B之頂面上形成殘留區域126A及126B。殘留區域126A及126B藉由閘極觸點110A及110B之頂面與來自形成開口124A及124B之蝕刻劑反應來形成。在一些實施例中,蝕刻劑可包括氟且殘留區域126A及126B之材料可包括一水溶性金屬氟化物,諸如(例如)氟化鈷。
圖19A及圖19B分別繪示在閘極觸點110A及110B之頂面中形成凹槽128A及128B。在形成開口124A及124B之後,可執行一濕式蝕刻(諸如一濕式清潔程序)以自閘極觸點110A及110B移除殘留區域126A及126B。執行濕式清潔程序以高效地自閘極觸點110A及110B之表面移除殘留區域126A及126B且移除IMD 116之側壁上之蝕刻副產物。在濕式清潔程序移除殘留區域126A及126B之後,凹槽128A及128B可延伸至閘極觸點110A及110B之各自頂面中。
在一實施例中,濕式清潔程序可包含將半導體基板50 (參閱上文圖17A及圖17B)浸入去離子(DI)水或另一適合化學品(其可在DI水中稀釋)中。在另一實施例中,濕式清潔程序使用氫氧化銨。在其中閘極觸點110由含Co材料製成之一實施例中,DI水可高效溶解可為一水溶性金屬氟化物(諸如(例如)氟化鈷)之殘留材料,因此移除殘留區域126A及126B之材料且在閘極觸點110A及110B上形成凹槽128A及128B。在其他實施例中,可利用與閘極觸點110之材料反應之一化學蝕刻劑。凹槽128A及128B可形成為具有形成於第二CESL 114之一底面下方之尖端129A及129B之一凹面(例如閘極觸點110上之一上凹面)。因為濕式清潔程序係一各向同性蝕刻程序,所以在溶液接觸閘極觸點110時各向同性及持續發生溶液與閘極觸點110之間的化學反應,直至達到一預定程序時段。凹槽128A及128B之尖端129A及129B分別自閘極觸點110A及110B橫向延伸且進一步延伸至第二CESL 114之底面下方。尖端129A及129B可輔助隨後形成於其中之材料以較佳黏著及擠壓錨固及接合通路120及捕穫用於隨後CMP程序中之漿料(亦可指稱CMP漿料)且減少到達閘極觸點110A及110B之CMP漿料量,藉此減少閘極觸點110A及110B之進一步蝕刻。
因為閘極觸點110B之寬度W6大於閘極觸點110A之寬度W5,所以各向同性蝕刻程序可形成凹槽128A至比凹槽128B之深度D2更大之一深度Dl,且其可形成凹槽128A至比凹槽128B之寬度W10更小之一寬度W9。深度D2小於深度D1可為有用的,因為閘極觸點110B之高度H8小於閘極觸點110A之高度H7且達成凹槽128B之一更小深度D2可減少凹槽128B過度蝕刻穿過閘極觸點110B至閘極電極94B中。此可用於減小接觸電阻及提高高頻寬記憶體之良率增益。
在一些實施例中,凹槽128A之深度Dl在6 nm至14 nm之一範圍內,其可用於達成一隨後形成之導電觸點(參閱下文圖20A)之一足夠寬鉚釘形底部部分以捕獲用於隨後CMP程序中之漿料。深度D1小於6 nm可為不利的,因為隨後形成之導電觸點之寬度不足以捕獲用於隨後CMP程序中之漿料以導致閘極觸點110A之非期望蝕刻。深度D1大於14 nm可為不利的,因為隨後形成之導電觸點可具有一非期望大寬度,其可導致與源極/汲極區域82或源極/汲極觸點112短接(參閱上文圖17B)。
在一些實施例中,凹槽128B之深度D2在6 nm至10 nm之一範圍內,其可用於達成一隨後形成之導電觸點(參閱下文圖20A)之一足夠寬鉚釘形底部部分以捕獲用於隨後CMP程序中之漿料,無閘極觸點110B之非期望過度蝕刻。深度D2小於6 nm可為不利的,因為隨後形成之導電觸點之寬度不足以捕獲用於隨後CMP程序中之漿料以導致閘極觸點110B之非期望蝕刻。深度D2大於10 nm可為不利的,因為閘極觸點110B可經過度蝕刻以導致更大接觸電阻及更差器件效能。在一些實施例中,凹槽128A之一寬度W9在0.4 nm至3.2 nm之一範圍內。
在分別在圖19A及圖19B之後的圖20A及圖20B中,導電構件130A及130B分別與各自閘極觸點110A及110B一起形成於凹槽128A及開口124A及凹槽128B及開口124B中。在一些實施例中,導電構件130A及130B由包括鎢之一導電填充材料形成,其用一ALD程序沈積。包括鎢及氟之一前驅體可用於選擇性ALD,諸如(例如) WF
6。在其他實施例中,導電構件130A及130B可藉由CVD、無電沈積(ELD)、PVD、電鍍或其他沈積技術形成。導電構件130A及130B可為或包括鎢、鈷、銅、釕、鋁、金、銀、其等之合金、類似者或其等之一組合。當導電構件130A及130B分別實質上填充凹槽128A及128B及開口124A及124B時,沈積程序終止。例如,自開口124A及124B過度生長之過量導電構件130A及130B可藉由使用一平坦化程序(諸如一CMP)來移除。平坦化程序可自IMD 116之一頂面上方移除過量導電構件130A及130B。因此,導電構件130A及130B及IMD 116之頂面可共面。導電構件130A及130B可為或可指稱觸點、插塞、金屬插塞、導線、導電墊、通路、通路至互連層(V
0)等等。導電構件130A及130B之底面上之一較大接觸面積可導致較低接觸電阻以改良器件功能。
為較容易填充開口124A及124B,可形成無阻障層或黏著層之導電構件130A及130B。因此,導電構件130A及130B與IMD 116之間的黏著性會降級,且導電構件130A及130B與IMD 116之間可存在微小裂縫。在CMP程序期間,用於CMP程序中之漿料(亦可指稱CMP漿料)可透過裂縫向下滲入且到達閘極觸點110A及110B。漿料對閘極觸點110A及110B之材料(例如鈷)可具有一高蝕刻選擇性(例如具有一高蝕刻速率),且因此可引起導電構件130A及130B之上表面凹進,藉此引起導電構件130A及130B與下伏閘極觸點110A及110B之間的不可靠電連接。藉由用各自尖端129A及129B (參閱上文圖19A及圖19B)填充凹槽128A及128B,導電構件130A及130B可包括延伸至各自閘極觸點110A及110B之頂面中之鉚釘形底部部分。導電構件130A及130B之擴大鉚釘形底部部分可捕獲向下滲入裂縫之CMP漿料且可減少到達閘極觸點110A及110B之CMP漿料量,藉此減少或防止閘極觸點110A及110B凹進。
在一些實施例中,跨導電構件130B之鉚釘形底部部分之對置外側壁量測之一寬度W10與跨導電構件130B之對置內側壁量測之寬度W8之一比率在1.2至1.5之一範圍內,其可有利於捕獲向下滲入裂縫之CMP漿料且藉此減少或防止閘極觸點110B凹進。寬度W10與寬度W8之比率小於1.2可不利的,因為無法捕獲向下滲入裂縫之CMP漿料且藉此增加閘極觸點110B凹進。寬度W10與寬度W8之比率大於1.5可為不利的,因為其會導致相鄰閘極觸點110B與源極/汲極觸點112之間短路。
圖20C至圖20F繪示根據一些實施例之穿過圖20B中所展示之剖面D-D'之結構之俯視圖。圖20C繪示其中閘極觸點110B及導電構件130B包括矩形輪廓之一實施例,其中導電構件130B包圍閘極觸點110B。圖20D繪示其中閘極觸點110B及導電構件130B包括卵形輪廓之一實施例,其中導電構件130B包圍閘極觸點110B。圖20E繪示其中閘極觸點110B及導電構件130B包括正方形輪廓之一實施例,其中導電構件130B包圍閘極觸點110B。圖20F繪示其中閘極觸點110B及導電構件130B包括圓形輪廓之一實施例,其中導電構件130B包圍閘極觸點110B。然而,一般技術者將認識到,上文所描述之閘極觸點110B及導電構件130B之俯視圖輪廓僅為實例且不意謂限制當前實施例。可使用任何適合輪廓,且所有此等輪廓完全意欲包含於本文中所討論之實施例之範疇內。
所揭露之FinFET實施例亦可應用於奈米結構器件,諸如奈米結構(例如奈米片、奈米線、環繞式閘極或其類似者)場效電晶體(NSFET)。在一NSFET實施例中,鰭片由藉由圖案化通道層及犧牲層之交替層之一堆疊形成之奈米結構替換。虛設閘極堆疊及源極/汲極區域依類似於上述實施例之一方式形成。在移除虛設閘極堆疊之後,可在通道區域中部分或完全移除犧牲層。替換閘極結構依類似於上述實施例之一方式形成,替換閘極結構可部分或完全填充藉由移除犧牲層留下之開口,且替換閘極結構可部分或完全包圍NSFET器件之區域通道中之通道層。ILD及至替換閘極結構及源極/汲極區域之觸點可依類似於上述實施例之一方式形成。可如美國公開專利申請案第2016/0365414號中所揭露般形成一奈米結構器件,該案之全文以引用的方式併入本文中。
實施例可提供優點。一閘極觸點形成於一閘極結構上且一接觸插塞隨後形成於閘極觸點上。閘極觸點具有比接觸插塞更大之一寬度,且接觸插塞之一鉚釘形底部部分延伸至閘極觸點中。接觸插塞之鉚釘形底部部分可減少來自一隨後執行之CMP之漿料對閘極觸點之非期望蝕刻。具有比接觸插塞更大之一寬度之閘極觸點可允許接觸插塞之鉚釘形底部部分更寬及更淺,其可減小非期望接觸電阻且提高高頻寬記憶體之良率增益。
根據一實施例,一種半導體器件包含:一第一閘極電極,其位於一基板上;一第二閘極電極,其位於該基板上;一第一導電觸點,其位於該第一閘極電極上,該第一導電觸點具有一第一高度及一第一寬度;一第二導電觸點,其位於該第二閘極電極上,該第二導電觸點具有一第二高度及一第二寬度,該第二高度小於該第一高度,該第二寬度大於該第一寬度;一蝕刻停止層(ESL),其位於該第一導電觸點及該第二導電觸點上;一第三導電觸點,其延伸穿過該ESL,該ESL懸在第三導電觸點之一部分上,該第三導電觸點之一凸底面實體接觸該第一導電觸點之一凹頂面,該第三導電觸點具有量測於該ESL之一底面處之一第三寬度;及一第四導電觸點,其延伸穿過該ESL,該ESL懸在該第四導電觸點之一部分上,該第四導電觸點之一凸底面實體接觸該第二導電觸點之一凹頂面,該第四導電觸點具有量測於該ESL之該底面處之一第四寬度,該第四寬度大於該第三寬度。在一實施例中,該第一導電觸點及該第二導電觸點包含鈷。在一實施例中,該第三導電觸點及該第四導電觸點包含鎢。在一實施例中,該半導體器件進一步包含該第二閘極電極與該ESL之間的一介電層。在一實施例中,該第二導電觸點之一部分中介於該介電層與該第四導電觸點之間。
根據另一實施例,一種半導體器件包含:一第一通道區域,其位於一半導體基板上;一第二通道區域,其位於該半導體基板上;一第一閘極結構,其位於該第一通道區域上,該第一閘極結構包含一第一閘極電極,該第一閘極電極具有一第一高度;一第二閘極結構,其位於該第二通道區域上,該第二閘極結構包含一第二閘極電極,該第二閘極電極具有一第二高度,該第二高度大於該第一高度;一第一介電層,其位於該第一閘極結構及該第二閘極結構上;一第一導電觸點,其位於該第一閘極電極上,該第一導電觸點延伸至該第一介電層之一頂面;一第二導電觸點,其位於該第二閘極電極上,該第二導電觸點延伸至該第一介電層之該頂面;一蝕刻停止層(ESL),其位於該第一介電層上,該ESL覆蓋該第一導電觸點之一部分及該第二導電觸點之一部分;一第三導電觸點,其包含:一第一底部部分,其位於該ESL之一下表面下方,在一俯視圖中,該第一底部部分由該第一導電觸點包圍,該第一底部部分在該ESL之該下表面下方延伸,該第一底部部分具有一第三寬度;及一第一頂部部分,其位於該ESL之該下表面上方;及一第四導電觸點,其包含:一第二底部部分,其位於該ESL之該下表面下方,在該俯視圖中,該第二底部部分由該第二導電觸點包圍,該第二底部部分在該ESL之該下表面下方延伸,該第二底部部分具有一第四寬度,該第四寬度大於該第三寬度;及一第二頂部部分,其位於該ESL之該下表面上方。在一實施例中,該第二導電觸點包含一襯層及一導電填充材料。在一實施例中,該襯層包含鈦。在一實施例中,該導電填充材料包含鈷。在一實施例中,該導電填充材料之一部分中介於該襯層與該第四導電觸點之間。
根據又一實施例,一種形成一半導體器件之方法包含:在一第一閘極電極及一第二閘極電極上沈積一第一介電層,該第一閘極電極及該第二閘極電極自一基板延伸;穿過該第一介電層形成一第一導電材料,該第一導電材料之一第一部分具有一第一高度及一第一寬度,該第一導電材料之一第二部分具有一第二高度及一第二寬度,該第一高度大於該第二高度,該第二寬度大於該第一寬度;在該第一導電材料及該第一介電層上方形成一蝕刻停止層(ESL);在該ESL上沈積一第二介電層;穿過該第二介電層及該ESL蝕刻一第一開口,該第一開口延伸至該第一導電材料之該第一部分中,在一俯視圖中,該第一開口由該第一導電材料之該第二部分包圍,該ESL懸在該第一開口之一部分上;穿過該第二介電層及該ESL蝕刻一第二開口,該第二開口延伸至該第一導電材料之該第二部分中,在該俯視圖中,該第二開口由該第一導電材料包圍,該ESL懸在該第一開口之一部分上;及用一第二導電材料填充該第一開口及該第二開口。在一實施例中,該第一導電材料包含鈷。在一實施例中,該第二導電材料包含鎢。在一實施例中,蝕刻該第一開口及該第二開口包含一乾式蝕刻及一濕式蝕刻。在一實施例中,該乾式蝕刻包含氟。在一實施例中,該氟與該第一導電材料之一頂面反應以形成包含一水溶性氟化物之一殘留區域。在一實施例中,該濕式蝕刻係包含去離子(DI)水之一濕式清潔程序。在一實施例中,該DI水移除該殘留區域。在一實施例中,該第一開口延伸至該ESL之一底面下方之該第一導電材料之該第一部分中達6 nm至14 nm之一範圍內之一第一深度。在一實施例中,該第二開口延伸至該ESL之一底面下方之該第一導電材料之該第二部分中達6 nm至10 nm之一範圍內之一第二深度。
上文已概述若干實施例之特徵,使得熟習技術者可較佳理解本揭露之態樣。熟習技術者應瞭解,其可易於將本揭露用作用於設計或修改用於實施相同目的及/或達成本文中所引入之實施例之相同優點之其他操作及結構之一基礎。熟習技術者亦應意識到,此等等效建構不應背離本揭露之精神及範疇,且其可在不背離本揭露之精神及範疇之情況下對本文作出各種改變、替換及更改。
20:分隔線
22:分隔線
50:基板
50N:n型區域
50P:p型區域
52:鰭片
54:絕緣材料
56:淺溝槽隔離(STI)區域
58:通道區域
60:虛設介電層
62A:虛設閘極層
62B:虛設閘極層
64:遮罩層
72:虛設閘極
72A:虛設閘極
72B:虛設閘極
74:遮罩
80:閘極密封間隔件
82:源極/汲極區域
86:閘極間隔件
87:第一接觸蝕刻停止層(CESL)
88:第一層間介電質(ILD)
89:區域
90:凹槽
90A:凹槽
90B:凹槽
91:襯層
92:閘極介電層
92A:閘極介電層
92B:閘極介電層
93:功函數調諧層
94:閘極電極
94A:閘極電極
94B:閘極電極
95:填充材料
96:閘極遮罩
96A:閘極遮罩
96B:閘極遮罩
100A:第一閘極區域
100B:第二閘極區域
108:第二ILD
109A:襯層
109B:襯層
110:閘極觸點
110A:閘極觸點
110B:閘極觸點
111A:導電填充材料
111B:導電填充材料
112:源極/汲極觸點
114:第二CESL
116:金屬間介電質(IMD)
118:區域
119:區域
120:通路
124A:開口
124B:開口
126A:殘留區域
126B:殘留區域
128A:凹槽
128B:凹槽
129A:尖端
129B:尖端
130A:導電構件
130B:導電構件
D1:深度
D2:深度
H1:高度
H2:高度
H3:高度
H4:高度
H5:高度
H6:高度
H7:高度
H8:高度
H9:高度
H10:高度
W1:寬度
W2:寬度
W3:寬度
W4:寬度
W5:寬度
W6:寬度
W7:寬度
W8:寬度
W9:寬度
W10:寬度
自結合附圖閱讀之以下詳細描述最佳理解本揭露之態樣。應注意,根據標準工業實踐,各種構件未按比例繪製。事實上,為使討論清楚,可任意增大或減小各種構件之尺寸。
圖1繪示根據一些實施例之一FinFET之一實例之三維圖。
圖2、圖3、圖4、圖5、圖6、圖7A、圖7B、圖8A、圖8B、圖9A、圖9B、圖10A、圖10B、圖10C、圖10D、圖11A、圖11B、圖12A、圖12B、圖13A、圖13B、圖14A、圖14B、圖14C、圖15A、圖15B、圖16A、圖16B、圖16C、圖16D、圖17A、圖17B、圖17C、圖17D、圖18A、圖18B、圖19A、圖19B、圖20A及圖20B係根據一些實施例之製造FinFET之中間階段之剖面圖。
圖20C、圖20D、圖20E及圖20F係根據一些實施例之製造FinFET之中間階段之俯視圖。
80:閘極密封間隔件
86:閘極間隔件
92A:閘極介電層
94B:閘極電極
96A:閘極遮罩
108:第二層間介電質(ILD)
109A:襯層
110A:閘極觸點
111A:導電填充材料
114:第二接觸蝕刻停止層(CESL)
116:金屬間介電質(IMD)
118:區域
130A:導電構件
Claims (10)
- 一種半導體器件,其包括: 一第一閘極電極,其位於一基板上; 一第二閘極電極,其位於該基板上; 一第一導電觸點,其位於該第一閘極電極上,該第一導電觸點具有一第一高度及一第一寬度; 一第二導電觸點,其位於該第二閘極電極上,該第二導電觸點具有一第二高度及一第二寬度,該第二高度小於該第一高度,該第二寬度大於該第一寬度; 一蝕刻停止層(ESL),其位於該第一導電觸點及該第二導電觸點上; 一第三導電觸點,其延伸穿過該ESL,該ESL懸在第三導電觸點之一部分上,該第三導電觸點之一凸底面實體地接觸該第一導電觸點之一凹頂面,該第三導電觸點具有於該ESL之一底面處量測之一第三寬度;及 一第四導電觸點,其延伸穿過該ESL,該ESL懸在該第四導電觸點之一部分上,該第四導電觸點之一凸底面實體地接觸該第二導電觸點之一凹頂面,該第四導電觸點具有於該ESL之該底面處量測之一第四寬度,該第四寬度大於該第三寬度。
- 如請求項1之半導體器件,進一步包括該第二閘極電極與該ESL之間之一介電層。
- 如請求項2之半導體器件,其中該第二導電觸點之一部分係中介於該介電層與該第四導電觸點之間。
- 一種半導體器件,其包括: 一第一通道區域,其位於一半導體基板上; 一第二通道區域,其位於該半導體基板上; 一第一閘極結構,其位於該第一通道區域上,該第一閘極結構包括一第一閘極電極,該第一閘極電極具有一第一高度; 一第二閘極結構,其位於該第二通道區域上,該第二閘極結構包括一第二閘極電極,該第二閘極電極具有一第二高度,該第二高度大於該第一高度; 一第一介電層,其位於該第一閘極結構及該第二閘極結構上; 一第一導電觸點,其位於該第一閘極電極上,該第一導電觸點延伸至該第一介電層之一頂面; 一第二導電觸點,其位於該第二閘極電極上,該第二導電觸點延伸至該第一介電層之該頂面; 一蝕刻停止層(ESL),其位於該第一介電層上,該ESL覆蓋該第一導電觸點之一部分及該第二導電觸點之一部分; 一第三導電觸點,其包括: 一第一底部部分,其位於該ESL之一下表面下方,在一俯視圖中,該第一底部部分係由該第一導電觸點包圍,該第一底部部分在該ESL之該下表面下方延伸,該第一底部部分具有一第三寬度;及 一第一頂部部分,其位於該ESL之該下表面上方;及 一第四導電觸點,其包括: 一第二底部部分,其位於該ESL之該下表面下方,在該俯視圖中,該第二底部部分係由該第二導電觸點包圍,該第二底部部分在該ESL之該下表面下方延伸,該第二底部部分具有一第四寬度,該第四寬度大於該第三寬度;及 一第二頂部部分,其位於該ESL之該下表面上方。
- 如請求項4之半導體器件,其中該第二導電觸點包括一襯層及一導電填充材料。
- 如請求項5之半導體器件,其中該導電填充材料之一部分係中介於該襯層與該第四導電觸點之間。
- 一種形成一半導體器件之方法,該方法包括: 在一第一閘極電極及一第二閘極電極上沈積一第一介電層,該第一閘極電極及該第二閘極電極自一基板延伸; 穿過該第一介電層形成一第一導電材料,該第一導電材料之一第一部分具有一第一高度及一第一寬度,該第一導電材料之一第二部分具有一第二高度及一第二寬度,該第一高度大於該第二高度,該第二寬度大於該第一寬度; 在該第一導電材料及該第一介電層上方形成一蝕刻停止層(ESL); 在該ESL上沈積一第二介電層; 穿過該第二介電層及該ESL蝕刻一第一開口,該第一開口延伸至該第一導電材料之該第一部分中,在一俯視圖中,該第一開口係由該第一導電材料之該第二部分包圍,該ESL懸在該第一開口之一部分上; 穿過該第二介電層及該ESL蝕刻一第二開口,該第二開口延伸至該第一導電材料之該第二部分中,在該俯視圖中,該第二開口係由該第一導電材料包圍,該ESL懸在該第一開口之一部分上;及 用一第二導電材料填充該第一開口及該第二開口。
- 如請求項7之方法,其中蝕刻該第一開口及該第二開口包括一乾式蝕刻及一濕式蝕刻。
- 如請求項7之方法,其中該第一開口延伸至該ESL之一底面下方之該第一導電材料之該第一部分中達6 nm至14 nm之一範圍內之一第一深度。
- 如請求項7之方法,其中該第二開口延伸至該ESL之一底面下方之該第一導電材料之該第二部分中達6 nm至10 nm之一範圍內之一第二深度。
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US9520482B1 (en) | 2015-11-13 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting metal gate |
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