CN114326980A - Multi-backboard cascading server - Google Patents
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Abstract
The invention discloses a multi-backboard cascading server which comprises a mainboard and a plurality of backplanes, wherein the mainboard comprises a mainboard programmable device and a BMC (baseboard management controller), the backplanes comprise backboard programmable devices, and the BMC is connected with each backboard programmable device through a communication bus. The mainboard programmable device is configured to send a signal to the first backplane programmable device; the first backplane programmable device is configured to convert the received signal into a signal of other frequency and send the signal to the next backplane programmable device; the other backboard programmable devices are also configured to convert the received signals into signals with other frequencies and send the signals to the next backboard programmable device, and the frequencies of the signals converted by the backboard programmable devices are different; each backplane programmable device is configured to configure a corresponding bus address according to the received signal frequency. The invention realizes the bus address configuration of the backboard programmable device without additionally increasing hardware configuration, so that the BMC can access the corresponding backboard programmable device through the communication bus.
Description
Technical Field
The invention relates to the technical field of servers, in particular to a server with multiple cascaded backplanes.
Background
With the development of informatization and intellectualization, the server is used as a core device for processing and storing data, the requirements of people on the performance and the configuration of the server are higher and higher, and in some application scenes, the server is required to be configured with a plurality of back plates.
At present, a server configured with multiple backplanes mainly includes two forms: the method comprises the steps that firstly, a plurality of connectors are arranged on a mainboard, each connector is correspondingly connected with a backboard, and a Baseboard Management Controller (BMC) of the mainboard can distinguish the position of each backboard in a system according to the connectors, so that the corresponding backboard can be accessed, but the arrangement of the plurality of connectors occupies more physical space, and meanwhile, the cost is increased; secondly, a plurality of backplanes are cascaded, bus equipment with configurable addresses is adopted on the backplanes, the bus equipment is configured into different addresses through different peripheral circuits, a Baseboard Management Controller (BMC) of the mainboard can access the corresponding backplanes according to the addresses, but the different peripheral circuits are used for distinguishing, each backplane needs a separate Bill of materials (BOM), the subsequent management and maintenance cost is high, and confusion is easily caused particularly under the condition that the number of the cascaded backplanes is large.
Disclosure of Invention
The invention aims to provide a server capable of configuring a communication address of a backboard without additionally configuring hardware.
In order to achieve the above object, the present invention provides a multi-backplane cascaded server, including a motherboard and a plurality of backplanes, where the motherboard includes a motherboard programmable device and a BMC, the backplanes include backplane programmable devices, each backplane programmable device is connected in sequence, and the backplane programmable device located at the head is connected to the motherboard programmable device, and the BMC is connected to each backplane programmable device through a communication bus. The mainboard programmable device is configured to send a signal to a backplane programmable device located at a head; the backboard programmable device at the head is configured to receive the signal sent by the mainboard programmable device, convert the signal into a signal with other frequency and send the signal to the next backboard programmable device; the other backboard programmable devices are configured to receive signals sent by the previous backboard programmable device, if the latter backboard programmable device exists, the received signals are converted into signals with other frequencies and sent to the latter backboard programmable device, and the frequencies of the signals converted by the backboard programmable devices are different; each backplane programmable device is configured to configure a respective bus address according to a received signal frequency.
Compared with the prior art, the invention sends signals to the backplate programmable device at the head by configuring the mainboard programmable device, the backplate programmable device at the head receives the signals sent by the mainboard programmable device and converts the signals into signals with other frequencies to send to the backplate programmable device at the next frequency, the other backplate programmable devices also convert the received signals into signals with other frequencies to send to the backplate programmable device at the next frequency, the frequencies of the signals converted by the backplate programmable devices are different, and the backplate programmable devices are configured to configure corresponding bus addresses according to the received signal frequencies. The invention realizes the bus address configuration of each backboard programmable device under the condition of not additionally increasing hardware configuration, thereby leading the BMC of the mainboard to be capable of distinguishing each backboard programmable device and carrying out information interaction with the corresponding backboard programmable device through the communication bus. Moreover, each backboard programmable device configures the bus address through frequency, and the BMC of the mainboard outputs a signal to realize the bus address configuration of each backboard programmable device, so that the realization is easy.
In some embodiments, each backplane programmable device stores a mapping of the received signal frequency to the bus address.
In some embodiments, each backplane programmable device is configured to obtain its rank according to the frequency of the received signal, and configure the bus address according to the rank.
In some embodiments, each backplane programmable device stores a mapping of the received signal frequency to the rank bits and a mapping of the rank bits to the bus address.
In some embodiments, each backplane programmable device converts the received signal into a signal with N times frequency, where N is a number greater than 0, and sends the signal to the subsequent backplane programmable device.
In some embodiments, N is 2.
In some embodiments, the motherboard programmable device and the backplane programmable device are both CPLDs.
In some embodiments, the communication bus is an I2C bus.
In some embodiments, each backplane further comprises an FRU, the FRU is connected to the backplane programmable device on the backplane on which it is located, and the FRU is connected to the communication bus, and each backplane programmable device configures a bus address of the FRU on the backplane on which it is located according to the received signal frequency.
In some embodiments, the input terminal and the output terminal of the backplane programmable device are respectively connected to a front-end connector and a back-end connector, the output terminal of the motherboard programmable device is connected to a motherboard connector, the backplane programmable device located at the head is connected to the motherboard connector through the front-end connector of the backplane where the backplane programmable device is located, and the remaining backplane programmable devices are connected to the back-end connector of the preceding backplane through the front-end connectors of the backplanes where the backplane programmable device is located.
Drawings
Fig. 1 is a schematic diagram of a server with multiple backplanes cascaded according to an embodiment of the present invention.
Detailed Description
In order to explain the contents, structural features, objects and effects of the present invention in detail, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The technical solution of the embodiment of the present invention is described in detail below with reference to fig. 1:
as shown in fig. 1, the multi-backplane cascaded server provided in this embodiment includes a motherboard 10 and three backplanes 20, 30, and 40, the motherboard 10 includes a motherboard programmable device 11, a BMC (baseboard management Controller) 12, and a motherboard connector 13 connected to the motherboard programmable device 11, the backplane 20 includes a backplane programmable device 21, a front connector 22 and a back connector 23 connected to the backplane programmable device 21, the backplane 30 includes a backplane programmable device 31, a front connector 32 and a back connector 33 connected to the backplane programmable device 31, the backplane 40 includes a backplane programmable device 41, a front connector 42 and a back connector 43 connected to the backplane programmable device 41, the front connector 22 of the backplane 20 at the head is connected to the motherboard 13, the front connector 32 of the backplane 30 is connected to the back connector 23 of the backplane 20, the front connector 42 of the backplane 40 is connected to the back connector 33 of the backplane 30, by the arrangement of the motherboard connector 13, the front connectors 22, 32, 42 and the back connectors 23, 33, 43, the motherboard programmable device 11, the backplane programmable device 21, the backplane programmable device 31 and the backplane programmable device 41 are sequentially cascaded together, and the backplane programmable devices 21, 31, 41 are connected to the communication bus 50 to be in communication connection with the BMC12 through the communication bus 50.
Wherein the motherboard programmable device 11 is configured to send a signal of a first frequency to the backplane programmable device 21 of the backplane 20; the backplane programmable device 21 is configured to receive the signal of the first frequency sent by the motherboard programmable device 11, convert the signal into a signal of the second frequency, and send the signal to the backplane programmable device 31 of the backplane 30; the backplane programmable device 31 is configured to receive a signal of a second frequency sent by the backplane programmable device 21, convert the signal into a signal of a third frequency, and send the signal to the backplane programmable device 41 of the backplane 40, where the first frequency, the second frequency, and the third frequency are different from each other; each backplane programmable device 21, 31, 41 is configured to configure a respective bus address according to the received signal frequency.
In this embodiment, the second frequency is one half of the first frequency, the third frequency is one half of the second frequency, the half-divide procedure is simple to set, and the backplane programmable devices 21, 31, 41 are easier to implement. For example, the motherboard programmable device 11 sends 256K signals to the backplane programmable device 21, the backplane programmable device 21 converts the 256K signals into 128K signals, and then sends the 128K signals to the backplane programmable device 31, the backplane programmable device 31 converts the 128K signals into 64K signals, and then sends the 64K signals to the backplane programmable device 41.
Of course, the first frequency and the second frequency, and the second frequency and the third frequency are not limited to a multiple relationship, and more limited to a double relationship (for example, the second frequency is one third of the first frequency, and the third frequency is one third of the second frequency). Motherboard programmable device 11 is not limited to sending 256K signals to backplane programmable device 21, and may send, for example, 200K signals to backplane programmable device 21.
In this embodiment, each backplane programmable device 21, 31, 41 is configured to obtain the rank of the received signal according to its frequency, and then configure the bus address according to the rank. The "level bit" refers to that the backplane programmable device (backplane) is in the second level of the cascade, for example, the backplane programmable device 21 connected to the motherboard programmable device 11 is assigned to the first level, the backplane programmable device 31 connected to the backplane programmable device 21 of the first level is assigned to the second level, the backplane programmable device 41 connected to the backplane programmable device 31 of the second level is assigned to the third level, and so on.
Specifically, each backplane programmable device 21, 31, 41 stores a mapping relationship between the received signal frequency and the level, and a mapping relationship between the level and the bus address. For example, the frequency of the received signal is 256K, corresponding to the first level, and the bus address (physical address) corresponding to the first-level backplane programmable device is OXE5, that is, the bus address of the backplane programmable device 21 is configured as OXE 5; the frequency of the received signal is 128K, which corresponds to the second level, and the bus address corresponding to the second-level backplane programmable device is OXE6, that is, the bus address of the backplane programmable device 31 is configured as OXE 6; the received signal frequency is 64K, corresponding to the third level, and the bus address corresponding to the backplane programmable device of the third level is OXE7, that is, the bus address of the backplane programmable device 41 is configured as OXE 7.
By setting this intermediate amount of level bits, the backplane can be configured later in time in relation to the level bits. Of course, the mapping relationship between the received signal frequency and the bus address may be stored in each backplane programmable device 21, 31, 41, and the bus address configuration of each backplane programmable device 21, 31, 41 may be performed directly according to the mapping relationship between the received signal frequency and the bus address, for example, the received signal frequency is 200K, the bus address configuration is OXE5, the received signal frequency is 100K, the bus address configuration is OXE6, the received signal frequency is 50K, and the bus address configuration is OXE 7.
In the embodiment shown in fig. 1, each backplane 20, 30, 40 further includes an FRU (Field replaceable Unit) 24, 34, 44, FRU24 is connected to address configuration pins of backplane programmable device 21, FRU34 is connected to address configuration pins of backplane programmable device 31, FRU44 is connected to address configuration pins of backplane programmable device 41, and each FRU24, 34, 44 is connected to communication bus 50, and each backplane programmable device 21, 31, 41 also configures bus addresses of FRUs 24, 34, 44 according to the received signal frequency. For example, backplane programmable device 21 configures the bus address of FRU24 to be OXA8, backplane programmable device 31 configures the bus address of FRU34 to be OXAA, and backplane programmable device 41 configures the bus address of FRU44 to be OXAC.
In addition, each backplane 20, 30, 40 may further include a functional module such as a temperature detection device, and the temperature detection device needs to send information to the BMC12 of the motherboard, and also may perform bus address configuration according to the received signal frequency through the backplane programmable device 21, 31, 41, which is not described herein again. That is, each backplane programmable device 21, 31, 41 not only configures its own bus address according to the received signal frequency, but also configures the bus address according to the received signal frequency by connecting to the address configuration pins and connecting to other function modules of the communication bus 50, so that the BMC12 of the motherboard can access the information of each function module on the backplane 20, 30, 40.
In the embodiment shown in fig. 1, the motherboard Programmable Device 11 and the backplane Programmable devices 21, 31, 41 are both CPLDs (Complex Programmable Logic devices). Of course, instead of the CPLD, for example, a single chip microcomputer of STM32 series, an FPGA (Field Programmable Gate Array), a PLD (Programmable Logic Device), or the like may be used as long as the present invention is implemented by having functions of transmitting and receiving signals, detecting frequencies of received signals, converting received signals into other frequencies, and the like.
In the embodiment shown in fig. 1, the communication bus 50 is an I2C (Inter-Integrated Circuit) bus, but the communication bus 50 may also be an spi (serial Peripheral interface) bus, for example. The main board connector 13, each front end connector 22, 32, 42, and each rear end connector 23, 33, 43 are 20-pin MISC connectors, but should not be limited thereto.
It is understood that three backplanes 20, 30, and 40 are shown in the embodiment shown in fig. 1 as an example, and in other embodiments, two backplanes may be cascaded, four backplanes are cascaded, seven backplanes are cascaded, and the specific implementation is not limited to the specific number of backplanes. Furthermore, those skilled in the art will appreciate that the server may include other components besides the components listed in the above embodiments, for example, the motherboard 10 may further include a CPU.
In summary, the present invention configures the motherboard programmable device to send a signal to the backplane programmable device located at the head, configures the backplane programmable device located at the head to receive the signal sent by the motherboard programmable device and convert the signal into a signal with other frequency, and send the signal to the subsequent backplane programmable device, and the other backplane programmable devices also convert the received signal into a signal with other frequency, and send the signal to the subsequent backplane programmable device, and the signal frequencies converted by the backplane programmable devices are different, and configures the backplane programmable devices to configure corresponding bus addresses according to the received signal frequencies. Under the condition that hardware configuration is not additionally added, the invention realizes the bus address configuration of the functional modules such as the backboard programmable device, the FRU and the like of each backboard, thereby leading the BMC of the mainboard to distinguish each backboard and carry out information interaction with the corresponding backboard programmable device, the FRU and the like through the communication bus. Moreover, each backboard programmable device configures the bus address through frequency, the BMC of the mainboard outputs a signal to realize the bus address configuration of each backboard programmable device, FRU and other functional modules, the realization is easy, and the invention is still suitable even if the backboard is expanded to a plurality of backboards.
The above disclosure is only a preferred embodiment of the present invention, and should not be taken as limiting the scope of the invention, so that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.
Claims (10)
1. The server is characterized by comprising a mainboard and a plurality of backplanes, wherein the mainboard comprises a mainboard programmable device and a BMC, the backplanes comprise backplane programmable devices, the backplane programmable devices are sequentially connected, the backplane programmable device positioned at the head is connected with the mainboard programmable device, and the BMC is connected with the backplane programmable devices through a communication bus;
the mainboard programmable device is configured to send a signal to a backplane programmable device located at a head;
the backboard programmable device at the head is configured to receive the signal sent by the mainboard programmable device, convert the signal into a signal with other frequency and send the signal to the next backboard programmable device;
the other backboard programmable devices are configured to receive signals sent by the previous backboard programmable device, if the latter backboard programmable device exists, the received signals are converted into signals with other frequencies and sent to the latter backboard programmable device, and the frequencies of the signals converted by the backboard programmable devices are different;
each backplane programmable device is configured to configure a respective bus address according to a received signal frequency.
2. The multi-backplane cascaded server of claim 1, wherein each of the backplane programmable devices stores a mapping of the received signal frequency to the bus address.
3. The multi-backplane cascaded server of claim 1, wherein each said backplane programmable device is configured to obtain its level according to a received signal frequency and configure said bus address according to said level.
4. The multi-backplane cascaded server of claim 3, wherein each said backplane programmable device stores a mapping of said received signal frequency to said level bits and a mapping of said level bits to said bus address.
5. The server of any one of claims 1 to 4, wherein each backplane programmable device converts the received signal into a signal with N times frequency, where N is a number greater than 0, and sends the signal to a subsequent backplane programmable device.
6. The multi-backplane cascaded server of claim 5, wherein N is 2.
7. The server of any one of claims 1 to 4, wherein the motherboard programmable device and the backplane programmable device are both CPLDs.
8. The server of any one of claims 1 to 4, wherein the communication bus is an I2C bus.
9. The server of any of claims 1 to 4, wherein each backplane further comprises an FRU, the FRU is connected to the backplane programmable device on the backplane on which it is located, and the FRU is connected to the communication bus, and each backplane programmable device configures a bus address of the FRU on the backplane on which it is located based on the frequency of the received signal.
10. The server of any one of claims 1 to 4, wherein the input and output terminals of the backplane programmable devices are respectively connected to a front-end connector and a back-end connector, the output terminal of the motherboard programmable device is connected to a motherboard connector, the first backplane programmable device is connected to the motherboard connector through the front-end connector of the backplane in which the backplane is located, and the remaining backplane programmable devices are connected to the back-end connector of the preceding backplane through the front-end connectors of the backplanes in which the backplane is located.
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2021
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Application publication date: 20220412 |