CN113448402A

CN113448402A - Server supporting multi-backboard cascade

Info

Publication number: CN113448402A
Application number: CN202110599101.5A
Authority: CN
Inventors: 冯鹏斌
Original assignee: Shandong Yingxin Computer Technology Co Ltd
Current assignee: Shandong Yingxin Computer Technology Co Ltd
Priority date: 2021-05-31
Filing date: 2021-05-31
Publication date: 2021-09-28
Anticipated expiration: 2041-05-31
Also published as: CN113448402B

Abstract

The invention discloses a server supporting multi-backboard cascade. The server comprises a mainboard, a BMC, a mainboard low-speed connector, an Expander chip and a plurality of mainboard high-speed connectors, wherein the BMC is connected to the mainboard low-speed connector through an I2C bus, and the BMC is connected to the Expander chip through an I2C bus; each backboard is provided with an I2C repeater, a backboard low-speed connector and a backboard high-speed connector, the backboard low-speed connectors and the backboard high-speed connectors are respectively connected with the I2C repeater, the backboard low-speed connectors are sequentially connected in series and then connected with the mainboard low-speed connector, each backboard corresponds to one mainboard high-speed connector, and each backboard high-speed connector is connected with the corresponding mainboard high-speed connector and then connected to an Expander chip; the BMC is configured to detect the presence backplanes and enable any I2C repeater on the presence backplane, and to select the backplane on which the enabled I2C repeater resides as the gated backplane. The server solves the problem of address repetition of the cascade backplane I2C, improves the polling efficiency of BMC access backplane equipment, and reduces the load of an I2C bus.

Description

Server supporting multi-backboard cascade

Technical Field

The invention relates to the technical field of servers, in particular to a server supporting multi-backboard cascading.

Background

With the rapid development of cloud computing applications, informatization and intellectualization gradually cover various fields of society. People's daily life is more and more communicated through the network, and the network data volume is also increasing at a burst formula, and the server is as the core equipment of processing and storage data, and is also higher and higher to the requirement of performance and configuration. In order to meet the complex and various application scenes of different users in various fields, the configuration of the server needs to be more flexible and changeable. For example, when the server is applied to the field of mass storage, more PCIe resources need to be allocated to the hard disk through the backplane, and when the server is applied to the field of computing, only a storage requirement with a smaller capacity is required, and a smaller number of hard disks can be satisfied, and at this time, part of PCIe resources can be allocated to other devices, such as a network card and a GPU. Therefore, in order to achieve compatible design of servers in different applications, a preferred solution is to design the backplane carrying the hard disk to have a small capacity, and if necessary, the storage capacity can be expanded by cascading the backplanes.

The common schemes for connecting the existing server and the main board mainly include the following two schemes: the first method comprises the following steps: as shown in fig. 1, in this scheme, I2C devices with configurable addresses are on the backplane, and the I2C devices are configured to different addresses through different peripheral circuits. The baseboard management controller (i.e. BMC) can directly access different addresses to interact with different devices to obtain required information. And the second method comprises the following steps: as shown in FIG. 2, in this scheme, the backplane design is kept consistent, multiple side connectors are placed at the end of the motherboard to connect different backplanes, each channel of the I2C Switch is connected to one connector separately, and the BMC switches different channels to access different backplanes through the I2 CSwitch.

The defects of the two modes are respectively as follows: in the first scheme, different peripheral circuits are used for distinguishing the backplanes, each backplane needs a separate Bill of materials (BOM for short), and the subsequent management and maintenance cost is high. Particularly, under the condition that the number of the cascaded backplanes is large, confusion is easy to cause, and the problem is more serious; in the second scheme, the I2C Switch chip is placed on the main board, so that the problem of I2C address repetition on the same backplane is solved, but a plurality of side band connectors are needed to connect the backplane at the moment, and the number of cables is large. In the application of large-capacity storage, the requirement for heat dissipation in the case is higher, and the space for cable routing is more tense. Meanwhile, in the scheme, the CPU VPP signal is divided into multiple paths of signals on the mainboard and is connected to the backboard through a cable, the topological requirement cannot be met, and the signal quality is poor. If the problem of signal quality is solved by adding a Switch chip according to the processing mode of the I2C signal, each CPU needs one Switch chip, and the cost is increased. In addition, when the BMC accesses the hard disk in this case, the BMC needs to pass through a secondary Switch chip, which results in low polling efficiency.

Disclosure of Invention

In view of the above, there is a need for providing a server supporting multi-backplane concatenation, the server comprising:

the system comprises a mainboard, wherein a mainboard manager, a mainboard low-speed connector, an Expander chip and a plurality of mainboard high-speed connectors are arranged on the mainboard, the mainboard management controller is connected to the mainboard low-speed connector through an I2C bus, and the mainboard management controller is connected to the Expander chip through an I2C bus;

each backboard is provided with an I2C repeater, a backboard low-speed connector connected with the I2C repeater and a backboard high-speed connector connected with the I2C repeater, the plurality of backboard low-speed connectors are sequentially connected in series and then connected with the mainboard low-speed connector, each backboard corresponds to one mainboard high-speed connector, and each backboard high-speed connector is connected with the corresponding mainboard high-speed connector and then connected to an Expander chip;

the baseboard management controller is configured to detect an in-place backplane through a plurality of mainboard high-speed connectors and corresponding backplane high-speed connectors, enable any I2C repeater of the in-place backplane through the Expander chip, and use the backplane where the enabled I2C repeater is located as a gated backplane.

In some embodiments, each motherboard high-speed connector and the Expander chip are connected through two signal lines, wherein one signal line is used for transmitting the in-place signal of the backplane, and the other signal line is used for transmitting the enabling signal of the I2C repeater of the backplane.

In some embodiments, the server further comprises: and each central processing unit is connected with the low-speed connector of the mainboard through a VPP signal.

In some embodiments, each central processor is connected to each motherboard high-speed connector by a PCIe bus.

In some embodiments, each backplane further comprises a CPLD, an I2C Switch chip, and a plurality of hard disks;

the CPLD and the I2C Switch chip are connected with an I2C repeater on the same backboard through an I2C bus;

the CPLD and the I2C Switch chip are connected with the plurality of hard disks, and the plurality of hard disks are respectively connected with the backboard high-speed connector on the same backboard through a PCIe bus.

In some embodiments, the CPLD connects with a backplane low speed connector on the same backplane through a VPP signal.

In some embodiments, the motherboard low speed connectors and the backplane low speed connectors of each backplane are simplex connectors.

In some embodiments, the plurality of motherboard high speed connectors and the backplane high speed connector of each backplane are slimline connectors.

In some embodiments, the plurality of motherboard high speed connectors and the backplane high speed connector of each backplane are MCIO connectors.

In some embodiments, the in-place signal of each backplane is divided into four paths to be connected to four backplane MCIO connectors, a motherboard MCIO connector corresponding to each backplane MCIO connector is arranged on the motherboard, and the four motherboard MCIO connectors connected to the same backplane are wired together and input to the Expander chip.

The server supporting multi-backplane cascade controls the switch of the backplane I2C channel by defining the backplane on the Expander chip and the enabling signal of the I2C repeater on the backplane, so that I2C communication is performed by selecting one backplane from a plurality of backplanes through the mainboard and the backplane low-speed connector by utilizing the Expander chip through the mainboard and the backplane high-speed connector, the problem of address repetition of the cascade backplane I2C is solved, meanwhile, the design of the cascade backplane is kept uniform, different backplanes do not need to be distinguished, the cost of later-stage operation and maintenance is reduced, the polling efficiency of the backplane equipment accessed by the baseboard management controller is improved, and the load of an I2C bus is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

FIG. 1 is a schematic diagram of a server connection in a first manner of cascading a motherboard and multiple backplanes in the prior art;

FIG. 2 is a schematic diagram illustrating a connection between a conventional motherboard and a server in a second manner of multi-backplane cascade connection;

fig. 3 is a schematic diagram of a server supporting multi-backplane cascading according to an embodiment of the present invention;

fig. 4 is a schematic diagram illustrating a definition of a part of signals in an MCIO connector according to another embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

In an embodiment, referring to fig. 3, the present invention provides a server supporting multi-backplane cascade, where the server includes:

the system comprises a Mainboard (MB), wherein a Baseboard Management Controller (BMC), a mainboard low-speed connector, an Expander chip and a plurality of mainboard high-speed connectors are arranged on the mainboard, the baseboard management controller is connected to the mainboard low-speed connector through an I2C bus, and the baseboard management controller is connected to the Expander chip through an I2C bus;

a plurality of backplates (BP for short), each backplane is provided with an I2C Repeater (I2C Repeater), a backplane low-speed connector connected with the I2C Repeater and a backplane high-speed connector connected with the I2C Repeater, the backplates are sequentially connected in series and then connected with the mainboard low-speed connector, each backplane corresponds to a mainboard high-speed connector, and each backplane high-speed connector is connected with the corresponding mainboard high-speed connector and then connected to an Expander chip; the baseboard management controller is configured to detect an in-place backplane through a plurality of mainboard high-speed connectors and corresponding backplane high-speed connectors, enable any I2C repeater of the in-place backplane through the Expander chip, and use the backplane where the enabled I2C repeater is located as a gated backplane.

In yet another embodiment, each motherboard high-speed connector and the Expander chip are connected through two signal lines, wherein one signal line is used for transmitting the in-place signal of the backplane, and the other signal line is used for transmitting the enable signal of the I2C repeater of the backplane.

In another embodiment, please refer to fig. 3 again, in which the server further includes: and each central processing unit is connected with the low-speed connector of the mainboard through a VPP signal.

Preferably, each central processor is connected to each motherboard high-speed connector via a PCIe bus.

In yet another embodiment, each backplane further comprises a CPLD, an I2C Switch chip, and a plurality of hard disks;

In yet another embodiment, the CPLD is connected to the backplane low speed connector on the same backplane via a VPP signal.

Preferably, the motherboard low-speed connector and the backplane low-speed connector of each backplane are both simplex connectors.

Preferably, the plurality of motherboard high-speed connectors and the backplane high-speed connector of each backplane are slimline connectors.

Preferably, the plurality of motherboard high-speed connectors and the backplane high-speed connector of each backplane are MCIO connectors.

In another embodiment, please refer to fig. 4, the in-place signal of each backplane is divided into four paths to be connected to four backplane MCIO connectors, the motherboard has a motherboard MCIO connector corresponding to each backplane MCIO connector, and the four motherboard MCIO connectors connected to the same backplane are wired together and input to the Expander chip.

In this embodiment, four backplane MCIO connectors are used on each backplane to monitor in-place signals of backplane hard disks, and only one of the hard disks needs to be online, the backplane in-place signals can be transmitted to the motherboard, and all the hard disks on the backplane do not need to be in place, thereby realizing flexible configuration of the backplane.

In another embodiment, to facilitate understanding of the technical solution of the present invention, the server shown in fig. 3 below is taken as an example, and includes two CPUs, three backplanes with the same configuration, each backplane having a sideband connector and eight hard disks. Currently, PCIe high-speed signals in existing server designs are generally connected to a backplane through slimine connectors, MCIO connectors, and other types of connectors, in this embodiment, the MCIO connectors are taken as an example, and each backplane has four MCIO connectors to connect eight hard disks.

As shown in fig. 3, the Expander chip defines a backplane bit signal BPx _ PRESNT and an enable signal REPEATERx _ EN of I2C Repeater on the backplane, which are connected to the backplane through the MCIO connector. When the BMC needs to interact with the I2C device on the backboard and acquire information, the level state of the BPx _ PRESNT signal is detected first, whether the backboard is in place is indicated, when the backboard is in place, a REPEATER _ EN signal is output to enable the I2C REPEATER on the corresponding backboard, an I2C channel is opened, and normal I2C interaction is performed. When the backplane is not in place or the BMC needs to access another backplane, the I2C channel is closed, so that the I2C channel of only one backplane at most is ensured to be in an open state at the same time, the problem of repeated I2C device addresses on a plurality of backplanes is avoided, and the load on an I2C bus is reduced.

When the layout is carried out on the backboard, the I2C Repeater and the CPLD are close to the sideband connector as much as possible, and meanwhile, the CPU VPP signal and the I2C signal are cascaded in a cable mode shown in the schematic diagram of the figure 3. The cables are arranged according to a topology similar to a daisy chain, and when the number of the backplanes is different, the stub of the signal can be reduced by changing the cables, so that the signal quality is improved.

Taking the conventional x8 MCIO connector as an example, 4 MCIO connectors are required for an 8-port backplane. As shown in FIG. 4, the invention divides the BPx _ PRESNT signal into 4 paths at the backplane end to be connected to 4 MCIO connectors, and the lines are input into the IO Expander together after the MCIO connectors are led out at the motherboard end. When the backplane only needs a small number of hard disks or part of cables are damaged, the on-site information of the backplane can be informed to the main board as long as one MCIO connector is normally connected. The REPEATERX _ EN signal is similar to the REPEATERX _ EN signal, and the I2C channel can be opened only by at least one MCIO connector in place, so that the fault tolerance rate of the system is improved. The detailed steps of the hard disk on which the mainboard is connected with one backboard to use are as follows:

the method comprises the following steps: VPP signals of a central processing unit (CPU0/1) and I2C signals for back panel interaction of BMC are connected to the side band, and are connected to the CPLD and each I2C device of the back panel in a cascading cable mode. Only one level of I2C Switch chip exists in the whole I2C link, so that the efficiency of BMC polling access to the hard disk is improved.

Step two: the Expander chip Port0 is connected with a backplane and is used for detecting whether the backplane is in place or not through an MCIO connector transmission line and a subsequent BPx _ PRESNT signal; the Port1 outputs the REPEATERX _ EN signal of the backplane terminal I2CRepeater, and is also connected to the I2C Repeater on and after the backplane;

step three, after the server is powered on, the BMC detects the in-place state of each backboard through the IO Expander Port0, and when information (such as temperature, hard disk information, FRU information and the like) on the backboard needs to be acquired, outputs a REPEATERx _ EN signal of the corresponding backboard through the Port1, opens an I2C channel on the backboard, and performs interaction. Closing the channel after completion can continue to interact in the same manner with the next backplane.

And step four, transmitting the Port information of the PCIe of the mainboard to a CPLD of the backboard through the MCIO connector in a PCIe Port ID format, analyzing the VPP signal sent by the CPU by the CPLD, and then comparing the VPP signal with a set PCIe Port ID table to finish lighting action.

The server supporting multi-backboard cascade connection at least has the following beneficial technical effects:

1) the design of the cascade back plates is kept uniform, different back plates are not distinguished through the bill of materials, the quantity of the bill of materials of the board cards is reduced, and the cost of later-stage operation and maintenance is reduced

2) The whole I2C link only uses a first-level I2C Switch chip, the polling efficiency of the baseboard management controller for accessing each device is improved, and meanwhile, when the baseboard management controller works, only one piece of I2C device on the backboard exists in the whole link, so that the load of an I2C bus is reduced;

3) the VPP signal and the I2C signal are routed in a daisy chain like topology, which improves signal quality by reducing the length of stub by modification.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A server supporting multi-backplane cascading, the server comprising:

2. The server according to claim 1, wherein each motherboard high-speed connector and the Expander chip are connected by two signal lines, wherein one signal line is used for transmitting an in-place signal of the backplane, and the other signal line is used for transmitting an enable signal of an I2C repeater of the backplane.

3. The server according to claim 2, wherein the server further comprises: and each central processing unit is connected with the low-speed connector of the mainboard through a VPP signal.

4. The server of claim 3, wherein each central processor is connected to each motherboard high-speed connector via a PCIe bus.

5. The server according to claim 4, wherein each backplane further comprises a CPLD, an I2C Switch chip, and a plurality of hard disks;

6. The server of claim 5, wherein the CPLD is connected to a backplane low speed connector on the same backplane via a VPP signal.

7. The server according to any of claims 1-6, wherein the motherboard low speed connectors and the backplane low speed connectors of each backplane are simplex connectors.

8. The server according to any one of claims 1 to 6, wherein the plurality of motherboard high speed connectors and the backplane high speed connector of each backplane are slimline connectors.

9. The server according to any one of claims 1 to 6, wherein the plurality of motherboard high speed connectors and the backplane high speed connector of each backplane are MCIO connectors.

10. The server according to claim 9, wherein the in-place signal of each backplane is divided into four paths to be connected to four backplane MCIO connectors, a motherboard MCIO connector corresponding to each backplane MCIO connector is arranged on the motherboard, and the four motherboard MCIO connectors connected to the same backplane are connected together to be input to the Expander chip.