CN1143200A - 制造光掩模的方法 - Google Patents

制造光掩模的方法 Download PDF

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CN1143200A
CN1143200A CN95102950A CN95102950A CN1143200A CN 1143200 A CN1143200 A CN 1143200A CN 95102950 A CN95102950 A CN 95102950A CN 95102950 A CN95102950 A CN 95102950A CN 1143200 A CN1143200 A CN 1143200A
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photomask
pattern
error
vernier
line
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CN1085849C (zh
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黄�俊
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G03F1/42—Alignment or registration features, e.g. alignment marks on the mask substrates

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

通过在产品模片图样四边上形成划线，并且在划线的四角上形成微调图样，制造光掩模。微调图样由正方形区域和正方形带状区域构成。采用光掩模对互相重叠并以预定曝光次数曝光的微调图样显影，全面得到各类误差值，即曝光机的刻线旋转误差，X轴和Y轴步进误差，透镜的弯曲误差，以及由于光掩模的制造误差而在芯片上形成的图样误差。

Description

制造光掩模的方法
本发明涉及一种制造光掩模的方法，特别是通过在产品模(芯)片图样(形)各边形成划线或刻线(soribe lines)，在各角形成预定形状的图样，以及根据各个曝光图样测量误差能够容易地测量出包括曝光机的每个误差和光掩模的制造误差在内的全部误差。
在光掩模的传统制造方法中，光掩模图样是按照图1中在产品模片图样4的底边和右边形成划线或刻线2而制造的。但是采用这种已有技术制造光掩模的方法存在一些问题，即使用这种光掩模不能全面测出曝光机的刻线旋转误差所导致的图线不能对准，以及X轴和Y轴的步进误差，透镜弯曲误差，和由于光掩模的制造误差在半导体片上形成的图样误差。
本发明的一个目的是提供一种制造光掩模的方法，该方法在产品模片图样四边上形成划线，在产品模片图样的四角上形成预定形状的图样，能够容易地测量出包括曝光机的每个误差和光掩模的制造误差在内的全部误差。
为了实现上述目的，提供了一种制造光掩模的方法，包括以下步骤：在产品模片图样四边上形成划线；在划线四角上形成微调图样(vernier patterns)，从而通过对互相重叠并且以预定次数曝光的微调图样显影，能测出包括曝光机的每个误差和光掩模的制造误差在内的全部误差。
本发明的其它目的、特征和特点以及相关部分的功用通过下面的详细说明，权利要求书以及附图，能够使本专业的普通技术人员清楚地理解。附图说明如下：
图1是包括产品模片和划线的现有光掩模平面图；
图2是本发明四边划线的光掩模平面图；
图3是本发明光掩模各角的图样平面图；
图4是本发明光掩模在半导体基片上的曝光图样。
以下参照附图，叙述本发明的优选实施例。
图2是本发明在四边上有划线的光掩模平面图，图3是本发明光掩模各角的微调图样平面图，而图4是本发明光掩模在半导体基片上形成的曝光图样。
在附图中，标号2是划线，4是产品模片图样。
如图2所示，在光掩模上，产品模片图样4的四边形成划线2，而如图3所示的四角具有同样形状的微调图样是用镀铬层实现的。每个微调图样包括正方形区域6和正方形带状区域8。阴影线区域表示覆盖铬层的部分。
在准备好上述光掩模以后，装有图4所示光掩模的曝光机分步进行曝光，在半导体片上形成图样。
使划线2互相重叠，重复行列方向等节距的步进曝光，在各个角形成的微调图样A、B、C和D互相重叠起来。
其后，曝光机的刻线旋转误差，X和Y轴步进误差，曝光机上安装的透镜的弯曲误差，以及由于光掩模的制造误差而在芯片上形成的图样误差均可以在芯片显影以后通过测量介于正方形区域6和正方形带状区域8之间X1、X2、Y1和Y2的长度而得出。
如图4所示，微调图样A、B、C和D分别互相重叠，且位于同一位置曝光。在这种情况下，各个曝光图样会显示出各种误差。所以，在芯片显影以后可以发现误差因素。而且，因为每一个微调图样A至D均在产品模片4的各角上构成，所以能发现最大误差因素。
根据以上详述，因为本发明的光掩模是通过在产品模片图样四边上形成划线，在四角上形成微调图样的方法制造的，所以，曝光机的刻线旋转误差，X和Y轴步进误差，透镜的弯曲误差，以及由于光掩模的制造误差在芯片上形成的图样误差均可以被发现。
以上就最实用和最优选的实施例对本发明予以描述。然而，本发明不受上述描述的限定，相反上述叙述在所附权利要求精神和范围内，还包括各种改动和等效的设计。

Claims (1)

1、一种制造光掩模的方法，其特征在于包括以下步骤：
在产品模片图样的四边上形成划线，在划线的四角形成微调图样，通过对互相重叠并采用光掩模以预定曝光次数进行曝光的微调图样进行显影，可完全测出曝光机的每个误差和光掩模的制造误差。
CN95102950A 1994-03-10 1995-03-10 制造光掩模的方法 Expired - Fee Related CN1085849C (zh)

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KR1994-4719 1994-03-10
KR1019940004719A KR0168772B1 (ko) 1994-03-10 1994-03-10 포토마스크 및 그를 이용한 반도체 장치 제조 방법

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CN1143200A true CN1143200A (zh) 1997-02-19
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104570589A (zh) * 2013-10-12 2015-04-29 北大方正集团有限公司 掩模板及利用掩模板进行光刻和测量步进精度的方法

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980030438A (ko) * 1996-10-29 1998-07-25 김영환 반도체 버어니어 구조 및 그것을 이용한 오버레이 정확도 측정방법
US5837404A (en) * 1997-01-04 1998-11-17 Holtek Microelectronics, Inc. Fabrication of zero layer mask
US5952132A (en) * 1997-09-12 1999-09-14 Taiwan Semiconductor Mfg. Co. Method for forming a stepper focus pattern through determination of overlay error
TW436878B (en) * 1998-09-08 2001-05-28 Mosel Vitelic Inc Method for checking accuracy of a measuring instrument for overlay machine
JP2001092109A (ja) * 1999-09-24 2001-04-06 Mitsubishi Electric Corp フォトマスクおよび半導体装置およびフォトマスクを用いた露光方法
US6462818B1 (en) 2000-06-22 2002-10-08 Kla-Tencor Corporation Overlay alignment mark design
US7541201B2 (en) 2000-08-30 2009-06-02 Kla-Tencor Technologies Corporation Apparatus and methods for determining overlay of structures having rotational or mirror symmetry
US7068833B1 (en) * 2000-08-30 2006-06-27 Kla-Tencor Corporation Overlay marks, methods of overlay mark design and methods of overlay measurements
US6486954B1 (en) 2000-09-01 2002-11-26 Kla-Tencor Technologies Corporation Overlay alignment measurement mark
US7804994B2 (en) * 2002-02-15 2010-09-28 Kla-Tencor Technologies Corporation Overlay metrology and control method
US7075639B2 (en) * 2003-04-25 2006-07-11 Kla-Tencor Technologies Corporation Method and mark for metrology of phase errors on phase shift masks
US7608468B1 (en) * 2003-07-02 2009-10-27 Kla-Tencor Technologies, Corp. Apparatus and methods for determining overlay and uses of same
US7346878B1 (en) 2003-07-02 2008-03-18 Kla-Tencor Technologies Corporation Apparatus and methods for providing in-chip microtargets for metrology or inspection
US7557921B1 (en) 2005-01-14 2009-07-07 Kla-Tencor Technologies Corporation Apparatus and methods for optically monitoring the fidelity of patterns produced by photolitographic tools
DE102010034875A1 (de) 2010-07-16 2012-01-19 Felix Heide Positionskennzeichen
US9927718B2 (en) 2010-08-03 2018-03-27 Kla-Tencor Corporation Multi-layer overlay metrology target and complimentary overlay metrology measurement systems
US10890436B2 (en) 2011-07-19 2021-01-12 Kla Corporation Overlay targets with orthogonal underlayer dummyfill
US10451412B2 (en) 2016-04-22 2019-10-22 Kla-Tencor Corporation Apparatus and methods for detecting overlay errors using scatterometry

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57198627A (en) * 1981-06-01 1982-12-06 Fujitsu Ltd Reticle
JPS6083328A (ja) * 1983-10-13 1985-05-11 Fujitsu Ltd フオトマスクの検査方法
JP2666859B2 (ja) * 1988-11-25 1997-10-22 日本電気株式会社 目合せ用バーニヤパターンを備えた半導体装置
JPH0312916A (ja) * 1989-06-12 1991-01-21 Nec Corp 電子ビーム描画方法
JPH0444307A (ja) * 1990-06-12 1992-02-14 Nec Corp 半導体装置の製造方法
JP3042639B2 (ja) * 1991-07-12 2000-05-15 日本電気株式会社 半導体装置製造用フォトレティクル
KR100273785B1 (ko) * 1991-07-18 2001-01-15 기타지마 요시토시 정합패턴을 갖는 패턴판의 묘화방법 및 그 방법에 의하여 묘화된 패턴판
KR970010666B1 (ko) * 1993-12-27 1997-06-30 현대전자산업 주식회사 반도체 소자의 패턴 중첩오차 측정방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104570589A (zh) * 2013-10-12 2015-04-29 北大方正集团有限公司 掩模板及利用掩模板进行光刻和测量步进精度的方法
CN104570589B (zh) * 2013-10-12 2018-08-07 北大方正集团有限公司 掩模板及利用掩模板进行光刻和测量步进精度的方法

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KR950027969A (ko) 1995-10-18
GB2287328A (en) 1995-09-13
US5665495A (en) 1997-09-09
CN1085849C (zh) 2002-05-29
GB9504906D0 (en) 1995-04-26
KR0168772B1 (ko) 1999-02-01
GB2287328B (en) 1997-11-19

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