CN114286027A - 最小高度cmos图像传感器 - Google Patents

最小高度cmos图像传感器 Download PDF

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CN114286027A
CN114286027A CN202111598156.0A CN202111598156A CN114286027A CN 114286027 A CN114286027 A CN 114286027A CN 202111598156 A CN202111598156 A CN 202111598156A CN 114286027 A CN114286027 A CN 114286027A
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冯琛
E.C.布雷默
T.冼
P.A.焦尔达诺
S.P.基尔尼
P.波罗尼维奇
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Hand Held Products Inc
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    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/14643—Photodiode arrays; MOS imagers
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    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
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    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
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    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14607—Geometry of the photosensitive area

Abstract

本申请涉及最小高度CMOS图像传感器，其中，提供了一种用于相机组装件的CMOS图像传感器，具有带有相对的面的传感器管芯，所述相对的面为上面和下面。在上面上，传感器管芯提供有传感器阵列、模拟向数字转换模块、数字逻辑电路、以及时序和时钟控制电路。传感器阵列基本上集中在传感器管芯上。模拟向数字转换模块划分成两个子模块。每一个子模块设置成邻近于传感器阵列并且定位在传感器阵列的相对侧部上。数字逻辑电路形成第一行。时序和时钟控制电路以及模拟信号处理电路邻近并且形成第二行。第一行和第二行具有类似尺寸并且设置在传感器阵列的相对侧部上。

Description

最小高度CMOS图像传感器
本申请是申请日为2017年6月21日，申请号为201710474223.5并且发明名称为“最小高度CMOS图像传感器”申请的分案申请。
技术领域
本发明涉及互补金属氧化物半导体型（CMOS）图像传感器。
背景技术
一般而言，用于CMOS图像传感器的传感器管芯的布局包括传感器阵列、模拟向数字（ADC）模块、数字逻辑电路以及时序和控制面板。传感器阵列没有集中（center）在传感器管芯上以便将类似组件保持在一起。优化传感器管芯布局设计以便将相似组件保持在一起，这允许一些优点。例如，常规图像传感器中的ADC模块以行到行图像数字格式进行输出，这与传统图像显示设备兼容。然而，存在对这些布局设计的不利后果。例如，牺牲使传感器阵列集中在管芯上以便将类似组件保持在一起。附加地，通过将相似组件保持在一起，用于传感器的较小足迹的可能性对常规（convention）形成要挟。这对于诸如成像条形码扫描仪之类的边缘安装传感器可能尤其成问题。
因此，存在对如下CMOS图像传感器的需要，该CMOS图像传感器允许传感器阵列尽可能多地集中在管芯上，并且对于常规图像传感器而言具有最小高度。
发明内容
因而，在一个方面中，本发明涵盖了一种用于相机组装件的CMOS图像传感器。
在示例性实施例中，CMOS图像传感器包括具有相对的面（上面和下面）的传感器管芯。传感器管芯具有上面上的组件，所述组件包括传感器阵列、模拟向数字转换模块、数字逻辑电路、时序和时钟控制电路、以及模拟信号处理电路。传感器阵列具有第一组和第二组相对侧部。第一组相对侧部包括顶部边缘和底部边缘。第二组是第一边缘和第二边缘。传感器阵列基本上集中在传感器管芯上。模拟向数字转换模块设置在两个子模块中。每一个子模块设置为邻近于传感器阵列并且定位在传感器阵列的相对侧部上。每一个子模块定位在传感器阵列的第一组相对侧部的任一侧部上，或者定位在传感器阵列的第二组相对侧部的任一侧部上。数字逻辑电路形成第一行。具有模拟信号处理电路的时序和时钟控制电路邻近于彼此并且形成第二行。第一行和第二行具有类似尺寸并且设置在传感器阵列的第二组相对侧部的相对侧部上。
在CMOS图像传感器的另一个示例性实施例中，模拟向数字转换子模块在尺寸上均匀地划分。
在CMOS图像传感器的另一个示例性实施例中，每一个模拟向数字转换子模块形成邻近第二组相对侧部中的每一个定位的子模块行。一个子模块行在数字逻辑电路的第一行和传感器阵列第一边缘之间。第二子模块行在第二行和传感器阵列第二边缘之间，所述第二行由具有模拟信号处理电路的时序控制电路形成。
在CMOS图像传感器的另一个示例性实施例中，每一个模拟向数字转换子模块形成邻近传感器阵列的第一组相对侧部中的每一个定位的子模块列。
在另一个示例性实施例中，CMOS图像传感器进一步包括存储器管芯。存储器管芯包括帧缓冲器存储器。存储器管芯具有第一和第二相对的面。存储器管芯和传感器管芯具有基本上类似的面尺寸。存储器管芯的第一面在传感器管芯的下面之下，在尺寸上对准以及邻近于传感器管芯的下面。CMOS图像传感器进一步包括硅通孔。硅通孔电气连接存储器管芯和传感器管芯。
在另一个示例性实施例中，CMOS图像传感器进一步包括处理管芯。处理管芯具有上面。处理管芯和存储器管芯具有基本上类似的面尺寸。处理管芯的上面在存储器管芯的第二面之下，在尺寸上对准以及邻近于存储器管芯的第二面。处理管芯和存储器管芯与硅通孔电气连接。
在CMOS传感器的另一个示例性实施例中，传感器管芯具有与传感器阵列的第二组相对侧部平行的相对竖直边缘。CMOS图像传感器进一步提供有键合（bonding）垫。键合垫形成两个键合垫行。第一键合垫行定位在与传感器管芯的相对竖直边缘之一毗邻的传感器管芯的上面上。第二键合垫行定位在与传感器管芯的相对竖直边缘中的第二个毗邻的传感器管芯的上面上。
在另一个示例性实施例中，CMOS图像传感器进一步提供有具有中央处理单元的处理管芯。处理管芯与存储器管芯处在相同的管芯上。
在CMOS图像传感器的又一个示例性实施例中，处理管芯包括中央处理单元。
在CMOS图像传感器的另一个示例性实施例中，传感器阵列是像素传感器彩色成像阵列，所述像素传感器彩色成像阵列包括布置在行和列中的像素。另外，传感器阵列具有用于在传感器阵列上捕获的像素到模拟向数字转换模块的输出序列。输出序列配置为逐列地将像素发送给模拟向数字转换模块，一列中的偶数编号的像素去往要转换成数字输出的模拟向数字转换子模块之一，并且一列中的奇数编号的像素去往要转换成数字输出的模拟向数字转换子模块中的另一个。来自两个模拟向数字转换子模块的数字输出在传感器管芯的输出端口处重新组合。
在另一个示例性实施例中，CMOS图像传感器进一步提供有视频序列转换器。视频序列转换器设置在传感器管芯的下面上。视频序列转换器具有双端口帧缓冲器、数字逻辑和时序控制。视频序列转换器配置为以逐列图像格式从两个模拟向数字转换子模块接收数字输出。视频序列转换器进一步配置为以逐行图像格式输出数字图像。
在另一个示例性实施例中，视频序列转换器帧缓冲器包括校正几何失真的数字读出逻辑。
在另一个示例性实施例中，视频序列转换器配置为分别在偶数和奇数行中输出数字图像以便支持交错显示。
在另一个示例性实施例中，CMOS图像传感器包括视频序列转换器。视频序列具有双端口帧缓冲器、数字逻辑和时序控制。视频序列转换器配置为以逐列图像格式从两个模拟向数字转换子模块接收数字输出。视频序列转换器进一步配置为以逐行图像格式输出数字图像。视频序列转换器设置在除传感器管芯上之外的位置处。视频定序器的位置可以是利用硅通孔电气连接到传感器管芯的管芯。
在另一方面中，本发明涵盖了一种用于相机组装件的CMOS图像传感器，所述CMOS图像传感器包括具有相对的面（上面和下面）的传感器管芯。传感器管芯具有其上面上的组件。这些包括传感器阵列、模拟向数字转换模块、数字逻辑电路、时序和时钟控制电路、以及模拟信号处理电路。传感器管芯具有相对竖直边缘。传感器阵列具有第一和第二组相对侧部。第一组包括顶部边缘和底部边缘。第一组平行于传感器管芯的相对竖直边缘。第二组包括第一边缘和第二边缘。传感器阵列基本上集中在传感器管芯上的相对竖直边缘之间。模拟向数字转换模块设置成邻近于传感器阵列并且定位在接近于传感器阵列的第二组相对侧部之一的行中。数字逻辑电路形成第一行。时序和时钟控制电路以及模拟信号处理电路邻近于彼此并且形成第二行。第一行和第二行具有类似尺寸。第一和第二行设置在传感器阵列的第二组相对侧部的相对侧部上。
在示例性实施例中，CMOS图像传感器进一步提供有存储器管芯。存储器管芯具有相对的面。存储器管芯和传感器管芯具有基本上类似的面尺寸。存储器管芯的第一面在传感器管芯的下面之下，在尺寸上对准以及邻近于传感器管芯的下面。CMOS图像传感器还提供有硅通孔。硅通孔电气连接存储器管芯和传感器管芯。
在另一个示例性实施例中，CMOS图像传感器进一步提供有处理管芯。处理管芯具有相对的面。处理管芯和存储器管芯具有基本上类似的面尺寸。处理管芯的第一面在存储器管芯的第二面之下，在尺寸上对准以及邻近于存储器管芯的第二面。处理管芯和存储器管芯与硅通孔电气连接。
在另一个示例性实施例中，CMOS图像传感器提供有键合垫。键合垫形成两个键合垫行。第一键合垫行定位在与传感器管芯的相对竖直边缘之一毗邻的传感器管芯的上面上。第二键合垫行定位在与传感器管芯的相对竖直边缘中的第二个毗邻的传感器管芯的上面上。
在CMOS图像传感器的另一个示例性实施例中，存储器管芯包括帧缓冲器存储器。
在CMOS图像传感器的另一个示例性实施例中，处理管芯包括中央处理单元。
本发明的前述说明性总结和其它示例性目的和/或优点，以及实现所述总结、目的和/或优点的方式，在以下具体实施方式及其附图中进一步解释。
附图说明
图1示意性描绘了现有技术CMOS图像传感器管芯布局。
图2示意性描绘了依照本发明的最小高度CMOS图像传感器管芯。
图3示意性描绘了依照本发明的经划分的列ADC CMOS传感器管芯。
图4示意性描绘了依照本发明的行ADC CMOS传感器管芯。
图5示意性描绘了依照本发明的堆叠式传感器管芯。
图6以流程图描绘了用于图5的传感器管芯的处理输出。
具体实施方式
现有技术CMOS图像传感器具有一般地如在现有技术附图1中描绘的布局。一般而言，现有技术CMOS传感器（10）具有传感器管芯（11）上的组件的布局，所述组件包括传感器阵列（12）、模拟向数字（ADC）模块（13）、数字逻辑电路（4）、时序和控制面板（5）、模拟信号处理模块（17），并且可以包括在传感器管芯（11）的周界周围的键合垫（18）。如可以从附图看到的，现有技术传感器阵列（12）未集中在传感器管芯（11）上。
本发明涵盖了一种用于相机组装件的CMOS图像传感器，所述CMOS图像传感器具有集中在传感器管芯上的传感器阵列并且具有较小的足迹。
在示例性实施例中，参照图2，提供了CMOS图像传感器（200）。图2的特定实施例具有最小高度。CMOS传感器（200）具有保持传感器的其它组件的传感器管芯（21）。传感器管芯（21）具有一组相对的面（22），上面指定为（22a）并且没有在该图中示出下面。传感器阵列（24）在传感器管芯（21）上。传感器阵列（24）可以是像素传感器彩色成像阵列，所述像素传感器彩色成像阵列包括布置在行和列中的像素。传感器阵列（24）具有第一组（25）和第二组（26）相对侧部。第一组（25）是传感器阵列（24）的顶部边缘（25a）和底部边缘（25b）。第二组（26）是第一边缘（26a）和第二边缘（26b）。传感器管芯（21）还具有模拟向数字模块（ADC）（27）。ADC（27）划分成两个模块，子模块（27a）和子模块（27b）。在本实施例中，每一个ADC子模块（27a和27b）定位在邻近于传感器阵列（24）的第二组相对侧部（26）中的每一个的传感器阵列（24）的任一侧部上。传感器管芯（21）还包括数字逻辑电路（28），数字逻辑电路（28）形成设置在传感器阵列（24）的第二组相对侧部（26）的第一个（26a）上的电路行。时序和时钟控制电路（29）以及模拟信号处理电路（30）形成设置在传感器阵列（24）的第二组相对侧部（26b）中的第二个（26b）上的第二行。ADC子模块（27a和27b）直接定位成邻近于传感器阵列（24）。键合垫（39）布置在传感器管芯（21）的外边缘（23）上。在其它实施例中，键合垫（39）可以在传感器管芯（21）的顶部和底部边缘上延伸。如可以看到，ADC子模块（27a和27b）在尺寸上基本上类似。
通过将ADC子模块（27a和27b）定位成邻近于第二组相对侧部（26a和26b）中的每一个，传感器管芯（21）通过仅在与传感器管芯（21）的竖直边缘（23）毗邻的传感器管芯（21）上定位键合垫以及在传感器阵列（24）与时序和时钟控制电路（29）和模拟信号处理电路（30）相对的侧部上定位数字逻辑电路（28）而保证了传感器管芯（21）具有最小高度，实质上是传感器阵列（24）本身的高度。在该配置中，传感器阵列（24）在竖直上以及在水平上均集中在传感器管芯（21）上。与使用该最小高度传感器管芯相关联的相机组装件可以实现最小竖直尺寸以便允许将它集成到较薄的移动应用设备中。尽管许多智能设备具有6.5到7.0mm的厚度，但是很快这些就可以减少为小于6.0mm。因此，当前图2的最小高度实施例可以满足这些新的较瘦设计。
在图3中描绘的另一个示例性实施例中，CMOS图像传感器（300）在配置上的类似之处在于，传感器阵列（24）集中在传感器管芯（21）上。然而，在本实施例中，ADC子模块（27a和27b）定位在传感器阵列（24）的第一组（25）相对侧部（25a和25b）上。附加地，键合垫（39）定位在传感器管芯的所有侧部周围。该图中的CMOS图像传感器（300）的配置相比现有技术（图1）的优点在于，传感器阵列是集中的，然而，传感器高度与现有技术相同。偏移相关的透镜-传感器组装件尺寸可以由于传感器阵列（24）的集中而最小化。
在图4中描绘的另一个示例性实施例示出了依照本发明的用于CMOS图像传感器（400）布局的另一选项。通过将ADC模块（27）保持为一行，邻近于传感器阵列（24）的一个侧部，减少了传感器管芯（21）的高度。尽管传感器阵列（24）保持竖直上集中在传感器管芯（21）上，但是现在存在水平偏移。该水平偏移成为新的问题，因为具有过量偏移的宽水平方向尺寸将使得与非对称结构的透镜-传感器集成以及热学相关质量问题进一步复杂化。
在图5中描绘的又一个示例性实施例中，提供了并且从传感器管芯的上面（22a）以及从侧视角示出了CMOS图像传感器（500）。CMOS图像传感器（500）非常类似于图1的最小高度CMOS图像传感器（200）。然而，本实施例不存在键合垫。本实施例示出了具有双帧缓冲器的堆叠式管芯CMOS图像传感器。
提供了存储器管芯（33）。存储器管芯具有相对的面（34），第一面（34a）和第二面（34b）。存储器管芯（33）的面尺寸类似于传感器管芯（21）的面尺寸。存储器管芯（33）定位在传感器管芯（21）的下面（22b）之下，并且与传感器管芯（21）对准。硅通孔（36）将传感器管芯（21）电气连接到存储器管芯（33）。存储器管芯包括帧缓冲器存储器（未示出）。尽管没有在该图中示出，但是在一些情况下（特别地，当电子组件的大小变得减少时），处理管芯可以与存储器管芯提供在相同管芯上。
在当前图5中描绘的另外的实施例中，处理管芯（37）还提供在分离的管芯上。处理管芯具有上面（38）。处理管芯（37）的面尺寸类似于存储器管芯（33）的面尺寸。处理管芯（37）定位在存储器管芯（33）的第二面（34b）之下并且与存储器管芯（33）对准。硅通孔（36）将存储器管芯（33）电气连接到处理管芯（37）。处理管芯（37）包括中央处理单元（CPU）（未示出）。
如在此之前所讨论的，传感器阵列优选地是像素传感器彩色成像阵列，所述像素传感器彩色成像阵列包括布置在行和列中的像素。传感器阵列具有用于在传感器阵列上捕获的像素向ADC模块的输出序列。因为ADC模块划分成两个成行（row-wise）子模块，所以传感器阵列输出序列必须适应该布置。因而，从传感器阵列向ADC子模块的像素的输出序列是逐列式的，其中偶数编号的像素去往ADC子模块中的一个，并且奇数编号的像素去往ADC子模块中的另一个。ADC子模块将像素转换成数字输出，并且以逐列数字输出在传感器管芯的输出端口（未示出）处重新组合现在的数字输出。因为一些显示设备仅可以处理逐行数字输出，所以本发明的CMOS传感器在使用多于一个ADC子模块时（例如图2、3和5）提供有视频序列转换器。视频序列转换器以逐列格式接收数字图像信号并且以逐行图像格式输出数字图像。在一些情况下，视频序列转换器配置为分别在偶数和奇数行中输出数字图像以便支持传统交错显示。
视频序列转换器可以包括双端口帧缓冲器、数字逻辑和时序控制。帧缓冲器可以包括校正几何失真的逻辑。
转换的视频序列可以位于传感器管芯的下面上。在其中存储器管芯位于传感器管芯的下面处并且在所述下面处连接到传感器管芯的配置中，视频序列转换器可以位于存储器管芯上或者例如位于处理管芯上。如果位于分离的管芯上，则视频序列转换器以硅孔电气连接到传感器管芯的输出。
视频序列转换器给予本发明CMOS图像传感器更多的多样性。例如，传统图像显示设备（诸如TV）以逐行信号输入工作在“光栅扫描模式”中。常规CMOS图像传感器可以直接连接到这些显示设备。最小高度CMOS图像传感器（图2和图5）要求视频序列转换器支持这些传统显示设备。视频序列转换器是具有数字逻辑和时序控制的双端口帧缓冲器以便读入逐列图像并且输出逐行图像。相同的帧缓冲器还可以通过分别输出偶数和奇数行而支持传统交错显示。一些附加校正（诸如几何失真）也可以利用特殊编程的数字读出逻辑来执行。失真校正还可以用于校正卷帘（rolling）快门引入的运动失真或者甚至污点。
图6以流程图示出了根据图5的CMOS图像传感器（500）（包括存在视频序列转换器（40））的信号（600）的处理。如在此之前所讨论，传感器管芯（21）包括像素传感器阵列、ADC模块、以及时序和控制电路。存储器管芯（33）接收数据并且向处理管芯（37）上的CPU传送信息。传感器将像素输出给视频序列转换器（40），所述视频序列转换器（40）包括数字逻辑和时序功能。视频序列转换器（40）与存储器管芯（33）交互并且向处理管芯（37）上的CPU进行输出。处理管芯（37）上的CPU输出数字图像数据和控制功能。
在说明书和/或附图中，已经公开了本发明的典型实施例。本发明不限于这样的示例性实施例。术语“和/或”的使用包括相关联的列出项目中的一个或多个中的任一个和所有组合。附图是示意性表示并且因此未必按照比例绘制。除非以其它方式指出，否则具体术语已经以一般和描述性意义被使用并且不用于限制的目的。

Claims (10)

1.一种堆叠管芯CMOS图像传感器，包括：
具有传感器阵列和相对表面的传感器管芯，所述相对表面即传感器管芯上表面和传感器管芯下表面；
存储器管芯，所述存储器管芯具有邻近于所述传感器管芯下表面的第一相对表面，其中所述存储器管芯通过硅通孔电连接到所述传感器管芯；
处理管芯，通过硅通孔电连接到所述存储器管芯，其中所述处理管芯包括中央处理单元(CPU)，所述中央处理单元被配置为输出数字图像数据和控制功能；和
视频序列转换器，电连接到所述传感器管芯的输出，其中所述视频序列转换器被配置为将逐列图像格式的数字图像数据转换为逐行图像格式的数字图像数据。
2.根据权利要求1所述的堆叠管芯CMOS图像传感器，其中所述处理管芯具有邻近于所述存储器管芯第二相对表面的上表面，其中所述传感器管芯、所述存储器管芯和所述处理管芯被堆叠。
3.根据权利要求1或2所述的堆叠管芯CMOS图像传感器，其中所述视频序列转换器还被配置为与奇数行的数字图像数据分开地输出偶数行的数字图像数据。
4.根据权利要求1-3中任一项所述的堆叠管芯CMOS图像传感器，其中所述视频序列转换器还被配置为校正以下各项中的至少一项：几何失真、卷帘快门引入的运动失真和污点。
5.根据权利要求1-4中任一项所述的堆叠管芯CMOS图像传感器，其中所述传感器阵列具有第一组相对侧和第二组相对侧；第一组是顶部边缘和底部边缘，第二组是从第一组的顶部边缘延伸到底部边缘的第一边缘和第二边缘，传感器阵列基本上位于传感器管芯的中心。
6.根据权利要求5所述的堆叠管芯CMOS图像传感器，还包括模数转换模块；所述模数转换模块设置在两个子模块中，两个子模块中的每个均设置为邻近于所述传感器阵列，所述两个子模块定位成彼此分开，并且所述两个子模块分别位于从第一组和第二组中选择的所述传感器阵列的第二组相对侧上。
7.根据权利要求6所述的堆叠管芯CMOS图像传感器，其中所述两个模数转换子模块在尺寸上均匀地划分。
8.根据权利要求6-7中任一项所述的堆叠管芯CMOS图像传感器，其中所述两个模数转换子模块中的每一个分别形成一个子模块行，所述子模块行定位成邻近于所述第二组相对侧中的每一个，一个子模块行位于第一边缘中间，并且第二子模块行位于第二边缘中间。
9.根据权利要求8所述的堆叠管芯CMOS图像传感器，其中所述两个模数转换子模块中的每一个形成子模块列，所述子模块列被定位成邻近于所述第一组相对侧中的每一个。
10.根据权利要求1-9中任一项所述的堆叠管芯CMOS图像传感器，其中所述传感器阵列是由按行和列布置的像素组成的像素传感器彩色成像阵列。
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