CN114270506A - 无电极无源嵌入式衬底 - Google Patents

无电极无源嵌入式衬底 Download PDF

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Publication number
CN114270506A
CN114270506A CN202080058107.5A CN202080058107A CN114270506A CN 114270506 A CN114270506 A CN 114270506A CN 202080058107 A CN202080058107 A CN 202080058107A CN 114270506 A CN114270506 A CN 114270506A
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CN
China
Prior art keywords
electrodeless
cavity
multilayer substrate
passive component
die
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CN202080058107.5A
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English (en)
Inventor
K·康
S·崔
H·金
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Qualcomm Inc
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Qualcomm Inc
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Publication of CN114270506A publication Critical patent/CN114270506A/zh
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Abstract

公开了一种电子组件，该电子组件包括无电极无源部件(220)，该无电极无源部件(220)嵌入多层衬底(210)的腔中，其中腔(218)具有形成在腔的至少两个侧壁上的导电元件(214)。导电元件被配置为电耦合到无电极无源部件。无电极无源部件可以与多层衬底的外部表面相邻地定位在第一金属层中。

Description

无电极无源嵌入式衬底
优先权要求
本专利申请要求于2019年8月20日提交的题为“无电极无源嵌入式衬底”的申请号16/546,158的优先权，本专利申请转让给本申请的受让人并且在此通过引用明确并入本文。
技术领域
本公开涉及包括具有至少一个管芯和多层衬底的封装的电子设备，该多层衬底具有嵌入衬底内的无电极无源部件。
背景技术
集成电路(IC)技术通过有源部件的小型化在提高计算能力、信号处理和通信方面取得了长足的进步。集成无源部件也已小型化，并且这些部件的进一步小型化的趋势仍在继续。无源部件可以包括许多集成电路设备中的较大元件中的一些较大元件，如此通常在芯片外实现为表面贴装设备(SMD)。
具体地，SMD中的无源部件可以位于与管芯相邻的衬底上或位于其上安装有管芯的衬底上。这些无源部件可以用于滤波和其他电路，并且可以位于衬底的管芯侧上，因为通常期望将无源部件定位在尽可能靠近管芯的位置。无源部件还可以位于衬底的底部表面上，即，“着陆侧”，用于电源滤波、噪声抑制和其他功能。在一些实例中，无源部件可以位于衬底内以进一步使与管芯相距的距离最小。然而，这可能导致衬底的厚度增加，以允许传统无源部件的厚度。
发明内容
以下发明内容标识了本公开的各种特征和方面，并且不旨在作为所公开的主题的排他性描述或详尽描述。在具体实施方式和所附权利要求中可以找到附加特征和其他细节。包括在发明内容中并不反映重要性。在阅读以下具体实施方式并查看形成其一部分的附图时，其他方面对于本领域技术人员而言变得显而易见。
在一个方面中，一种无电极无源部件嵌入电子组件的多层衬底的腔中。该电子组件包括多层衬底，该多层衬底在电介质中具有多个金属层。无电极无源部件嵌入多层衬底的腔中。腔具有形成在腔的至少两个侧壁上的导电元件，并且导电元件被配置为电耦合到无电极无源部件。
在另一方面中，一种形成电子组件的方法包括：基于腔图案来在多层衬底中形成腔。无电极无源部件嵌入腔中。导电元件形成在腔的至少两个侧壁上并且电耦合到无电极无源部件。
基于附图和具体实施方式，与本文中所公开的各方面相关联的其他目的和优点对于本领域技术人员而言是显而易见的。
附图说明
提供附图以帮助描述本公开的实施例并且仅提供用于说明所公开的各个方面而不是对其进行限制。
图1A是示例传统无源部件的图示。
图1B是示例传统无源部件的备选视图。
图2是根据本公开的一个方面的电子组件的图示。
图3是根据本公开的一个方面的电子组件的图示。
图4是根据本公开的一个方面的电子组件的另一图示。
图5示出了根据本公开的各方面的一些示例的可以包括一个或多个设备的设备的一个示例功能示意图。
图6A描绘了根据本公开的一个方面的形成电子组件的示例过程的一部分。
图6B描绘了根据本公开的至少一个方面的形成电子组件的示例过程的另一部分。
图6C描绘了根据本公开的一个方面的形成电子组件的示例过程的另一部分。
图6D描绘了根据本公开的至少一个方面的形成电子组件的示例过程的另一部分。
图6E描绘了根据本公开的至少一个方面的形成电子组件的示例过程的另一部分。
图6F描绘了根据本公开的至少一个方面的形成电子组件的示例过程的另一部分。
图6G描绘了根据本公开的至少一个方面的形成电子组件的示例过程的另一部分。
图6H描绘了根据本公开的至少一个方面的形成电子组件的示例过程的另一部分。
图6I描绘了根据本公开的至少一个方面的形成电子组件的示例过程的另一部分。
图6J描绘了根据本公开的至少一个方面的形成电子组件的示例过程的另一部分。
图6K描绘了根据本公开的至少一个方面的形成电子组件的示例过程的另一部分。
图7图示了根据本公开的至少一个方面的用于形成电子组件的示例性方法。
图8示出了根据本公开的至少一个方面的用于进一步形成电子组件/封装的示例性方法。
具体实施方式
在针对特定实施例的以下描述和相关附图中对本公开的各方面进行说明。在没有背离本文中所教导的范围的情况下，可以设想备选方面或实施例。附加地，本文中的说明性实施例的众所周知的元素可能不会被详细描述或可能被省略以免混淆本公开中的教导的相关细节。
在所描述的某些示例实现方式中，标识各种部件结构和操作部分可以取自已知传统技术，然后根据一个或多个示例性实施例布置的实例。在这些实例中，可以省略已知传统部件结构和/或操作部分的内部细节，以帮助避免对本文中所公开的说明性实施例中所说明的概念的潜在混淆。
本文中所使用的术语仅出于描述特定实施例的目的，并不旨在进行限制。如本文中所使用的，除非上下文另有明确说明，否则单数形式“一”、“一个”和“该”也旨在包括复数形式。还应当理解，术语“包括(comprises)”、“包括(comprising)”、“包含(includes)”和/或“包含(including)”当在本文中使用时，指定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除存在或添加一个或多个其他特征、整数、步骤、操作、元件、部件和/或它们的组。
图1A是示例传统无源部件100的图示。描绘了无源部件100(在该图示中，为陶瓷电容器)的示意性图像的侧视图/横截面视图。无源部件100具有两个电极110以及位于电极110之间的本体120(在这种情况下，为多层陶瓷电容器)。如所图示的，可以看出电极110显著增加了无源部件100的厚度。电极110增加了无源部件100的总厚度的大约三分之一。附加地，提供了基于无源部件100的实际图像的俯视图，其图示了两个电极110和本体120。
图1B是示例无源部件100的另一图示。无源部件100的示意图的类似侧视图/横截面视图提供有电极110的附加细节。如所图示的，电极110形成为具有内层114和外层112。内层114可以通过铜(Cu)浆料浸渍然后高温烧制或其他已知技术形成。外层112可以由镀锡或镀镍(例如，用于表面贴装技术SMT/SMD)或用于嵌入式部件的铜形成。无源部件100的角部部分130以详细横截面视图的形式提供，该详细横截面视图基于显示具有围绕本体120形成的电极110的外层112和内层114的实际设备的图像来提供。同样，无源部件100的较大部分140以详细横截面图像示出，该详细横截面图像示出了具有围绕本体120形成的电极110的实际设备，以提供无源部件100的相关部分的一些比例透视图。
图2是根据本公开的一个方面的电子组件200的图示。如所图示的，电子组件200包括多层衬底210，该多层衬底210具有多个金属层212和可以由一个或多个电介质材料层形成的电介质204。应当理解，多层衬底210可以为封装衬底并且可以为封装的一部分，该封装包括设置在管芯周围的保护本体，从而允许其安全处置和安装。例如，封装衬底可以被配置为将管芯电气互连到布线板和/或分配功率。在另一示例中，多层衬底210可以为中介层，用作用于在不同连接配置之间进行连接的电气接口。在一些方面中，多层衬底210具有芯。在其他方面中，多层衬底210为无芯衬底(例如，无芯嵌入式迹线衬底(ETS))，这进一步减小了多层衬底210的厚度和嵌入式部件的可用厚度。无电极无源部件220可以嵌入多层衬底210的腔218中。在一个实施例中，多层衬底210可以在多层衬底210的层内不包括有源设备(例如，晶体管)。例如，如所图示的，无电极无源部件220为多层陶瓷电容器(MLCC)。应当领会，本文中所公开的各个方面还可以与其他类型的无源部件一起使用。如本文中所使用的，术语无电极无源部件表示形成为没有用于外部连接的电极的无源部件，诸如上文所图示和讨论的MLCC。腔218(由其包含的元件限定)具有形成在腔218的至少两个侧壁上的导电元件214(例如，金属或导电膏)。导电元件214电耦合到无电极无源部件220。在这种配置中，无电极无源部件220位于多层衬底210的多个金属层中的第一金属层中，该无电极无源部件220与多层衬底210的外部表面相邻。附加地，粘合剂216可以设置在腔218的底部中，以稳固无电极无源部件220。粘合剂的厚度的量级可能为5um至10um。应当领会，所图示的配置具有位于顶部金属层(M1)中与电耦合到管芯230的表面相邻的无电极无源部件220。在所图示的配置中，无电极无源部件220位于管芯230的正下方以允许无电极无源部件220与管芯230之间的短连接长度。进一步地，导电元件214中的每个导电元件214直接耦合到管芯230的至少一个管芯凸块232以允许直接电耦合到无电极无源部件220。管芯凸块232可以由铜、焊料、其他导电材料和/或它们的组合形成。附加地，应当领会，腔218、无电极无源部件220和导电元件214可替代地或附加地与多层衬底210的底部表面(例如，着陆侧)相邻定位在底部金属层上。
多个金属层212可以包括第一金属层202、第二金属层206和第三金属层208。电介质材料可以用于形成一个或多个电介质层，该一个或多个电介质层被描绘为公共元件并且本文中被称为电介质204。除了多个金属层212之外，导电过孔207可以通过电介质204形成以允许第一金属层202和第二金属层206之间电耦合。导电过孔209可以通过电介质204形成以允许第二金属层206与第三金属层208之间电耦合。一个或多个电极224可以电耦合到第三金属层208(在该配置中为底部金属层)。一个或多个电极224可以用作与一个或多个外部连接点226的耦合点。例如，一个或多个电极224可以用作一个或多个外部连接点226的焊球焊盘，该一个或多个电极图示为焊球。组合过孔207和209允许第一金属层202与第三金属层208之间并且最终允许管芯230与一个或多个外部连接点226之间电耦合。应当领会，根据本文中所公开的各个方面，可以包括更多或更少个金属层。进一步地，各种金属层图案、过孔、外部连接和类似元件的图示仅仅是示例性的并且不旨在限制本文中所公开的各个方面。
图3是根据本公开的一个方面的电子组件300的图示。如所图示的，电子组件300与图2所图示的各方面相似，所以为了避免冗余，并非对所有元件都会进行详述。电子组件300包括具有多个金属层的多层衬底310(包括例如封装衬底或中介层)。无电极无源部件320嵌入多层衬底310的腔中。腔具有形成在腔的至少两个侧壁上的导电元件。导电元件电耦合到无电极无源部件320。在这种配置中，无电极无源部件320也与电耦合到管芯330的表面相邻定位在顶部金属层(M1)中。进一步地，如所描绘的，无电极无源部件320位于管芯330的正下方，以允许无电极无源部件320与管芯330之间的短连接长度。然而，在这种配置中，无电极无源部件320偏离管芯330的中心定位。附加地，图3描绘了封装管芯330的至少一部分和多个管芯凸块332的底部填充物或模塑料350。管芯凸块332被图示为焊球，该管芯凸块332可以为球栅阵列(BGA)的一部分，而且还可以为着陆栅阵列(LGA)焊盘或铜、焊料、其他导电材料和/或它们的组合。同样，外部连接点326被图示为焊球，该外部连接点326可以是球栅阵列(BGA)的一部分，而且还可以为着陆栅阵列(LGA)焊盘或任何其他合适的连接类型。外部连接点326位于多层衬底310的着陆侧/底部上，以允许电子组件300的外部电连接和安装。
图4是根据本公开的一个方面的电子组件400的另一图示。如所图示的，电子组件400与图3中图示的各方面相似，所以为了避免冗余，并非对所有元件都会进行详述。电子组件400包括具有多个金属层的多层衬底410(包括例如封装衬底或中介层)。具有底部填充物或模塑料450的管芯430封装管芯430的至少一部分和多个管芯凸块432。无电极无源部件420嵌入多层衬底410的腔中。在这种配置中，腔和无电极无源部件420也与多层衬底410的底部表面(例如，着陆侧)和多个外部连接点426(被图示为焊球)相邻地定位在底部金属层中，多个外部连接点426附接到多层衬底410的着陆侧/底部以允许电子组件400的外部电连接和安装。
根据前述说明，应当领会，嵌入式无电极无源部件的位置不限于多层衬底中的任何特定位置。附加地，尽管上文中仅图示了一个嵌入式无电极无源部件，但是应当领会，在其他方面中多于一个的无电极无源部件可以嵌入在单个多层衬底中。因而，应当领会，本文中所提供的各种说明仅用于提供用于解释所公开的各个方面的示例，而不应被解释为限制本公开。
图5图示了根据本公开的一个或多个方面(例如，参考图2至图4中的任一个或多个附图所描述的方面)的示例性通信系统500。为了说明的目的，图5示出了三个远程单元520、530和550以及两个基站540。应当认识，传统无线通信系统可以具有更多个远程单元和基站。远程单元520、530和550分别包括集成电路或其他半导体设备525、535和555，该集成电路或其他半导体设备525、535和555具有根据如参考图2至图4中的任一个或多个附图所要求保护或描述的所公开的示例性方面中的一个或多个示例性方面的一个或多个电子组件(例如，200、300、400)。图5示出了来自基站540和远程单元520、530和550的前向链路信号580以及从远程单元520、530和550到基站540的反向链路信号590。
在图5中，远程单元520被示为移动电话，远程单元530被示为便携式计算机，并且远程单元550被示为无线本地环路系统中的固定位置远程单元。这些只是数量和类型两方面的示例。例如，远程单元520、530和550可以为以下各项中的一项或任何组合：移动电话、手持式个人通信系统(PCS)单元、诸如个人数据助理(PDA)之类的便携式数据单元、导航设备(诸如GPS使能设备)、机顶盒、音乐播放器、视频播放器、娱乐单元、固定位置数据单元(诸如抄表设备)或存储或检索数据或计算机指令的任何其他设备或其任何组合。尽管图5图示了根据本公开的各方面的远程单元520、530和550，但是本公开不限于这些示例性图示单元。本公开的各方面可以适当地用于具有如本文中所公开的电子组件的任何设备中。本领域技术人员将领会，本公开的各方面可以并入集成设备中，诸如移动电话，该集成设备并入RF(射频)通信以便分离不同频率的RF信号频带。
例如，本文中所公开的电子组件(例如，200、300、400)可以并入设备中，该设备可以包括音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、移动设备、移动电话、智能手机、个人数字助理、固定位置终端、平板计算机、计算机、可穿戴式设备、笔记本计算机、服务器或机动车辆中的设备。进一步地，应当领会，本公开的各方面可以用于广泛多种设备并且不限于本文中所提供的具体示例。
图6A至图6K图示了用于形成本文中所公开的电子组件的示例工艺流程。图6A至图6K中所示的元件为了概念目的而被简化并且不旨在表示如本文中所公开的各个方面中所设想的元件的尺寸、比例或数目。
图6A描绘了具有载体箔层603的载体601，该载体601可以为铜或其他导电材料。针对正在实现的特定设计，可以对第一金属层602进行图案化。第一金属层602的一部分可用于形成腔图案611。应当领会，本文中所提供的图示仅用于提供基本制造技术的示例以解释所公开的各个方面。它不旨在详尽列举所有工艺细节和潜在可选制造技术，也不旨在将本文中所公开的方面限制为这些说明。进一步地，为了避免不必要的冗余，并非对每个附图所介绍或图示的所有元件都会进行详述。
图6B描绘了进一步限定腔图案611的附加镀覆工艺(例如，一个或多个附加时间)。附加镀覆工艺将腔图案611延伸到第一金属层602之外，以允许形成腔的期望深度。应当领会，腔的维度基于嵌入腔中的无电极无源部件的维度。应当领会，具有载体箔层603的载体601仍可以附接到第一金属层602以在制造工艺的至少一部分期间提供支撑。
图6C描绘了施加到包括腔图案611的第一金属层602的电介质604。例如，电介质材料可以层压到包括腔图案611的第一金属层602。进一步地，第二金属箔层605可以层压在电介质604上。第二金属箔层605可以为铜或其他导电材料。应当领会，具有载体箔层603的载体601仍可以附接到第一金属层602以在制造工艺的至少这部分期间提供支撑。
图6D描绘了可以被图案化以形成第二金属层606的第二金属箔层605。附加地，可以形成穿过电介质604的导电过孔607以将第一金属层602的各部分连接到第二金属层606的各部分。应当领会，具有载体箔层603的载体601仍可以附接到第一金属层602以在制造工艺的至少这部分期间提供支撑。
图6E描绘了另一层压工艺，由于存在不存在电介质材料分离的部分并且在一些实施例中该材料可以熔合或粘合在一起，所以该层压工艺可以包括覆盖第二金属层606和现有电介质材料以形成电介质604的附加电介质材料，该附加电介质材料被描绘为共同元件。除了导电过孔607之外，还可以形成穿过电介质604的导电过孔609，以将第二金属层606的各部分连接到第三金属层608的各部分，第三金属层608可以如上文关于第二金属层606所讨论的那样形成。导电过孔607允许第一金属层602(包括腔图案611)电耦合到第二金属层606，并且导电过孔609允许第二金属层606电耦合到第三金属层608。组合导电过孔607和609允许第一金属层602与第三金属层608之间电耦合。应当领会，根据本文中所公开的各个方面，可以包括更多或更少个金属层。进一步地，各种图案和过孔的图示仅是举例，并不旨在限制本文中所公开的各个方面。附加地，应当领会，具有载体箔层603的载体601仍可以附接到第一金属层602以在制造工艺的至少这部分期间提供支撑。
图6F描绘了从第一金属层602移除具有载体箔层603的载体601。还可以蚀刻第一金属层602以移除多余金属以允许完成图案化。在移除载体601和载体箔层60之后剩余的多层衬底610具有可以由一个或多个电介质层和多个金属层612形成的电介质604(例如，玻璃、预浸材料(PPG)等)。如上文所描述的，多层衬底610可以具有芯或为无芯的，并且在一些方面中为无芯嵌入式迹线衬底(ETS)。多层衬底610可以使用后镀覆进行图案化以形成用于耦合管芯和外部连接(例如，焊球、球栅阵列(BGA)等)的各种连接焊盘。附加地，应当领会，第一金属层602形成腔图案611的至少一个部分，该至少一个部分还可以进行镀覆以获得腔的期望维度，如上文所讨论的。
图6G描绘了多层衬底610，该多层衬底610可以具有掩模625，施加该掩模625以允许蚀刻多层衬底610(例如，上文所讨论的腔图案611)以形成腔618。掩模625提供对多层衬底610的顶部的保护，该多层衬底610包括第一金属层602(在本文中也称为顶部金属层(M1))。附加地，应当领会，可以使用形成腔618的其他技术。
图6H描绘了具有嵌入腔618中的无电极无源部件620的多层衬底610。在该图示中，无电极无源部件620至少部分位于与多层衬底610的外部表面(即，顶部侧/管芯侧)相邻的多层衬底610的第一金属层602部分中。应当领会，腔618和无电极无源部件620的位置不限于第一金属层602并且可以位于多层衬底610中的任何期望位置处。作为嵌入工艺的一部分，可以在腔618的底部中提供粘合剂616以在进一步处理期间稳固无电极无源部件620。此外，应当指出，在将无电极无源部件620设置在腔618中时，在腔618的至少两个侧壁与无电极无源部件620之间形成间隙619。
图6I描绘了多层衬底610，该多层衬底610具有嵌入多层衬底610中的无电极无源部件620，具体地，多层衬底610的电介质604(例如，PPG)。在该图示中，由粘合剂616稳固的无电极无源部件620具有导电元件614，该导电元件614形成在腔618的至少两个侧壁上。导电元件614可以通过使用导电材料填充腔的至少两个侧壁与无电极无源之间的间隙(例如，其中间隙在图6H中)来形成。例如，可以通过使用铜进行镀覆(导电材料)来填充间隙。可替代地，间隙可以由焊膏填充，该焊膏也是导电材料。
图6J描绘了将电极624添加到多层衬底610。电极624可以用于连接到多层衬底610的着陆侧上的外部连接点(例如，焊球)(例如焊球焊盘或其他电触点)。
图6K描绘了可以使用传统技术电耦合到多层衬底610的顶部侧的管芯630。附加地，多个外部连接点626可以电耦合到多层衬底610的与管芯相对的着陆侧/底部。在一些方面中，外部连接点为焊球。如上文所指出的，无电极无源部件620可以位于多层衬底610的任何期望部分中。然而，在本文中所公开的一些方面中，导电元件614中的每个导电元件直接耦合到管芯的至少一个管芯凸块632以允许直接电耦合到无电极无源组件620。这允许管芯与无电极无源组件620之间的信号路径比在具有位于多层衬底610的外部表面上的无源SMD的传统配置中实现的信号路径短得多。
应当领会，根据本文中所公开的各方面，存在用于形成电子组件的各种方法，该电子组件可以包括多层衬底并且还可以包括管芯和用于形成电子封装的合适连接器。图7是图示了根据本文中所公开的至少一个方面的示例方法700的流程图。例如，框710包括：基于腔图案来在多层衬底中形成腔。例如，如上文所讨论的，可以遮蔽多层衬底并且可以蚀刻腔图案，从而形成腔。如上文所讨论的，腔图案可以部分由金属层中的一个金属层形成，然后可以提供附加镀覆以实现腔的期望维度。框720包括：将无电极无源部件嵌入腔中。如上文所指出的，无电极无源部件可以与多层衬底的外部表面相邻定位在第一金属层处，定位底部金属层处或多层衬底的任何其他部分处。框730包括：在腔的至少两个侧壁上形成导电元件，这些导电元件电耦合到无电极无源部件。
图8是进一步图示了进一步形成电子组件的示例方法800的流程图。例如，框810包括：将管芯电耦合到多层衬底的顶部侧。框820包括：将多个外部连接点电耦合到多层衬底的与管芯相对的着陆侧。框830包括：沉积模具材料以覆盖管芯的至少一部分和多层衬底的相邻部分。
根据前述公开内容，应当领会，用于制造本文中所公开的各个方面的附加工艺对于本领域技术人员而言是显而易见的，并且上文所讨论和所附附图中图示的工艺的所有变型的字面再现实非必要。
前述公开的设备和功能(例如，如参考图2至图6K中的任一个或多个附图所描述的设备和功能)可以被设计和配置到存储在计算机可读介质上的计算机文件(例如，RTL、GDSII、GERBER等)中。一些或所有这些文件可以提供给基于这些文件来制造设备的制造处理者。所得产品可能包括半导体晶片，这些半导体晶片然后被切割成半导体管芯并且封装成半导体芯片。然后，可以在如上文所描述的设备中采用这些芯片。
结合本文中所公开的实施例描述的方法、序列和/或算法可以直接体现在硬件中、由处理器执行的软件模块中或两者的组合中。软件模块可以驻留在RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移除磁盘、CD-ROM或本领域已知的任何其他形式的存储介质中。示例性存储介质耦合到处理器，使得处理器可以从存储介质读取信息和将信息写入存储介质。在备选方案中，存储介质可以集成到处理器中。
因而，本文中所公开的实施例可以包括体现用于制造本文中所公开的各种电子组件的方法的非暂态计算机可读介质。因而，由于用于执行本文中所描述的功能的任何装置都为本公开所设想，所以本公开不限于所图示的示例。
虽然前述公开示出了各种说明性实施例，但应当指出，在没有背离如所附权利要求所限定的本公开的教导的范围的情况下，可以在本文中进行各种改变和修改。举例标识和说明的各种材料可以由已知等同物或备选材料代替。上文所讨论的示例制造工艺可以具有组合或拆分成附加工艺操作的各种工艺操作。附加地，根据本文中所描述的本公开的实施例的方法权利要求中描述的功能、步骤和/或动作无需按任何特定次序执行。进一步地，尽管本公开的元件可以以单数形式描述或要求保护，但是除非明确说明对单数的限制，否则还可以设想复数。

Claims (30)

1.一种电子组件，包括：
多层衬底，在电介质中具有多个金属层；以及
无电极无源部件，嵌入所述多层衬底的腔中，其中所述腔具有形成在所述腔的至少两个侧壁上的导电元件，并且其中所述导电元件被配置为电耦合到所述无电极无源部件。
2.根据权利要求1所述的电子组件，其中所述无电极无源部件与所述多层衬底的外部表面相邻地定位在第一金属层中。
3.根据权利要求2所述的电子组件，其中所述外部表面被配置为耦合到管芯，并且所述第一金属层为所述多层衬底的顶部金属层。
4.根据权利要求2所述的电子组件，其中所述外部表面位于着陆侧上，并且所述第一金属层为底部金属层。
5.根据权利要求2所述的电子组件，还包括：
管芯，电耦合到所述多层衬底的所述外部表面。
6.根据权利要求5所述的电子组件，其中所述无电极无源部件位于所述管芯的正下方。
7.根据权利要求6所述的电子组件，其中所述导电元件中的每个导电元件直接耦合到所述管芯的多个管芯凸块中的至少一个管芯凸块，以允许直接电耦合到所述无电极无源部件。
8.根据权利要求7所述的电子组件，还包括底部填充物，所述底部填充物包封所述管芯的至少一部分和所述多个管芯凸块。
9.根据权利要求5所述的电子组件，还包括：
多个外部连接点，电耦合到所述多层衬底的与所述管芯相对的着陆侧。
10.根据权利要求9所述的电子组件，其中所述多个外部连接点为焊球。
11.根据权利要求1所述的电子组件，还包括：
粘合剂，位于所述腔的底部中以将所述无电极无源部件粘附在所述腔中。
12.根据权利要求1所述的电子组件，其中所述多层衬底为无芯嵌入式迹线衬底(ETS)。
13.根据权利要求1所述的电子组件，其中所述无电极无源部件为多层陶瓷电容器(MLCC)。
14.根据权利要求1所述的电子组件，其中所述电子组件并入选自由以下各项组成的组的设备中：音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、移动设备、移动手机、智能手机、个人数字助理、固定位置终端、平板计算机、计算机、可穿戴式设备、膝上型计算机、服务器、以及机动车辆中的部件。
15.一种形成电子组件的方法，包括：
基于腔图案来在多层衬底中形成腔；
在所述腔中嵌入无电极无源部件；以及
在所述腔的至少两个侧壁上形成导电元件，所述导电元件电耦合到所述无电极无源部件。
16.根据权利要求15所述的方法，其中形成所述腔包括：
遮蔽所述多层衬底；以及
蚀刻所述腔图案以形成所述腔。
17.根据权利要求15所述的方法，其中形成所述腔图案包括：
在第一金属层中形成所述腔图案的一部分；以及
对所述部分执行一个或多个镀覆操作以形成所述腔图案。
18.根据权利要求15所述的方法，其中形成所述导电元件包括：
使用导电材料填充所述腔的所述至少两个侧壁与所述无电极无源部件之间的间隙。
19.根据权利要求18所述的方法，其中所述间隙通过镀覆填充并且所述导电材料为铜。
20.根据权利要求18所述的方法，其中所述间隙由焊膏填充。
21.根据权利要求15所述的方法，还包括：
将管芯电耦合到所述多层衬底的顶部侧，其中所述无电极无源部件与所述多层衬底的外部表面相邻地定位在第一金属层中。
22.根据权利要求21所述的方法，还包括：
将多个外部连接点电耦合到所述多层衬底的着陆侧，所述着陆侧位于所述多层衬底的与所述管芯相对的一侧上。
23.根据权利要求22所述的方法，其中所述多个外部连接点为焊球。
24.根据权利要求22所述的方法，其中所述外部表面位于所述着陆侧上并且所述第一金属层为底部金属层。
25.根据权利要求21所述的方法，其中所述外部表面与所述管芯相邻并且所述第一金属层为所述多层衬底的顶部金属层。
26.根据权利要求21所述的方法，其中所述无电极无源部件位于所述管芯的正下方。
27.根据权利要求26所述的方法，其中所述导电元件中的每个导电元件直接耦合到所述管芯的至少一个凸块以允许直接电耦合到所述无电极无源部件。
28.根据权利要求15所述的方法，其中所述无电极无源部件为多层陶瓷电容器(MLCC)。
29.根据权利要求15所述的方法，其中所述多层衬底为无芯嵌入式迹线衬底(ETS)。
30.根据权利要求15所述的方法，还包括：
在所述腔的底部提供粘合剂以将所述无电极无源部件粘附在所述腔中。
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