CN114267646A - 半导体存储装置 - Google Patents

半导体存储装置 Download PDF

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Publication number
CN114267646A
CN114267646A CN202110927715.1A CN202110927715A CN114267646A CN 114267646 A CN114267646 A CN 114267646A CN 202110927715 A CN202110927715 A CN 202110927715A CN 114267646 A CN114267646 A CN 114267646A
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China
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semiconductor chip
semiconductor
pad
notch
memory device
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CN202110927715.1A
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English (en)
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井户道雄
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Kioxia Corp
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Kioxia Corp
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Abstract

本发明的一个实施方式提供能够将半导体芯片进一步高集成化的半导体存储装置。一个实施方式的半导体存储装置具备基板、第1半导体芯片及第2半导体芯片。第1半导体芯片具有与基板相接的第1面、第1面的相反侧的第2面及设置于第2面的第1焊盘。第2半导体芯片具有与第2面相接的第3面、第3面的相反侧的第4面及缺口部。缺口部设置于处于第3面与第4面之间的侧面和第3面交叉的角部。缺口部在从第4面的上方观察时与第1焊盘的至少一部分重叠。

Description

半导体存储装置
本申请享受以日本专利申请2020-155713号(申请日：2020年9月16日)为基础申请的优先权。本申请通过参照该基础申请而包括基础申请的全部内容。
技术领域
本实施方式涉及半导体存储装置。
背景技术
在NAND型EEPROM(Electrically Erasable Programmable Read-Only Memory：电可擦可编程只读存储器)等这样的半导体存储装置中，多个存储器芯片层叠在基板上。层叠的存储器芯片与基板之间由金属引线键合。另外，在半导体存储装置中，期望存储器芯片的高集成化。
发明内容
本发明的一个实施方式提供一种能够将半导体芯片进一步高集成化的半导体存储装置。
一个实施方式的半导体存储装置具备基板、第1半导体芯片及第2半导体芯片。第1半导体芯片具有与基板相接的第1面、第1面的相反侧的第2面及设置于第2面的第1焊盘。第2半导体芯片具有与第2面相接的第3面、第3面的相反侧的第4面及缺口部。缺口部设置于处于第3面与第4面之间的侧面与第3面交叉的角部。缺口部在从第4面的上方观察时与第1焊盘的至少一部分重叠。
附图说明
图1是示出第1实施方式的半导体存储装置的结构的一例的半导体存储装置的剖视图。
图2是示出第1实施方式的半导体存储装置的结构的一例的半导体存储装置的放大剖视图。
图3是示出第1实施方式的半导体存储装置的结构的配置的一例的半导体存储装置的俯视图。
图4是示出第1实施方式的半导体晶片的单片化方法的一例的剖视图。
图5是示出第1实施方式的半导体芯片的加工方法的一例的剖视图。
图6是示出第1比较例的半导体存储装置的结构的一例的半导体存储装置的剖视图。
图7是示出第2比较例的半导体存储装置的结构的一例的半导体存储装置的剖视图。
标号说明
1 半导体存储装置
1a 半导体存储装置
1b 半导体存储装置
11 布线基板
111 布线
112 树脂层
113 树脂层
114 焊盘
115 焊盘
23 树脂
30 粘接层群
31 粘接层
32 粘接层
33 粘接层
40 粘接层
B 金属凸块
C 缺口部
CD 缺口深度
CF 缺口面
CH1 半导体芯片群
CH11～CH16 半导体芯片
CH2 半导体芯片
CHs 边
D 虚线框
DB 划片刀
F1～F6 面
FS 侧面
L 距离
L1 布线层
L2 布线层
L3 布线层
O 偏移量
P1 焊盘群
P11～P16 焊盘
P2 焊盘
PB 加工用刀
W 半导体晶片
W1 引线群
W11 引线
W12 引线
W13 引线
具体实施方式
以下，参照附图来说明本发明的实施方式。在以下的实施方式中，基板的上下方向表示将设置半导体芯片的面设为上的情况下的相对方向。附图是示意性或概念性的。在说明书和附图中，对同样的要素标注同一标号。
(第1实施方式)
图1是示出第1实施方式的半导体存储装置1的结构的一例的半导体存储装置1的剖视图。半导体存储装置1具备布线基板11、粘接层群30、粘接层40、半导体芯片群CH1、半导体芯片CH2、引线群W1、引线W2、树脂23及金属凸块B。
布线基板11例如是印制基板等基板。布线基板11也可以是硅基板。布线基板11能够经由引线群W1及引线W2而分别与半导体芯片群CH1及半导体芯片CH2连接。
粘接层群30包括多个粘接层。粘接层群30所包含的粘接层及粘接层40例如是膜状的树脂(DAF，Die Attach Film)。粘接层群30及粘接层40设置于布线基板11的上方。在图1所示的例子中，粘接层群30包括多个粘接层31、32、33。
半导体芯片群CH1是将多个半导体芯片重叠并粘接而得到的。即，半导体芯片群CH1具有层叠构造。半导体芯片群CH1的层叠数根据存储器容量而设定。半导体芯片群CH1通过粘接层群30而粘接于布线基板11上。
半导体芯片CH2例如是控制器芯片。半导体芯片CH2与半导体芯片群CH1电连接而控制半导体芯片群CH1的工作。半导体芯片CH2例如如图1所示，与半导体芯片群CH1相邻地设置，通过粘接层40而粘接于布线基板11。另外，半导体芯片CH2例如也可以设置于半导体芯片群CH1的上方。另外，半导体芯片CH2具有用于与引线W2连接的焊盘P2。
引线群W1将布线基板11和半导体芯片群CH1电连接。在引线群W1中包括多个引线。包含于引线群W1的引线的材料例如是金、银或铜等导电性金属。
引线W2将布线基板11和半导体芯片CH2电连接。引线W2的材料例如是金、银或铜等导电性金属。
树脂23例如是环氧树脂。树脂23将半导体芯片群CH1、半导体芯片CH2、引线群W1及引线W2在布线基板11的上表面处密封。由此，树脂23保护半导体芯片群CH1、半导体芯片CH2、引线群W1及引线W2免受来自外部的冲击、外部气体的影响。
金属凸块B例如是焊料球。金属凸块B将半导体存储装置1与外部的安装基板等(未图示)电连接。金属凸块B的材料是焊料等导电性金属。金属凸块B设置于布线基板11的下表面。金属凸块B连接于布线层L3。
接着，对布线基板11的内部结构进行说明。布线基板11具有布线111和树脂层112、113。
布线111将布线基板11的上表面的电极焊盘(焊盘114、115)与布线基板11的下表面的金属凸块B电连接。布线111的材料例如是铜或钨等导电性金属。布线111包括层叠的多个布线层L1、L2、L3。多个布线层L1、L2、L3之间通过树脂层113而绝缘。另外，多个布线层L1、L2、L3例如也可以通过过孔(via hole)而在一部分处电连接。焊盘114、115例如是布线层L1的一部分。
树脂层112例如是阻焊剂等绝缘材料。树脂层113例如是预浸材料。树脂层113例如是玻璃布等纤维状加强材料与环氧树脂等热固性树脂的复合材料。树脂层113与树脂层112相比强度及刚性高。
接着，对半导体芯片群CH1的内部结构进行说明。例如，如图1所示，半导体芯片群CH1包括多个半导体芯片CH11、CH12、CH13。
多个半导体芯片CH11、CH12、CH13例如是存储器芯片。多个半导体芯片CH11、CH12、CH13例如是NAND芯片。多个半导体芯片CH11、CH12、CH13例如是同一构造。半导体芯片CH11经由粘接层31而粘接于布线基板11上。半导体芯片CH12经由粘接层32而粘接于半导体芯片CH11上。半导体芯片CH13经由粘接层33而粘接于半导体芯片CH12上。多个半导体芯片CH11、CH12、CH13例如包括半导体元件。半导体元件例如是存储单元阵列或CMOS电路(Complementary Metal-Oxide-Semiconductor circuit：互补金属氧化物半导体电路)。
图2是示出第1实施方式的半导体存储装置的结构的一例的半导体存储装置1的放大剖视图。图2也是图1的虚线框D的放大图。此外，在图2中，树脂23被省略。
半导体芯片CH11具有面F1、面F2及焊盘P11。面F1是布线基板11侧的面。面F2是面F1的相反侧的面。焊盘P11是半导体芯片CH11的布线的一部分。焊盘P11设置于面F2上。半导体芯片CH11在面F1侧经由粘接层31而与布线基板11粘接。半导体芯片CH11是最下层的芯片。
半导体芯片CH12具有面F3、面F4、焊盘P12及半导体基板。面F3是布线基板11侧的面。面F4是面F3的相反侧的面。焊盘P12是半导体芯片CH12的布线的一部分。焊盘P12设置于面F4上。另外，在图2所示的例子中，焊盘P12以在从面F4的上方观察时焊盘P12的一部分与焊盘P11重叠的方式配置。半导体基板例如是硅基板。在半导体基板上设置半导体元件。半导体基板配置于半导体芯片CH12的面F3侧。另外，半导体芯片CH12在面F3侧经由粘接层32而与半导体芯片CH11的面F2粘接。另外，半导体芯片CH12以在从上方观察时与焊盘P11的至少一部分重叠的方式与半导体芯片CH11粘接。半导体芯片CH12以在从上方观察时中心位置与半导体芯片CH11的中心位置大致一致的方式配置。半导体芯片CH12配置于半导体芯片CH11的正上方。
半导体芯片CH13具有面F5、面F6及焊盘P13。面F5是布线基板11侧的面。面F6是面F5的相反侧的面。焊盘P13是半导体芯片CH13的布线的一部分。焊盘P13设置于面F6上。另外，半导体芯片CH13在面F5侧经由粘接层33而与半导体芯片CH12的面F4粘接。另外，半导体芯片CH13以在从上方观察时与焊盘P12的至少一部分重叠的方式与半导体芯片CH12粘接。半导体芯片CH13以在从上方观察时中心位置与半导体芯片CH12的中心位置大致一致的方式配置。半导体芯片CH13配置于半导体芯片CH12的正上方。
这样，在半导体芯片CH12的上方层叠与半导体芯片CH12同一结构的半导体芯片CH13。此外，在半导体芯片被层叠4层以上的情况下，也可以在半导体芯片CH13的上方反复层叠与半导体芯片CH12同一结构的半导体芯片。
接着，对引线群W1的内部结构进行说明。如图2所示，引线群W1包括引线W11、W12、W13。引线W11与设置于半导体芯片CH11的焊盘P11及设置于布线基板11的焊盘114电连接。同样，引线W12与设置于半导体芯片CH12的焊盘P12及焊盘114电连接。引线W13与设置于半导体芯片CH13的焊盘P13及焊盘114电连接。
引线W11例如以从焊盘P11向上方立起的方式设置。另外，引线W11以形成顶点的方式向下方延伸。向下方延伸的引线W11与图1所示的布线基板11的焊盘114连接。这样，半导体芯片CH11的焊盘P11与从布线基板11延伸的引线W11电连接。
接着，对缺口部C进行说明。
半导体芯片CH12在面F3的外周部具有缺口部C。面F3的外周部是处于面F3与面F4之间的侧面FS和面F3交叉的角部。缺口部C也是设置于半导体芯片CH12的侧面FS的下部的凹部。缺口部C以与焊盘P11相对向的方式设置。
另外，更详细而言，缺口部C以使引线W11和半导体芯片CH12的缺口面CF分离的方式设置。缺口面CF是通过形成缺口部C而露出的半导体芯片CH12的面。缺口面CF位于引线W11中的弯曲成形成顶点的部分的旁边。通过缺口部C，能够使引线W11不与半导体芯片CH12接触。由此，能够抑制由接触引起的引线W11及半导体芯片CH12的损伤。其结果，能够抑制半导体存储装置1的可靠性的下降。
另外，更详细而言，缺口部C以从面F3的中心部侧到外周部侧缺口深度CD逐渐变大的方式设置。缺口深度CD是相对于面F3的缺口部C的深度。在图2所示的例子中，缺口部C以使缺口面CF相对于面F3的倾斜角大致恒定的方式设置。即，缺口面CF是倾斜角大致恒定的平面。
另外，缺口部C设置于半导体芯片CH12的半导体基板。缺口部C设置于半导体芯片CH12内的比设置半导体元件的区域靠下方处。表示半导体芯片CH12中的最薄的部分的厚度的距离L优选为半导体元件的厚度以上。对于距离L，也可以根据需要而加上余裕。这是为了能够抑制因缺口部C的形成而可能产生的对半导体元件的损伤。其结果，能够使半导体芯片CH12的工作的可靠性提高。半导体元件的厚度例如为约10μm。
另外，在某半导体芯片内，优选在缺口部的大致正上方设置焊盘。在图2所示的例子中，焊盘P12以在从面F4的上方观察时焊盘P12的一部分与缺口部C重叠的方式配置。在焊盘P12的周边例如设置保护元件等。
另外，例如，在半导体芯片CH13也设置缺口部。半导体芯片CH13的缺口部的配置及形状等，例如与半导体芯片CH12的缺口部C相同。
另外，例如，在最下层的半导体芯片CH11不设置缺口部。由此，从对半导体元件的损伤的观点来看，能够抑制半导体芯片CH11的工作的可靠性的下降。
另外，例如，也可以在包含于半导体芯片群CH1的全部的半导体芯片设置缺口部。因此，能够对全部半导体芯片应用相同的制造工艺。其结果，能够使半导体存储装置1的制造效率提高。
缺口部C优选以在焊盘P11的周边能够得到约25μm的高度的空间的方式设置。引线W11的直径例如为约15μm。从焊盘P11到引线W11的顶点为止的高度、即环的高度例如为约10μm。由此，引线W11的直径与环的高度之和为约25μm。另外，缺口部C优选以使缺口深度CD成为约15μm左右的方式设置。粘接层32的厚度例如为约10μm。从上述的空间减去粘接层32的厚度后的高度为约15μm。此外，上述的数值是一例，也可以根据半导体芯片CH12、粘接层32、焊盘P11及引线W11的尺寸及形状等而变更。
接着，说明布线基板11上的半导体芯片CH13及焊盘P13的配置。
图3是示出第1实施方式的半导体存储装置1的结构的配置的一例的半导体存储装置1的俯视图。图3是从上方观察半导体芯片群CH1时的图。此外，图3的A-A线表示与作为剖视图的图1对应的截面。另外，半导体芯片CH11、CH12、CH13以重叠的方式设置。
另外，如图3所示，焊盘P13沿着半导体芯片CH13的边CHs而设置多个。边CHs是半导体芯片CH13的一个边。焊盘P13从图3的纸面下方经由引线W13而与布线基板11上的焊盘114电连接。
接着，对半导体存储装置1的制造方法进行说明。
图4是示出第1实施方式的半导体晶片W的单片化方法的一例的剖视图。图5是示出第1实施方式的半导体芯片CH12、CH13的加工方法的一例的剖视图。
首先，利用划片刀DB将半导体晶片W切断。由此，半导体晶片W例如被单片化成半导体芯片CH12及半导体芯片CH13。
接着，利用加工用刀PB对半导体芯片CH11、CH12的边CHs进行加工。加工用刀PB例如比划片刀DB厚，前端为锥状。由此，能够将半导体芯片CH12的与粘接层32的接触面的外周部加工成锥状。同样，能够将半导体芯片CH13的与粘接层33的接触面的外周部加工成锥状。之后，半导体芯片CH12、CH13被安装在半导体芯片CH11上。例如，依次进行单片化后的半导体芯片CH12的设置、引线W12的键合、半导体芯片CH13的设置及引线W13的键合。这样，使半导体芯片群CH1层叠。
此外，利用加工用刀PB的加工也可以在划片刀DB对半导体芯片CH12、CH13的单片化前进行。另外，为了使软的粘接层32、33的加工性提高，也可以在图5中的粘接层32、33上，例如在加工前设置作为加工用垫板发挥功能的假晶片(dummy wafer)等。另外，加工方法不限定于上述的例子。例如，也可以使用能够同时进行半导体芯片CH12、CH13的单片化及加工的形状的刀。另外，也可以通过激光来进行半导体芯片CH12、CH13的加工。
如以上这样，根据第1实施方式，能够将多个半导体芯片CH11、CH12、CH13不错开地层叠。其结果，能够使半导体存储装置1内的各结构的配置的自由度提高。另外，能够在与层叠方向垂直的方向上将多个半导体芯片进一步高集成化。
另外，在半导体芯片CH12设置缺口部C。通过缺口部C，能够扩大半导体芯片CH11与半导体芯片CH12之间的空间。由此，能够将半导体芯片CH12相对于其他的半导体芯片CH11不错开地层叠。
另外，在第1实施方式中，在半导体芯片CH11、CH12、CH13间不设置中介层(interposer)及间隔层等。在半导体芯片CH11、CH12间及半导体芯片CH12、CH13间，分别仅设置有粘接层32、33。由此，能够在层叠方向上将半导体芯片群CH1高集成化。
在第1实施方式中，能够将半导体芯片CH11、CH12、CH13不错开地配置。因此，能够从半导体芯片群CH1的单侧将引线群W1与半导体芯片群CH1连接。由此，能够抑制半导体芯片CH11、CH12、CH13与半导体芯片CH2之间的布线长的不均。另外，能够使半导体芯片CH11、CH12、CH13的电特性更均匀。
此外，半导体芯片群CH1未必需要从半导体芯片群CH1的单侧被连接引线群W1。例如，也可以是，在层叠的偶数层和奇数层中，焊盘群P1分别配置于相反侧。另外，还可以是，焊盘群P1设置于1个半导体芯片的2个边。即使在这些情况下，也以使引线群W1不与半导体芯片群CH1接触的方式设置缺口部。
作为将多个半导体芯片不错开地层叠的其他方法，已知有在多个半导体芯片间将中介层或间隔层等以不与焊盘重叠的方式设置的方法。但是，在该情况下，高集成化会因根据层叠数而设置的中介层或间隔层等的厚度而变得困难。
图6是示出第1比较例的半导体存储装置1a的结构的一例的半导体存储装置1a的剖视图。
一般来说，为了使得半导体芯片CH11、CH12、CH13不重叠在与引线群W1连接的焊盘群P1上，已知有如图6所示那样将半导体芯片CH11、CH12、CH13呈台阶状地错开地层叠的方法。但是，在该情况下，层叠数越增加，则最下层的半导体芯片CH11与最上层的半导体芯片CH13之间的偏移量O越大。会因大的偏移量O而在与层叠方向垂直的方向上需要大的空间。因此，存在半导体存储装置1a内的各结构的配置的自由度下降的可能性。另外，例如，根据产品等，也存在要求在更小的外壳以高密度配置半导体芯片的情况。在该情况下，无法确保偏移量O用的空间，存在产品设计变得困难的可能性。
图7是示出第2比较例的半导体存储装置1b的结构的一例的半导体存储装置1b的剖视图。
作为抑制在第1比较例中说明的偏移量O变大的方法，如图7所示，已知从层叠的中途起将半导体芯片CH14、CH15、CH16向与半导体芯片CH11、CH12、CH13的偏移方向相反的方向错开地层叠。此外，半导体芯片CH14、CH15、CH16包含于半导体芯片群CH1。但是，在该情况下，例如，需要使半导体芯片CH14、CH15、CH16的焊盘P14、P15、P16的位置成为与半导体芯片CH11、CH12、CH13的焊盘P11、P12、P13相反一侧的位置。此外，焊盘P14、P15、P16包含于焊盘群P1。因此，在图7所示的例子中，从半导体芯片群CH1的左右进行引线群W1的键合。在该情况下，半导体芯片CH11、CH12、CH13与半导体芯片CH2之间的布线长会比半导体芯片CH14、CH15、CH16与半导体芯片CH2之间的布线长大。此外，实际层叠的半导体芯片CH11～CH16的层叠方向的厚度例如为100μm以下。另一方面，半导体芯片CH11～CH16的宽度例如为几mm。即，布线长度与引线群W1的高度方向的距离相比更大地受布线111的距离影响。因此，半导体芯片CH11～CH16各自的半导体芯片CH11～CH16与半导体芯片CH2之间的布线长度的不均会变大。其结果，存在半导体芯片CH11～CH16各自的电特性的不均变大的可能性。
另外，作为缺口面CF的形状，例如也考虑弯曲成L字的形状。即，在侧面FS与面F3交叉的角部呈矩形状地形成缺口。但是，存在L字的角成为应力的奇异点的可能性。例如，在与L字的角对应的位置处，有时半导体芯片CH12容易折断。
实施方式是例示，发明的范围不限定于它们。

Claims (9)

1.一种半导体存储装置，
具备基板、第1半导体芯片及第2半导体芯片，
所述第1半导体芯片具有与所述基板相接的第1面、所述第1面的相反侧的第2面及设置于所述第2面的第1焊盘，
所述第2半导体芯片具有与所述第2面相接的第3面、所述第3面的相反侧的第4面及缺口部，
所述缺口部设置于处于所述第3面与所述第4面之间的侧面和所述第3面交叉的角部，在从所述第4面的上方观察时与所述第1焊盘的至少一部分重叠。
2.根据权利要求1所述的半导体存储装置，
所述第1半导体芯片的所述第1焊盘与从所述基板延伸的引线电连接，
所述引线在所述第2半导体芯片的缺口面旁边分离设置。
3.根据权利要求1或2所述的半导体存储装置，
所述缺口部被设置为相对于所述第3面的缺口深度从所述第3面的中心部侧到外周部侧逐渐变大。
4.根据权利要求1或2所述的半导体存储装置，
所述第2半导体芯片还具有：
半导体基板，配置于所述第3面侧；及
半导体元件，配置于所述第4面侧，设置在所述半导体基板上，
所述缺口部设置于所述半导体基板。
5.根据权利要求4所述的半导体存储装置，
所述缺口部离开所述半导体元件而设置。
6.根据权利要求1或2所述的半导体存储装置，
所述第2半导体芯片在所述第4面具有第2焊盘，
所述第2焊盘被配置为在从所述第4面的上方观察时其至少一部分与所述缺口部重叠。
7.根据权利要求1或2所述的半导体存储装置，
所述第2半导体芯片在所述第4面具有第2焊盘，
所述第2焊盘被配置为在从所述第4面的上方观察时其至少一部分与所述第1焊盘重叠。
8.根据权利要求1或2所述的半导体存储装置，
所述第2半导体芯片被配置为在从所述第4面的上方观察时其中心位置与所述第1半导体芯片的中心位置一致。
9.根据权利要求1或2所述的半导体存储装置，
所述第2半导体芯片的所述第3面经由粘接层与所述第1半导体芯片的所述第2面粘接。
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