CN114038900B - TVS chip and production method thereof - Google Patents
TVS chip and production method thereof Download PDFInfo
- Publication number
- CN114038900B CN114038900B CN202111139076.9A CN202111139076A CN114038900B CN 114038900 B CN114038900 B CN 114038900B CN 202111139076 A CN202111139076 A CN 202111139076A CN 114038900 B CN114038900 B CN 114038900B
- Authority
- CN
- China
- Prior art keywords
- silicon substrate
- layer
- junction
- area
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 87
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 87
- 239000010703 silicon Substances 0.000 claims abstract description 87
- 239000000758 substrate Substances 0.000 claims abstract description 77
- 238000009792 diffusion process Methods 0.000 claims abstract description 39
- 238000004140 cleaning Methods 0.000 claims abstract description 21
- 239000007788 liquid Substances 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 238000001259 photo etching Methods 0.000 claims abstract description 7
- 239000011248 coating agent Substances 0.000 claims abstract description 5
- 238000000576 coating method Methods 0.000 claims abstract description 5
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 16
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 238000005520 cutting process Methods 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- 238000001035 drying Methods 0.000 claims description 7
- 238000000206 photolithography Methods 0.000 claims description 5
- 230000007797 corrosion Effects 0.000 claims description 4
- 238000005260 corrosion Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 21
- 230000007547 defect Effects 0.000 abstract description 8
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000000243 solution Substances 0.000 description 16
- 230000008569 process Effects 0.000 description 13
- 239000011521 glass Substances 0.000 description 11
- 238000002161 passivation Methods 0.000 description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Weting (AREA)
Abstract
The invention provides a TVS chip and a production method thereof, relating to the field of semiconductors. The method comprises the steps of cleaning a silicon substrate and oxidizing to form an oxide film; coating photoresist on the surface of the oxide film, and removing the oxide film in the area needing to be diffused by adopting a photoetching mode to form a trenching area; putting the trenched silicon substrate into corrosive liquid to form a shallow trench; removing the photoresist, and cleaning the silicon substrate; attaching a diffusion source on the surface of the silicon substrate, and diffusing in the shallow trench to form an outer deep junction layer; removing an oxide film and cleaning the silicon substrate; and attaching a diffusion source to the surface region of the silicon substrate, and diffusing all the regions to form an inner shallow junction layer. According to the invention, two PN junction layers are formed by two times of diffusion, and the deep junction of the outer layer can protect the shallow junction of the inner layer, so that the PN junction protection capability and the capability of reducing lattice defect pollution are effectively enhanced, and the leakage current is reduced. Meanwhile, the diffusion source is positioned through the shallow trench, so that the subsequent operation and the production are facilitated.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a TVS chip and a production method thereof.
Background
A Transient Voltage Suppressor (TVS) is a diode-type high-performance protection device. When two poles of the TVS diode are impacted by reverse transient high energy, the TVS diode can change the high impedance between the two poles into low impedance at the speed of 10 to the order of minus 12 seconds, absorb surge power of thousands of watts and clamp the voltage between the two poles at a preset value, thereby effectively protecting precise components in an electronic circuit from being damaged by various surge pulses.
The electrical property of the TVS is realized through the movement of electrons and holes of PN, under the condition that the substrate concentration is unchanged, the depth of a PN junction is directly related to the breakdown voltage, namely the shallower the PN junction is, the lower the breakdown voltage is. Conversely, if the breakdown voltage is to be made very low, the PN junction must be made very shallow. Taking a mesa TVS as an example, a mesa TVS chip generally adopts a diffusion process, a silicon wafer is lapped after a substrate is doped, and after diffusion, certain lattice defects are formed on the surface of the silicon wafer, and the closer the silicon wafer is to the surface of the silicon wafer, the more the defects are. Products with breakdown voltage below 10V require that the PN junction depth is reduced during process design due to low voltage, so that the distance from the surface of a silicon wafer is very close, and a PN junction extension area has lattice defects when a chip is electrified, so that leakage current is overlarge.
Disclosure of Invention
Technical problem to be solved
Aiming at the defects of the prior art, the invention provides a TVS chip and a production method thereof, and solves the technical problem that the existing mesa TVS chip with the voltage of below 10V has larger leakage current.
(II) technical scheme
In order to achieve the purpose, the invention is realized by the following technical scheme:
in a first aspect, the present invention provides a TVS chip, which includes a silicon substrate, an inner shallow junction layer and an outer deep junction layer;
the silicon substrate is a boss substrate and comprises a top layer, a middle layer and a bottom layer, wherein the middle layer is positioned at the corner of the boss substrate;
the inner shallow junction layer is positioned on the top layer of the silicon substrate and is formed by diffusing a diffusion source to the silicon substrate;
the outer deep junction layer is positioned on two sides of the inner shallow junction layer, is positioned in the middle layer of the silicon substrate and is formed by diffusing a diffusion source to the silicon substrate.
Preferably, the chip further comprises: an oxide layer, a passivated glass layer and a metal surface;
the oxide layer is attached to the surface of the outer deep junction layer and the surface of the joint of the inner shallow junction layer and the outer deep junction layer.
The passivation glass layer is attached to the surface of the oxide layer;
the metal surface is attached to the surface of the inner shallow junction layer which is not covered by the passivated glass layer.
Preferably, the silicon substrate comprises boron-doped silicon or phosphorus-doped silicon, and the resistivity of the silicon substrate is less than 0.01 omega-m.
In a second aspect, the present invention provides a TVS chip production method, including:
s1, oxidizing the silicon substrate after cleaning to form an oxide film;
s2, coating photoresist on the surface of the oxide film, and removing the oxide film in the area needing to be diffused by adopting a photoetching mode to form a trenching area;
s3, putting the trenched silicon substrate into corrosive liquid to form a shallow trench;
s4, removing photoresist, and cleaning the silicon substrate;
s5, attaching a diffusion source on the surface of the silicon substrate, and diffusing in the shallow trench to form an outer deep junction layer;
s6, removing the oxide film and cleaning the silicon substrate;
and S7, attaching a diffusion source to the surface region of the silicon substrate, and diffusing all the regions to form an inner shallow junction layer.
Preferably, the method further comprises:
s8, removing the oxide layer formed by diffusion, carrying out second photoetching to form an etching area in the center of the shallow trench area, and corroding the etching area to form deep ditching;
and S9, passivating, surface metalizing and cutting to form the TVS chip.
Preferably, the silicon substrate comprises boron-doped silicon or phosphorus-doped silicon, and the resistivity of the silicon substrate is less than 0.01 omega-m.
Preferably, the S3 includes:
chemically corroding the trenching area for 1-5 min by using corrosive liquid under the temperature condition of-10-0 ℃ to form a shallow trench with the depth of 10-20 mu m.
Preferably, the S5 includes:
attaching a boron or phosphorus liquid source on the surface of the silicon substrate, and diffusing for 5-30h at the temperature of 1200-1300 ℃ to form an outer deep junction layer with the depth of 30-50 mu m.
Preferably, the S7 includes:
attaching a boron or phosphorus liquid source on the surface of the silicon substrate, and diffusing for 2-5 hours at the temperature of 1100-1300 ℃ to form an inner-layer shallow junction layer with the depth of 10-20 mu m.
Preferably, the S8 includes:
removing the surface oxide layer by corrosive liquid, cleaning and spin-drying; performing a second photolithography to leave an etched region in the center of the shallow trench region, wherein the relationship between the area S of the etched region and the area M of the upper surface of the shallow trench region is S ≦
M; and (3) dripping corrosive liquid on the etched area, corroding for 10-30 min to form deep ditches with the corrosion depth of 50-150 mu m, and cleaning and drying.
(III) advantageous effects
The invention provides a TVS chip and a production method thereof. Compared with the prior art, the method has the following beneficial effects:
according to the TVS chip and the production method thereof, two PN junction layers are formed by two times of diffusion, and the shallow junction of the inner layer can be protected by the deep junction of the outer layer, so that the PN junction protection capability and the capability of reducing lattice defect pollution are effectively enhanced, and the leakage current is reduced. Meanwhile, the diffusion source is positioned through the shallow trench, so that the subsequent operation and the production are facilitated.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a TVS chip according to an embodiment of the present invention;
FIG. 2 is a flow chart of a TVS chip manufacturing method according to an embodiment of the present invention;
fig. 3 is a chip diagram illustrating a cutting process of a TVS chip manufacturing method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are clearly and completely described, and it is obvious that the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The TVS chip and the production method thereof solve the technical problem that the current mesa TVS chip with breakdown voltage smaller than 10V has large leakage current, realize that the shallow junction of the inner layer can be protected by the outer deep junction, and reduce the leakage current.
In order to solve the technical problems, the general idea of the embodiment of the application is as follows:
for electronic products, the protection circuit is to protect the critical sensitive devices in the circuit from damages caused by over-current, over-voltage, over-heat, and other impacts. The quality of the protection circuit is critical to the quality and life of the electronic product. The TVS is a high-efficiency circuit protection device commonly used internationally at present, and the circuit symbol of the TVS is the same as that of a common voltage stabilizing diode, and the appearance of the TVS is also the same as that of the common diode. Its main feature is that under reverse application condition, when it is subjected to a high-energy large pulse, its working impedance is immediately reduced to extremely low conducting value, so that it can allow large current to pass through, and at the same time, the voltage is clamped at predefined level, its response time is only 10-12And the second level, so that the precision components in the electronic circuit can be effectively protected. However, when TVS chips are manufactured by using the conventional phosphorus boron diffusion process, more lattice defects are generated due to phosphorus boron diffusion, and when the lattice defects are closer to the PN junction, IR bias or failure is likely to occur in products with a depth of less than 10V because of the shallower PN depth. In order to solve the problems, the embodiment of the invention forms two PN junction layers through two times of diffusion, and the deep junction of the outer layer can protect the shallow junction of the inner layer, thereby effectively strengthening the PN junction protection and reducing the impurity pollution and reducing the leakage current.
In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.
In a first aspect, an embodiment of the present invention provides a TVS chip, as shown in fig. 1, the chip has a convex mesa structure as a whole, and includes a silicon substrate 1, an inner shallow junction layer 2, an outer deep junction layer 3, an oxide layer 4, a passivation glass layer 5, and a metal surface 6.
The silicon substrate 1 is a boss substrate and comprises a top layer, a middle layer and a bottom layer, wherein the middle layer is positioned between the top layer and the bottom layer and is a corner of the boss substrate. The inner shallow junction layer 2 is positioned on the top layer of the silicon substrate 1 and is formed by diffusing a diffusion source to the silicon substrate 1. The outer deep junction layer 3 is positioned on two sides of the inner shallow junction layer 2, is positioned in the middle layer of the silicon substrate 1, and is formed by diffusing a diffusion source to the silicon substrate 1. The oxide layer 4 is attached to the surface of the outer deep junction layer 3 and the surface of the joint of the outer deep junction layer 3 and the inner shallow junction layer 2, and the oxide layer 4 is made of silicon dioxide. The passivation glass layer 5 is attached to the surface of the oxide layer 4. The metal surface 6 is attached to the surface of the inner shallow junction layer 2 not covered by the passivated glass layer 5. According to the TVS chip provided by the embodiment of the invention, the deep junction on the outer layer can protect the shallow junction on the inner layer, so that the PN junction protection and impurity pollution reduction capabilities are effectively enhanced, and the leakage current is reduced. Meanwhile, the boss substrate can form good visual coordinates in the generation process, which area is expanded by two knots and which area is expanded by one knot can be conveniently found, namely, the diffusion source is conveniently positioned in the production process, and therefore an inner knot layer and an outer knot layer are formed.
In a second aspect, embodiments of the present invention provide a TVS chip production method for producing a TVS chip of the first aspect. As shown in fig. 2, the method comprises the steps of:
s1, oxidizing the silicon substrate after cleaning to increase an oxide film on the surface of the silicon substrate;
s2, coating photoresist on the surface of the oxide film, and removing the oxide film in the area needing to be diffused by adopting a photoetching mode to form a trenching area;
s3, putting the trenched silicon substrate into corrosive liquid to form a shallow trench;
s4, removing photoresist, and cleaning the silicon substrate;
s5, attaching a diffusion source on the surface of the silicon substrate, and diffusing in the shallow trench to form an outer deep junction layer;
s6, removing the oxide film and cleaning the silicon substrate;
s7, attaching a diffusion source to the surface region of the silicon substrate, and diffusing all the regions to form an inner shallow junction layer;
s8, removing the oxide layer formed by diffusion, carrying out second photoetching to form an etching area in the center of the shallow trench area, and corroding the etching area to form deep ditching;
and S9, passivating, surface metalizing and cutting to form the TVS chip.
According to the TVS chip production method provided by the embodiment of the invention, two PN junction layers are formed by two times of diffusion, and the shallow junction of the inner layer can be protected by the deep junction of the outer layer, so that the PN junction protection capability and the impurity pollution reduction capability are effectively enhanced, and the leakage current is reduced. Meanwhile, the diffusion source is positioned through the shallow trench, so that the subsequent operation and the production are facilitated.
The following describes each step in detail:
in step S1, the silicon substrate is cleaned and oxidized to increase the surface thereof with an oxide film. The specific implementation process is as follows:
cleaning a silicon substrate, and placing the silicon substrate in N under a high-temperature condition2And O2And water vapor, and forming a silicon dioxide oxide film on the surface of the silicon substrate.
It should be noted that, in the embodiment of the present invention, the manufacturing method of the TVS chip with the breakdown voltage smaller than 10V is adopted, because the breakdown voltage is very low, the doping concentration of the silicon substrate is high. The higher the doping concentration of the substrate is, the slower the diffusion rate of the phosphorus source or the boron source in the silicon wafer is, and the control of the junction depth of the PN junction formed by diffusion is more facilitated. In the embodiment of the invention, the silicon substrate is boron-doped silicon or phosphorus-doped silicon, and the resistivity of the silicon substrate is less than 0.01 omega-m.
In step S2, photoresist is coated on the surface of the oxide film, and the area oxide film to be diffused is removed by photolithography to form a trench region. The specific implementation process is as follows:
respectively coating photoresist on both sides of silicon substrate, prebaking, exposing, developing, and adding HF and NH4F and H2And removing silicon dioxide in the region needing to be diffused in the mixed solution of O to form a groove region.
In step S3, the silicon substrate after trenching is put in an etchant to form a shallow trench. The specific implementation process is as follows:
and (3) placing the trenched silicon substrate in a corrosion-resistant flower basket, and then placing the flower basket in an etching tank filled with corrosive liquid. The etching solution is formed by mixing a plurality of etching solutions such as nitric acid, hydrofluoric acid and the like, and chemically etches the trenching area for 1-5 min under the temperature condition of-10-0 ℃ to form a shallow trench with the depth of 10-20 mu m.
In step S4, the photoresist is removed, and the silicon substrate is cleaned. The specific implementation process is as follows:
and then putting the silicon substrate into sulfuric acid solution, removing the photoresist on the surface of the silicon substrate, then cleaning and drying.
In step S5, a diffusion source is attached to the surface of the silicon substrate, and the shallow trench is diffused to form an outer deep junction layer. The specific implementation process is as follows:
and attaching a boron or phosphorus liquid source on the surface of the silicon substrate, and diffusing for 5-30h at the temperature of 1200-1300 ℃ to form an outer deep junction layer (deep junction) with the depth of 30-50 mu m, wherein the deep junction plays a role in protection.
In step S6, the oxide film is removed, and the silicon substrate is cleaned. The specific implementation process is as follows:
and removing the oxide film and the oxide layer formed by the first diffusion by using an etching solution, and cleaning the silicon substrate. The composition of the etching solution is the same as that of the etching solution in step S3.
In step S7, a diffusion source is attached to the surface region of the silicon substrate, and all the regions are diffused to form an inner shallow junction layer. The specific implementation process is as follows:
attaching a boron or phosphorus liquid source on the surface of the silicon substrate, and diffusing for 2-5 hours at the temperature of 1100-1300 ℃ to form an inner-layer shallow junction layer, wherein the inner-layer shallow junction layer is a shallow junction with the depth of 10-20 mu m.
In the embodiment of the present invention, after the diffusion is completed, a small sample needs to be fed, the trial voltage is insufficient, and the time-lapse diffusion is performed again.
In step S8, the oxide layer formed by diffusion is removed, and then a second photolithography is performed to form an etching region in the center of the shallow trench region, and the etching region is etched to form a deep trench, which is implemented as follows:
removing the surface oxide layer by an etching solution (having the same composition as that of the etching solution in step S3), andand cleaning and drying. Performing a second photolithography to leave an etched region in the center of the shallow trench region, wherein the relationship between the etched region S and the upper surface M of the shallow trench region is S ≦
And M. And (3) dripping corrosive liquid on the etched area, corroding for 10-30 min to form deep ditches with the corrosion depth of 50-150 mu m, and cleaning and drying. The deep ditching function lies in exposing the PN junction layer, makes things convenient for follow-up protection to the PN junction layer through the glass passivation. Meanwhile, the deep ditching can effectively reduce the thick bottom of the silicon substrate, and the follow-up cutting is convenient.
In step S9, after the deep trench digging is finished, passivation, surface metallization and cutting are performed to form individual TVS chips. The specific implementation process is as follows:
the passivation has two steps, one is to perform the passivation of the oxide film, the other is to perform the passivation of the glass, the passivation of the oxide film is to mix oxygen and chlorine-containing gas, and an oxide layer is formed through high-temperature oxidation, and the oxide layer has the passivation effect. After the oxide layer is passivated, the glass slurry is coated, and then sintering is carried out at high temperature, so that glass crystallization is formed, namely, the glass layer is passivated, the PN junction is further protected, the passivation capability of the chip is further improved, and the reliability is improved.
The surface metallization is that nickel in nickel liquid is deposited on the surface of a silicon wafer through a reducing agent and a catalyst in a chemical nickel plating mode, and then the nickel and the silicon wafer form an alloy through sintering, so that the surface of the silicon wafer has weldability.
The nickel-plated silicon wafer is a finished wafer, and is cut along a trench of the wafer by a blade or a laser-related device, as shown in fig. 3, a cutting line of the cutting is a center of the deep trench, so that the wafer is divided into chips.
In summary, compared with the prior art, the method has the following beneficial effects:
1. according to the TVS chip and the production method thereof disclosed by the embodiment of the invention, two PN junction layers are formed by two times of diffusion, and the shallow junction of the inner layer can be protected by the deep junction of the outer layer, so that the PN junction protection capability and the impurity pollution reduction capability are effectively enhanced, and the leakage current is reduced.
2. The embodiment of the invention positions the diffusion source through the shallow trench, thereby facilitating subsequent operation and production.
3. The chip provided by the embodiment of the invention does not need an epitaxial layer, can effectively reduce the production cost, can be produced in batch and can realize commercial sale.
4. The substrate adopted by the embodiment of the invention is a silicon substrate with high doping concentration, so that the diffusion rate of a boron or phosphorus liquid source in the silicon wafer can be effectively reduced, and the control of the junction depth of a PN junction is facilitated.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (7)
1. A TVS chip production method, comprising:
s1, oxidizing the silicon substrate after cleaning to form an oxide film;
s2, coating photoresist on the surface of the oxide film, and removing the oxide film in the area needing to be diffused by adopting a photoetching mode to form a trenching area;
s3, putting the trenched silicon substrate into corrosive liquid to form a shallow trench;
s4, removing photoresist, and cleaning the silicon substrate;
s5, attaching a diffusion source on the surface of the silicon substrate, and diffusing in the shallow trench to form an outer deep junction layer;
s6, removing the oxide film and cleaning the silicon substrate;
and S7, attaching a diffusion source to the surface region of the silicon substrate, and diffusing all regions of the surface of the silicon substrate to form an inner shallow junction layer.
2. The TVS chip production method of claim 1, further comprising:
s8, removing the oxide layer formed by diffusion, carrying out second photoetching to form an etching area in the center of the shallow trench area, and corroding the etching area to form deep ditching;
and S9, passivating, surface metalizing and cutting to form the TVS chip.
3. The TVS chip production method of claim 1, wherein said silicon substrate comprises boron-doped silicon or phosphorus-doped silicon having a resistivity of less than 0.01 Ω -m.
4. The TVS chip manufacturing method of claim 1, wherein said S3 comprises:
chemically corroding the trenching area for 1-5 min by using corrosive liquid under the temperature condition of-10-0 ℃ to form a shallow trench with the depth of 10-20 mu m.
5. The TVS chip production method as set forth in any one of claims 1 to 4, wherein the S5 includes:
attaching a boron or phosphorus liquid source on the surface of the silicon substrate, and diffusing for 5-30h at the temperature of 1200-1300 ℃ to form an outer deep junction layer with the depth of 30-50 mu m.
6. The TVS chip production method as set forth in any one of claims 1 to 4, wherein the S7 includes:
attaching a boron or phosphorus liquid source on the surface of the silicon substrate, and diffusing for 2-5 hours at the temperature of 1100-1300 ℃ to form an inner-layer shallow junction layer with the depth of 10-20 mu m.
7. The TVS chip manufacturing method of claim 2, wherein said S8 comprises:
removing an oxide layer formed by diffusion through corrosive liquid, cleaning and drying; performing a second photolithography to leave an etched region in the center of the shallow trench region, wherein the relationship between the area S of the etched region and the area M of the upper surface of the shallow trench region is S ≦
M; and (3) dripping corrosive liquid on the etched area, corroding for 10-30 min to form deep ditches with the corrosion depth of 50-150 mu m, and cleaning and drying.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111139076.9A CN114038900B (en) | 2021-09-27 | 2021-09-27 | TVS chip and production method thereof |
| PCT/CN2022/096369 WO2023045393A1 (en) | 2021-09-27 | 2022-05-31 | Tvs chip and production method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111139076.9A CN114038900B (en) | 2021-09-27 | 2021-09-27 | TVS chip and production method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114038900A CN114038900A (en) | 2022-02-11 |
| CN114038900B true CN114038900B (en) | 2022-06-10 |
Family
ID=80140797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111139076.9A Active CN114038900B (en) | 2021-09-27 | 2021-09-27 | TVS chip and production method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN114038900B (en) |
| WO (1) | WO2023045393A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114038900B (en) * | 2021-09-27 | 2022-06-10 | 安徽芯旭半导体有限公司 | TVS chip and production method thereof |
| CN116013779B (en) * | 2022-12-08 | 2024-01-30 | 江苏长晶科技股份有限公司 | TVS device with BPTM structure and manufacturing method thereof |
| CN117476641B (en) * | 2023-12-28 | 2024-04-09 | 深圳市槟城电子股份有限公司 | High-voltage discharge tube and method for producing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013056556A1 (en) * | 2011-10-19 | 2013-04-25 | 西安电子科技大学 | Layer i vanadium-doped pin-type nuclear battery and preparation method thereof |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201383498Y (en) * | 2009-03-03 | 2010-01-13 | 百圳君耀电子（深圳）有限公司 | Semiconductor diode chip |
| CN101916786A (en) * | 2010-06-22 | 2010-12-15 | 南通明芯微电子有限公司 | High-power planar junction bidirectional TVS diode chip and production method thereof |
| US8987858B2 (en) * | 2013-03-18 | 2015-03-24 | General Electric Company | Method and system for transient voltage suppression |
| CN103972305B (en) * | 2014-04-18 | 2017-01-11 | 苏州固锝电子股份有限公司 | Method for manufacturing low-voltage transient voltage suppression diode chip |
| CN104091823A (en) * | 2014-07-24 | 2014-10-08 | 江苏捷捷微电子股份有限公司 | Transient-suppression diode chip and manufacturing method thereof |
| CN108365015A (en) * | 2017-12-29 | 2018-08-03 | 济南兰星电子有限公司 | Semiconductor diode chip and preparation method thereof |
| CN108987458B (en) * | 2018-07-03 | 2021-09-17 | 西安卫光科技有限公司 | Bidirectional low-voltage plane transient voltage suppression diode and manufacturing method thereof |
| CN109860309A (en) * | 2019-02-13 | 2019-06-07 | 安徽亚科微电子科技有限公司 | A kind of the structure design and production method of TVS |
| CN111128698A (en) * | 2019-12-26 | 2020-05-08 | 安徽芯旭半导体有限公司 | Novel diffusion process of TVS chip |
| CN111370497A (en) * | 2020-04-24 | 2020-07-03 | 济南兰星电子有限公司 | Semiconductor mesa diode chip and manufacturing method thereof |
| CN111863616A (en) * | 2020-08-03 | 2020-10-30 | 江苏晟驰微电子有限公司 | 5G base station protection chip manufacturing process |
| CN114038900B (en) * | 2021-09-27 | 2022-06-10 | 安徽芯旭半导体有限公司 | TVS chip and production method thereof |
-
2021
- 2021-09-27 CN CN202111139076.9A patent/CN114038900B/en active Active
-
2022
- 2022-05-31 WO PCT/CN2022/096369 patent/WO2023045393A1/en active Application Filing
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013056556A1 (en) * | 2011-10-19 | 2013-04-25 | 西安电子科技大学 | Layer i vanadium-doped pin-type nuclear battery and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114038900A (en) | 2022-02-11 |
| WO2023045393A1 (en) | 2023-03-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114038900B (en) | TVS chip and production method thereof | |
| RU2468475C2 (en) | Method of making silicon solar cell (versions) and corresponding solar cell | |
| CN102592995B (en) | Manufacture method of Zener diode | |
| JPWO2008065918A1 (en) | Solar cell and method for manufacturing the same | |
| CN104078353B (en) | Reverse GPP high-voltage diodes chip and production technology in a kind of automobile module | |
| CN103035746B (en) | Current regulative diode and manufacturing method thereof | |
| CN203150557U (en) | Reverse direction GPP high voltage diode chip in automobile module group | |
| CN107680962B (en) | Low forward voltage TVS device and manufacturing method thereof | |
| CN111640788A (en) | GPP unidirectional instantaneous voltage suppression diode chip and production method thereof | |
| CN106057914A (en) | Double step field plate terminal based 4H-SiC Schottky diode and manufacturing method thereof | |
| CN111446331A (en) | Method for removing plating and method for preparing passivated contact solar cell | |
| CN114203550A (en) | Transient suppression diode and manufacturing method thereof | |
| CN210866178U (en) | TVS device of integrated unidirectional low-capacity GPP process | |
| CN104616978A (en) | Silicon-carbide power device terminal structure manufacturing method | |
| CN104637793A (en) | Manufacturing method of terminal structure of silicon carbide device | |
| CN116959979A (en) | Production process of high temperature resistant GPP chip | |
| CN111370497A (en) | Semiconductor mesa diode chip and manufacturing method thereof | |
| CN108987458B (en) | Bidirectional low-voltage plane transient voltage suppression diode and manufacturing method thereof | |
| CN212209498U (en) | GPP unidirectional instantaneous voltage suppression diode chip | |
| CN105990134B (en) | A method of making diode | |
| CN112909078B (en) | High-voltage ultrafast recovery diode chip and manufacturing method thereof | |
| CN116169181B (en) | Low-leakage low-voltage TVS device and manufacturing method thereof | |
| CN113066722B (en) | Method for manufacturing high-voltage element anisotropically | |
| CN208861996U (en) | A kind of Schottky chip and Schottky diode of arbitrary structures | |
| RU165466U1 (en) | MESASTRUCTURE ETCHING MASK |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |