CN111640788A - GPP unidirectional instantaneous voltage suppression diode chip and production method thereof - Google Patents
GPP unidirectional instantaneous voltage suppression diode chip and production method thereof Download PDFInfo
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- CN111640788A CN111640788A CN202010615164.0A CN202010615164A CN111640788A CN 111640788 A CN111640788 A CN 111640788A CN 202010615164 A CN202010615164 A CN 202010615164A CN 111640788 A CN111640788 A CN 111640788A
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- GVVPGTZRZFNKDS-JXMROGBWSA-N geranyl diphosphate Chemical compound CC(C)=CCC\C(C)=C\CO[P@](O)(=O)OP(O)(O)=O GVVPGTZRZFNKDS-JXMROGBWSA-N 0.000 title claims abstract description 25
- 230000001629 suppression Effects 0.000 title claims abstract description 14
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- 238000005530 etching Methods 0.000 claims abstract description 18
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- 230000001052 transient effect Effects 0.000 claims abstract description 7
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- 238000005260 corrosion Methods 0.000 claims abstract description 5
- 238000004140 cleaning Methods 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 239000000843 powder Substances 0.000 claims description 16
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000009792 diffusion process Methods 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 7
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000002791 soaking Methods 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910017604 nitric acid Inorganic materials 0.000 claims description 4
- 238000001962 electrophoresis Methods 0.000 claims description 3
- FYDKNKUEBJQCCN-UHFFFAOYSA-N lanthanum(3+);trinitrate Chemical compound [La+3].[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O FYDKNKUEBJQCCN-UHFFFAOYSA-N 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 238000005488 sandblasting Methods 0.000 claims description 3
- 229910021484 silicon-nickel alloy Inorganic materials 0.000 claims description 3
- 230000005684 electric field Effects 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000005406 washing Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 6
- 241000293849 Cordylanthus Species 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 8
- 239000008367 deionised water Substances 0.000 description 4
- 229910021641 deionized water Inorganic materials 0.000 description 4
- 238000007599 discharging Methods 0.000 description 4
- 239000007921 spray Substances 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
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- 238000005476 soldering Methods 0.000 description 2
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- 229910019213 POCl3 Inorganic materials 0.000 description 1
- 229960000583 acetic acid Drugs 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- SWXQKHHHCFXQJF-UHFFFAOYSA-N azane;hydrogen peroxide Chemical compound [NH4+].[O-]O SWXQKHHHCFXQJF-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 239000007789 gas Substances 0.000 description 1
- 239000012362 glacial acetic acid Substances 0.000 description 1
- CABDFQZZWFMZOD-UHFFFAOYSA-N hydrogen peroxide;hydrochloride Chemical compound Cl.OO CABDFQZZWFMZOD-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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Abstract
The invention provides a GPP unidirectional instantaneous voltage suppression diode chip and a production method thereof, wherein the production method comprises the following steps: an N + + layer 4, a P + layer 5, and a P + + layer 6; the upper surface of the P + + layer 6 comprises a plane part and an etching groove 1 arranged around the edge of the plane part; the P + layer 5 is disposed on the P + + layer 6, and the N + + layer 4 is disposed on the P + layer 5; and passivating glass 2 is arranged in the side surface of the N + + layer 4, the side surface of the P + layer 5 and the corrosion groove 1. By adopting the P + substrate, the uniformity of the P + substrate is better, the VB of the product is more uniform, and the characteristics of the transient voltage suppression diode are met. The adoption of the inverted trapezoid groove shape avoids the bird's beak shape of the photoresist mask, improves the uniformity of the electrophoretic glass, and reduces the risk of point discharge.
Description
Technical Field
The invention relates to the field of electronic components, in particular to a GPP unidirectional instantaneous voltage suppression diode chip and a production method thereof.
Background
Gpp (glass passivation parts), the glass passivation technology has high reliability and stability, and is widely applied to the table passivation of high-back-voltage high-power diodes.
Patent document CN203150557U discloses a reverse GPP high voltage diode chip in an automobile module, wherein the reverse GPP high voltage diode chip is of a P + + -P + -N + type; the front side layer cutting structure of the reverse GPP high-voltage diode core sequentially comprises a corrosion groove, passivated glass and a metal layer; the cross section layer-cutting structure of the reverse GPP high-voltage diode core sequentially comprises a corrosion groove, passivated glass, a metal layer, an N + region, a base region N, a P + region and a high-concentration P + + region.
The traditional GPP unidirectional instantaneous voltage suppression diode generally adopts N + as a substrate, so that the uniformity of breakdown voltage VB is poor; meanwhile, the bird's beak shape of the photoresist mask is easily caused in the grooving process, the uniformity of the electrophoretic glass is reduced, and the risk of point discharge exists.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a GPP unidirectional transient voltage suppression diode chip and a production method thereof.
According to the present invention, a GPP unidirectional transient voltage suppression diode chip includes: an N + + layer (4), a P + layer (5) and a P + + layer (6);
the upper surface of the P + + layer (6) comprises a plane part and an etching groove (1) which is arranged along the edge of the plane part in a surrounding mode;
the P + layer (5) is arranged on the upper side of the P + + layer (6), and the N + + layer (4) is arranged on the upper side of the P + layer (5);
and passivating glass (2) is arranged on the side surface of the N + + layer (4), the side surface of the P + layer (5) and the corrosion groove (1).
Preferably, the etch trench (1) has a half inverted trapezoid shape.
Preferably, the width of the planar portion is the same as the width of the N + + layer (4) and the P + layer (5).
Preferably, the passivated glass (2) on the side of the N + + layer (4) is higher than the upper surface of the N + + layer (4).
Preferably, the upper surface of the N + + layer (4) is provided with a first metal layer and a silicon dioxide layer (7) disposed around an edge of the first metal layer.
Preferably, the passivation glass (2) on the side surface of the N + + layer (4) is higher than the upper surface of the N + + layer (4), covers the edge of the upper surface of the N + + layer (4), and is connected with the silicon dioxide layer (7).
Preferably, the lower surface of the P + + layer (6) is provided with a second metal layer.
Preferably, the depth of the etching groove (1) is 80 +/-3 microns.
Preferably, the width of the widest part of the etching groove (1) is 280 +/-10 microns.
According to the present invention, there is provided a method for producing a GPP unidirectional tvs chip as claimed in claim 1, comprising:
step 1: cleaning the surface of the P + type silicon wafer;
step 2: carrying phosphorus oxychloride with 10 ℃ by using 3L/min nitrogen, and diffusing at 1000 ℃ for 2 hours to form an N + + layer on the surface of the silicon wafer;
and step 3: soaking for 30min by using hydrofluoric acid to remove an oxide layer caused by diffusion;
and 4, step 4: a sand blasting machine is used on the reverse side to remove the thickness of 30 +/-3 microns, and the N + + layer on the bottom surface is removed;
and 5: cleaning the surface;
step 6: coating a liquid boron source with the concentration of 10% on the back surface, coating the source at the speed of 3000 r/min, and diffusing at 1250 ℃ for 20 hours to form a P + + layer;
and 7: soaking for 30min by using hydrofluoric acid to remove an oxide layer caused by diffusion;
and 8: introducing water vapor at 1150 ℃ for oxidation for 24 hours to ensure that the thickness of the obtained oxide layer reaches 3 microns;
and step 9: scribing the size of the required chip by using a scribing machine;
step 10: etching for 10min at-10 ℃ by using nitric acid, and etching to obtain an etched groove by using an oxide layer as a mask;
step 11: cleaning and etching the groove;
step 12: 100g of glass powder is poured into the lanthanum nitrate solution, the glass powder is electrified by ultrasonic waves, electrophoresis is carried out for 2 minutes under the condition that the electrode voltage is 180V, and the glass powder uniformly grows in the groove under the action of an electric field, wherein the thickness of the glass powder reaches 20 +/-3 micrometers;
step 13: heating at 800 deg.C for 30min to melt the glass powder;
step 14: cleaning the surface of the silicon wafer;
step 15: growing an oxide layer with the thickness of 3000 +/-300 angstroms on the surface of the silicon wafer by adopting LPCVD at the temperature of 800 ℃, and complementing the damage of the original oxide layer caused by the grooving;
step 16: coating negative photoresist with the viscosity of 450 on the surface of the silicon wafer, wherein the film thickness is 8 microns;
and step 17: exposing the glass powder by using a photoetching plate under a photoetching machine, and leaving 20 microns of width on the periphery of the grown glass powder;
step 18: washing away the unexposed portion with a developing solution;
step 19: baking at 135 deg.C for 30min to harden the photoresist;
step 20: removing the oxide layer without the photoresist protection part;
step 21: removing the photoresist by using a 20% solution of sulfuric acid and hydrogen peroxide at 80 ℃;
step 22: chemical nickel plating, the thickness is 1 micron;
step 23: nickel diffuses into a part of the silicon wafer at 600 ℃ to form a silicon-nickel alloy layer.
Compared with the prior art, the invention has the following beneficial effects:
1. by adopting the P + substrate, the uniformity of the P + substrate is better, the VB of the product is more uniform, and the characteristics of the transient voltage suppression diode are met.
2. The adoption of the inverted trapezoid groove shape avoids the bird's beak shape of the photoresist mask, improves the uniformity of the electrophoretic glass, and reduces the risk of point discharge.
3. An oxide layer is reserved between the passivated glass and the first metal layer, so that the reliability risk caused by pressing the soldering tin on the glass during welding is effectively eliminated.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a cross-sectional view of the present invention;
FIG. 2 is a block diagram of a process flow of the present invention;
fig. 3 to 14 are schematic views of the process of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
As shown in fig. 1, the GPP unidirectional tvs chip provided in this embodiment includes: an N + + layer 4, a P + layer 5, and a P + + layer 6.
The upper surface of the P + + layer 6 comprises a plane part and an etch trench 1 arranged along the edge of the plane part in a surrounding mode, the P + layer 5 is arranged on the upper side of the P + + layer 6, the N + + layer 4 is arranged on the upper side of the P + layer 5, and passivation glass 2 is arranged on the side face of the N + + layer 4, the side face of the P + layer 5 and the etch trench 1.
In the present embodiment, the shape of the etching trench 1 is a half inverted trapezoid. The depth of the etched trench 1 was 80 microns and the width of the etched trench 1 was 280 microns.
The width of the planar portion is the same as the width of the N + + layer 4 and the P + layer 5, and the height of the passivated glass 2 on the side of the N + + layer 4 is higher than the upper surface of the N + + layer 4. The upper surface of the N + + layer 4 is provided with a first metal layer and a silicon dioxide layer 7 arranged around the edge of the first metal layer. The passivated glass 2 on the side surface of the N + + layer 4 is higher than the upper surface of the N + + layer 4, covers the edge of the upper surface of the N + + layer 4, and is connected with the silicon dioxide layer 7. The lower surface of the P + + layer 6 is provided with a second metal layer.
As shown in fig. 3 to 14, the production process flow of the embodiment of the invention is as follows:
1) diffusion cleaning: and SC1, SC2, deionized water spray quick-discharging cleaning and other processes are carried out to clean the surface of the silicon wafer shown in the figure 3. SC1 and SC2 are a first cleaning solution (ammonia hydrogen peroxide) and a second cleaning solution (hydrochloric acid hydrogen peroxide).
2)POCl3Diffusion: a4 inch diffusion of phosphorus oxychloride at 10 ℃ using 3L/min nitrogen gas at 1000 ℃ for 2 hours resulted in the N + + layer shown in FIG. 4.
3) Removing an oxidation layer: and soaking for 30min by using hydrofluoric acid to remove an oxide layer caused by diffusion.
4) Back thinning: as shown in fig. 5, the opposite side of the wafer was removed by a sandblasting machine to remove 30 microns and the counter source caused by diffusion, i.e., the bottom N + + layer was removed.
5) Diffusion cleaning: and carrying out SC1, SC2, deionized water spraying, quick-discharging, cleaning and other procedures to clean the surface of the silicon wafer.
6) Back boron diffusion: the backside was coated with a liquid boron source at a concentration of 10%, and the source was diffused at 1250 c for 20 hours using a speed of 3000 rpm to obtain a P + + layer as shown in fig. 6.
7) Removing an oxidation layer: and soaking for 30min by using hydrofluoric acid to remove an oxide layer caused by diffusion.
8) Wet oxidation: the oxidation was carried out by passing water vapor at 1150 ℃ for 24 hours to reach an oxide layer thickness of 3 μm, as shown in FIG. 7.
9) Scribing: the desired chip size was scribed using a Disco321 dicing saw, 200 microns wide and 40 microns deep, as shown in FIG. 8.
10) Grooving: etching was performed at-10 ℃ for 10min using a pad nitric acid (nitric acid: hydrofluoric acid: glacial acetic acid: sulfuric acid: 9: 12: 4), using the oxide layer as a mask, and after etching, the trench depth was 80 μm and the width was 280 μm, as shown in fig. 9.
11) Cleaning a groove: SC1, SC2, deionized water spray quick-discharging cleaning and other procedures clean the groove and reserve the electrophoretic glass.
12) Electrophoresis: 100g of NEG GP230 glass powder was poured into the lanthanum nitrate solution and electrophoresed at 180V for 2 minutes until the thickness of the glass powder reached 20 μm, as shown in FIG. 10.
13) And (3) glass burning: and (4) firing at 800 ℃ for 30min to melt the glass.
14) Cleaning: SC1, SC2, deionized water spray quick-discharging cleaning and the like.
15) MTO: growing a 3000 angstrom oxide layer on the surface of the substrate by LPCVD at 800 ℃, and complementing the damage of the original oxide layer caused by the grooving.
16) Gluing: the surface of the silicon wafer is coated with negative photoresist with the viscosity of 450, and the film thickness is 8 microns.
17) Photoetching: the plate was exposed to light using a photolithography machine, leaving a 20 micron width around the periphery of the grown glass frit.
18) And (3) developing: the developer washes away the unexposed portions.
19) Hardening the film: baking at 135 deg.C for 30min to completely harden the photoresist.
20) Silicon etching: as shown in fig. 11, the oxide layer without the photoresist protection is removed and nickel plating is left.
21) Removing the photoresist: and removing the photoresist by using sulfuric acid and hydrogen peroxide 20% solution at 80 ℃.
22) Electroless nickel was plated to a thickness of 1 micron as shown in figure 12.
23) And (3) sintering and infiltrating: the nickel diffuses into the silicon at 600 ℃ to form a silicon-nickel alloy.
24) And (3) testing: and (5) testing by using a probe station, and dotting defective products.
25) Scribing: as shown in fig. 13, dicing using a laser dicing saw resulted in the individual chips shown in fig. 14.
26) Packaging and warehousing: and weighing the chips, packaging into a finished product warehouse, and finishing the process.
Through tests, the parameters of the GPP unidirectional instantaneous voltage suppression diode chip produced by the invention are as follows:
according to the production process of the GPP unidirectional instantaneous voltage suppression diode chip, the gas carrying source is adopted for diffusion, the high-concentration PN diffusion junction with good flatness and uniformity is formed, the stability and uniformity and the surge resistance of voltage are enhanced, and the ohmic contact with metal is enhanced; the silicon dioxide is adopted for carrying out the process of digging grooves after scribing the mask, so that inverted trapezoidal grooves are formed, bird mouths of the grooves are removed, the electrophoretic glass is more suitable for carrying out glass passivation, the uniformity of the electrophoretic glass is improved, and the problem of point discharge is solved; a20-micron oxide layer is reserved between glass and metal by photoetching to remove the oxide layer, so that the reliability risk caused by pressing the soldering tin on the glass during welding is effectively eliminated.
In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (10)
1. A GPP unidirectional transient voltage suppression diode chip is characterized by comprising: an N + + layer (4), a P + layer (5) and a P + + layer (6);
the upper surface of the P + + layer (6) comprises a plane part and an etching groove (1) which is arranged along the edge of the plane part in a surrounding mode;
the P + layer (5) is arranged on the upper side of the P + + layer (6), and the N + + layer (4) is arranged on the upper side of the P + layer (5);
and passivating glass (2) is arranged on the side surface of the N + + layer (4), the side surface of the P + layer (5) and the corrosion groove (1).
2. The GPP unidirectional tvs chip of claim 1, wherein the etching trench (1) has a half-inverted trapezoid shape.
3. The GPP unidirectional tvs chip of claim 1, wherein the width of said planar portion is the same as the width of said N + + layer (4) and said P + layer (5).
4. The GPP unidirectional tvs chip of claim 1, wherein a height of the passivation glass (2) on the side of the N + + layer (4) is higher than an upper surface of the N + + layer (4).
5. The GPP unidirectional tvs chip of claim 1, wherein said N + + layer (4) is provided on its upper surface with a first metal layer and a silicon dioxide layer (7) disposed around the edge of said first metal layer.
6. The GPP unidirectional TVS diode chip of claim 5, wherein a passivation glass (2) on a side surface of the N + + layer (4) is higher than an upper surface of the N + + layer (4), covers an edge of the upper surface of the N + + layer (4), and is connected to the silicon dioxide layer (7).
7. The GPP unidirectional tvs chip of claim 1, wherein the lower surface of said P + + layer (6) is provided with a second metal layer.
8. The GPP unidirectional transient voltage suppression diode chip according to claim 1, wherein the depth of the etching trench (1) is 80 ± 3 microns.
9. The GPP unidirectional transient voltage suppression diode chip according to claim 1, wherein the widest width of the etching trench (1) is 280 ± 10 μm.
10. A method for producing a GPP unidirectional tvs chip as claimed in claim 1, comprising:
step 1: cleaning the surface of the P + type silicon wafer;
step 2: carrying phosphorus oxychloride with 10 ℃ by using 3L/min nitrogen, and diffusing at 1000 ℃ for 2 hours to form an N + + layer on the surface of the silicon wafer;
and step 3: soaking for 30min by using hydrofluoric acid to remove an oxide layer caused by diffusion;
and 4, step 4: a sand blasting machine is used on the reverse side to remove the thickness of 30 +/-3 microns, and the N + + layer on the bottom surface is removed;
and 5: cleaning the surface;
step 6: coating a liquid boron source with the concentration of 10% on the back surface, coating the source at the speed of 3000 r/min, and diffusing at 1250 ℃ for 20 hours to form a P + + layer;
and 7: soaking for 30min by using hydrofluoric acid to remove an oxide layer caused by diffusion;
and 8: introducing water vapor at 1150 ℃ for oxidation for 24 hours to ensure that the thickness of the obtained oxide layer reaches 3 microns;
and step 9: scribing the size of the required chip by using a scribing machine;
step 10: etching for 10min at-10 ℃ by using nitric acid, and etching to obtain an etched groove by using an oxide layer as a mask;
step 11: cleaning and etching the groove;
step 12: 100g of glass powder is poured into the lanthanum nitrate solution, the glass powder is electrified by ultrasonic waves, electrophoresis is carried out for 2 minutes under the condition that the electrode voltage is 180V, and the glass powder uniformly grows in the groove under the action of an electric field, wherein the thickness of the glass powder reaches 20 +/-3 micrometers;
step 13: heating at 800 deg.C for 30min to melt the glass powder;
step 14: cleaning the surface of the silicon wafer;
step 15: growing an oxide layer with the thickness of 3000 +/-300 angstroms on the surface of the silicon wafer by adopting LPCVD at the temperature of 800 ℃, and complementing the damage of the original oxide layer caused by the grooving;
step 16: coating negative photoresist with the viscosity of 450 on the surface of the silicon wafer, wherein the film thickness is 8 microns;
and step 17: exposing the glass powder by using a photoetching plate under a photoetching machine, and leaving 20 microns of width on the periphery of the grown glass powder;
step 18: washing away the unexposed portion with a developing solution;
step 19: baking at 135 deg.C for 30min to harden the photoresist;
step 20: removing the oxide layer without the photoresist protection part;
step 21: removing the photoresist by using a 20% solution of sulfuric acid and hydrogen peroxide at 80 ℃;
step 22: chemical nickel plating, the thickness is 1 micron;
step 23: nickel diffuses into a part of the silicon wafer at 600 ℃ to form a silicon-nickel alloy layer.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112289678A (en) * | 2020-11-07 | 2021-01-29 | 扬州虹扬科技发展有限公司 | Processing method before silicon wafer electrophoresis |
| CN113113324A (en) * | 2021-04-07 | 2021-07-13 | 捷捷半导体有限公司 | Passivation layer manufacturing method |
| CN113611607A (en) * | 2021-08-26 | 2021-11-05 | 山东晶导微电子股份有限公司 | Electrophoresis process manufacturing method of semiconductor discrete device fast recovery chip |
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2020
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112289678A (en) * | 2020-11-07 | 2021-01-29 | 扬州虹扬科技发展有限公司 | Processing method before silicon wafer electrophoresis |
| CN112289678B (en) * | 2020-11-07 | 2022-05-13 | 扬州虹扬科技发展有限公司 | Processing method before silicon wafer electrophoresis |
| CN113113324A (en) * | 2021-04-07 | 2021-07-13 | 捷捷半导体有限公司 | Passivation layer manufacturing method |
| CN113113324B (en) * | 2021-04-07 | 2024-02-06 | 捷捷半导体有限公司 | Passivation layer manufacturing method |
| CN113611607A (en) * | 2021-08-26 | 2021-11-05 | 山东晶导微电子股份有限公司 | Electrophoresis process manufacturing method of semiconductor discrete device fast recovery chip |
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