CN111863616A - 5G base station protection chip manufacturing process - Google Patents
5G base station protection chip manufacturing process Download PDFInfo
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- CN111863616A CN111863616A CN202010768084.9A CN202010768084A CN111863616A CN 111863616 A CN111863616 A CN 111863616A CN 202010768084 A CN202010768084 A CN 202010768084A CN 111863616 A CN111863616 A CN 111863616A
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- phosphorus
- station protection
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 19
- 239000011574 phosphorus Substances 0.000 claims abstract description 19
- 238000009792 diffusion process Methods 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 13
- 230000008021 deposition Effects 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000002161 passivation Methods 0.000 claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 238000004140 cleaning Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000005245 sintering Methods 0.000 claims description 6
- 239000002253 acid Substances 0.000 claims description 3
- 238000004026 adhesive bonding Methods 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 230000001052 transient effect Effects 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 230000001590 oxidative effect Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001962 electrophoresis Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66121—Multilayer diodes, e.g. PNPN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
Abstract
The invention discloses a 5G base station protection chip manufacturing process, relates to the technical field of 5G base stations, and particularly relates to a 5G base station protection chip manufacturing process which comprises the following steps: s1, diffusion pretreatment; s2, oxidizing; s4, double-sided open-tube phosphorus deposition; s5, opening a pipe to expand phosphorus; s6, etching a groove; s7, electrophoretic passivation; and S8, completing chip manufacturing. The chip arranged in the 5G base station protection chip manufacturing process adopts a mesa process, an auxiliary groove structure is designed in the area near the mesa of the chip, when the highest reverse voltage is applied, a depletion layer of a P-type base region is limited in the base region, the breakdown voltage of the depletion layer is higher than the breakdown voltage of a main body junction, the main body junction region is firstly broken down, leakage current is distributed in the main body junction region, and the auxiliary junction region is not broken down, so that the voltage withstanding performance of a high-voltage transient voltage suppressor is improved, and the surge resistance and the reliability of the transient voltage suppressor are improved.
Description
Technical Field
The invention relates to the technical field of 5G base stations, in particular to a 5G base station protection chip manufacturing process.
Background
The 5G base station is a core device of the 5G network, provides wireless coverage, and realizes wireless signal transmission between a wired communication network and a wireless terminal. The architecture and morphology of the base station directly affect how the 5G network is deployed. In the technical standard, the frequency band of 5G is much higher than that of 2G, 3G and 4G networks, and the 5G network mainly works in the frequency band of 3000-5000MHz at present. The base station density of a 5G network will be higher since the higher the frequency, the greater the attenuation in the signal propagation.
Integrated circuits, or microcircuits, microchips, and chips, are a way in electronics to miniaturize circuits, including primarily semiconductor devices, including passive components, and the like, and are typically fabricated on the surface of a semiconductor wafer. The integrated circuit in which the circuit is manufactured over the surface of the semiconductor chip is also referred to as a thin film integrated circuit. Another type of thick film hybrid integrated circuit is a miniaturized circuit formed by a discrete semiconductor device and passive components integrated into a substrate or wiring board.
The 5G base station protection chip has the defects of channel diffusion leakage current and poor chip.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a manufacturing process of a 5G base station protection chip, which solves the problems that the 5G base station protection chip has channel diffusion leakage current and the chip is poor in the background technology.
In order to achieve the purpose, the invention is realized by the following technical scheme: A5G base station protection chip manufacturing process comprises the following steps:
s1, diffusion pretreatment: adopting a P-type monocrystalline silicon wafer, and carrying out chemical treatment on the surface of the silicon wafer through procedures of acid cleaning, sandichz 3# formula cleaning and the like;
s2, oxidation: growing an oxide layer on the silicon wafer subjected to diffusion pretreatment in an oxidation furnace under a certain temperature condition;
s3, photoetching: carrying out the procedures of gluing, exposing, developing, removing an oxide layer and the like on the oxidized silicon wafer, and bidirectionally etching a primary diffusion pattern on both sides;
s4, double-sided open-tube phosphorus deposition: the adopted double-sided open-tube phosphorus source deposition process is characterized in that a proper high-concentration deposition layer can be obtained by depositing for a period of time at high temperature, and the N + depth is pushed to the proper depth required by the product by means of a subsequent phosphorus diffusion process to form a wide N + layer region;
s5, opening a pipe to expand phosphorus: etching the surface of the silicon wafer clean by using 100% HF, diffusing phosphorus again to form a high-concentration N + layer, and pushing the base region junction to a proper depth by using high-temperature push junction to enable the base region junction to reach target pressure resistance;
s6, etching the groove: etching the groove on the diffused silicon wafer by adopting a mesa process to expose the P/N junction;
s7, electrophoretic passivation: adopting electrophoretic passivation protection and sintering at a certain temperature;
s8, completing chip manufacturing: and then, finishing the chip manufacturing by photoetching holes, evaporating metal and scribing.
Optionally, in the step S2 and the oxidizing, the operating temperature range of the oxidizing furnace is 1000-1100 ℃.
Optionally, in the step S4, in the double-sided open-tube phosphor deposition, the deposition time is approximately 180 min.
Optionally, in the step S7 and the electrophoretic passivation, the sintering temperature range is 750-930 ℃.
The invention provides a 5G base station protection chip manufacturing process which has the following beneficial effects:
aiming at the characteristics of market application, a special and appropriate new material for the P-type substrate is selected, channel diffusion is used for reducing leakage current, and electrophoresis passivation is used for improving reliability;
the surface high-concentration N + layer is beneficial to improving the anti-surge capacity, and the electrophoretic compact thin layer improves the reliability;
the chip adopts a mesa process, an auxiliary groove structure is designed in the area near the mesa of the chip, when the highest reverse voltage is applied, the depletion layer of the P-type base region is limited in the base region, the breakdown voltage of the depletion layer is higher than that of a main body junction, the main body junction region is firstly broken down, the leakage current is distributed in the main body junction region, and the auxiliary junction region is not broken down, so that the voltage resistance of the high-voltage transient voltage suppressor is improved, and the surge resistance and the reliability of the transient voltage suppressor are improved.
Drawings
FIG. 1 is a schematic view of the process of the present invention;
FIG. 2 is a schematic diagram of a chip according to the present invention
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Referring to fig. 1 to 2, the present invention provides a technical solution: A5G base station protection chip manufacturing process comprises the following steps:
s1, diffusion pretreatment: adopting a P-type monocrystalline silicon wafer, and carrying out chemical treatment on the surface of the silicon wafer through procedures of acid cleaning, sandichz 3# formula cleaning and the like;
s2, oxidation: growing an oxide layer on the silicon wafer subjected to diffusion pretreatment in an oxidation furnace under a certain temperature condition;
s3, photoetching: carrying out the procedures of gluing, exposing, developing, removing an oxide layer and the like on the oxidized silicon wafer, and bidirectionally etching a primary diffusion pattern on both sides;
s4, double-sided open-tube phosphorus deposition: the adopted double-sided open-tube phosphorus source deposition process is characterized in that a proper high-concentration deposition layer can be obtained by depositing for a period of time at high temperature, and the N + depth is pushed to the proper depth required by the product by means of a subsequent phosphorus diffusion process to form a wide N + layer region;
s5, opening a pipe to expand phosphorus: etching the surface of the silicon wafer clean by using 100% HF, diffusing phosphorus again to form a high-concentration N + layer, and pushing the base region junction to a proper depth by using high-temperature push junction to enable the base region junction to reach target pressure resistance;
s6, etching the groove: etching the groove on the diffused silicon wafer by adopting a mesa process to expose the P/N junction;
s7, electrophoretic passivation: adopting electrophoretic passivation protection and sintering at a certain temperature;
s8, completing chip manufacturing: subsequently, the chip manufacturing is finished by photoetching holes, metal evaporation and scribing;
step S2, in the oxidation, the working temperature range of the oxidation furnace is 1000-1100 ℃;
step S4, depositing for about 180min in double-sided open-tube phosphorus deposition;
step S7, in the electrophoresis passivation, the sintering temperature range is 750-930 ℃.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.
Claims (4)
1. The manufacturing process of the 5G base station protection chip is characterized by comprising the following steps:
s1, diffusion pretreatment: adopting a P-type monocrystalline silicon wafer, and carrying out chemical treatment on the surface of the silicon wafer through procedures of acid cleaning, sandichz 3# formula cleaning and the like;
s2, oxidation: growing an oxide layer on the silicon wafer subjected to diffusion pretreatment in an oxidation furnace under a certain temperature condition;
s3, photoetching: carrying out the procedures of gluing, exposing, developing, removing an oxide layer and the like on the oxidized silicon wafer, and bidirectionally etching a primary diffusion pattern on both sides;
s4, double-sided open-tube phosphorus deposition: the adopted double-sided open-tube phosphorus source deposition process is characterized in that a proper high-concentration deposition layer can be obtained by depositing for a period of time at high temperature, and the N + depth is pushed to the proper depth required by the product by means of a subsequent phosphorus diffusion process to form a wide N + layer region;
s5, opening a pipe to expand phosphorus: etching the surface of the silicon wafer clean by using 100% HF, diffusing phosphorus again to form a high-concentration N + layer, and pushing the base region junction to a proper depth by using high-temperature push junction to enable the base region junction to reach target pressure resistance;
s6, etching the groove: etching the groove on the diffused silicon wafer by adopting a mesa process to expose the P/N junction;
s7, electrophoretic passivation: adopting electrophoretic passivation protection and sintering at a certain temperature;
s8, completing chip manufacturing: and then, finishing the chip manufacturing by photoetching holes, evaporating metal and scribing.
2. The manufacturing process of the 5G base station protection chip according to claim 1, wherein: in the step S2 and the oxidation, the working temperature range of the oxidation furnace is 1000-1100 ℃.
3. The manufacturing process of the 5G base station protection chip according to claim 1, wherein: in the S4 double-sided open-tube phosphorus deposition, the deposition time is about 180 min.
4. The manufacturing process of the 5G base station protection chip according to claim 1, wherein: and in the S7 and electrophoretic passivation, the sintering temperature range is 750-930 ℃.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010768084.9A CN111863616A (en) | 2020-08-03 | 2020-08-03 | 5G base station protection chip manufacturing process |
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| CN202010768084.9A CN111863616A (en) | 2020-08-03 | 2020-08-03 | 5G base station protection chip manufacturing process |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112582480A (en) * | 2020-12-15 | 2021-03-30 | 扬州杰利半导体有限公司 | PN junction passivation process for low-medium voltage table top TVS product |
| CN112820698A (en) * | 2020-12-31 | 2021-05-18 | 江苏晟驰微电子有限公司 | Manufacturing process of quick charging source and interface surge protection chip |
| CN113161427A (en) * | 2020-11-30 | 2021-07-23 | 江苏吉莱微电子股份有限公司 | Low-capacitance high-voltage discharge tube and preparation method thereof |
| CN113270318A (en) * | 2021-05-27 | 2021-08-17 | 江苏晟驰微电子有限公司 | Manufacturing process of unidirectional negative resistance type TVS chip |
| CN114038900A (en) * | 2021-09-27 | 2022-02-11 | 安徽芯旭半导体有限公司 | TVS chip and production method thereof |
| CN115472605A (en) * | 2022-09-10 | 2022-12-13 | 江苏晟驰微电子有限公司 | Manufacturing method of high-power low-clamping protection device and protection device |
| CN116169181A (en) * | 2022-09-30 | 2023-05-26 | 富芯微电子有限公司 | Low-leakage low-voltage TVS device and manufacturing method thereof |
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| CN115472605B (en) * | 2022-09-10 | 2023-11-28 | 江苏晟驰微电子有限公司 | Manufacturing method of high-power low-clamping protection device and protection device |
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