CN114373800A - Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit - Google Patents
Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit Download PDFInfo
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The invention provides a transverse double-diffusion field effect transistor, a manufacturing method, a chip and a circuit. The transistor includes: the substrate comprises a first substrate layer, a first oxidation layer, a heavily doped layer, a second oxidation layer and a second substrate layer from top to bottom in sequence, wherein the first substrate layer and the first oxidation layer protrude out of the surface of the heavily doped layer, the first substrate layer and the second substrate layer are of a first conduction type, and the heavily doped layer is of a second conduction type; a well region, a body region, a drift region, a source electrode, a drain electrode and a grid electrode are formed in the first substrate layer; the oxidation isolation layer is formed on the two sides of the first substrate layer and the first oxidation layer, and the bottom of the oxidation isolation layer is in contact with the heavily doped layer; a heavily doped polysilicon region is formed on the outer side of the oxidation isolation layer, the bottom of the heavily doped polysilicon region is in contact with the heavily doped layer, and the heavily doped polysilicon region has a second conductivity type; an electrical electrode is formed within the heavily doped polysilicon region. The transistor provided by the invention can reduce the surface electric field and improve the breakdown voltage.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a transverse double-diffusion field effect transistor, a manufacturing method of the transverse double-diffusion field effect transistor, a chip and a circuit.
Background
As a Lateral power device, a Lateral Double-Diffused MOSFET (LDMOS) has electrodes on the surface of the device, which is easy to implement monolithic integration with a low-voltage signal circuit and other devices through internal connection, and has the advantages of high voltage endurance, large gain, good linearity, high efficiency, good broadband matching performance, etc., and is now widely used in power integrated circuits, especially low-power and high-frequency circuits.
In the prior art, the surface electric field intensity of the transverse double-diffused field effect transistor is very large, so that the breakdown voltage is very easy to break down on the surface, and the breakdown voltage is very low, so that the effect of high breakdown voltage cannot be achieved.
Disclosure of Invention
The invention provides a transverse double-diffusion field effect transistor, a manufacturing method of the transverse double-diffusion field effect transistor, a chip and a circuit, aiming at the technical problem that the surface electric field of the transverse double-diffusion field effect transistor is large in the prior art.
To achieve the above object, an aspect of the present invention provides a lateral double diffused field effect transistor, including: the substrate comprises a first substrate layer, a first oxidation layer, a heavily doped layer, a second oxidation layer and a second substrate layer from top to bottom in sequence, wherein the first substrate layer and the first oxidation layer protrude out of the surface of the heavily doped layer, the first substrate layer and the second substrate layer are of a first conduction type, and the heavily doped layer is of a second conduction type different from the first conduction type; a well region, a body region, a drift region, a source electrode, a drain electrode and a grid electrode are formed in the first substrate layer; the oxidation isolation layer is formed on two sides of the first substrate layer and the first oxidation layer, and the bottom of the oxidation isolation layer is in contact with the heavily doped layer; a heavily doped polysilicon region is formed outside the oxidation isolation layer, the bottom of the heavily doped polysilicon region is in contact with the heavily doped layer, and the heavily doped polysilicon region has a second conductivity type; and an electrical electrode is formed in the heavily doped polysilicon region.
Furthermore, a shallow trench isolation is formed on one side of the drift region, which is far away from the body region.
Further, the number of the shallow trench isolations is at least two; a first protection ring is formed between two adjacent shallow trench isolations and has a second conduction type.
Further, a second guard ring is formed outside the shallow trench isolation, the second guard ring having a first conductivity type.
Furthermore, a micro shallow trench isolation is formed in the drift region and is covered by the polysilicon of a part of the gate.
Further, the thickness of the first oxide layer is between 1000 and 1500 angstroms.
Further, the thickness of the oxidation isolation layer is between 1500-200 angstroms.
The second aspect of the present invention provides a method for manufacturing a lateral double-diffused field effect transistor, where the method for manufacturing a lateral double-diffused field effect transistor includes: forming a substrate, wherein the substrate sequentially comprises a first substrate layer, a first oxidation layer, a heavily doped layer, a second oxidation layer and a second substrate layer from top to bottom, the first substrate layer and the first oxidation layer protrude out of the surface of the heavily doped layer, the first substrate layer and the second substrate layer are of a first conduction type, and the heavily doped layer is of a second conduction type different from the first conduction type; a well region, a body region and a drift region are formed in the first substrate layer; forming an oxidation isolation layer on two sides of the first substrate layer and the first oxidation layer, wherein the bottom of the oxidation isolation layer is in contact with the heavily doped layer; forming a heavily doped polysilicon region outside the oxide isolation layer, wherein the bottom of the heavily doped polysilicon region is in contact with the heavily doped layer, and the heavily doped polysilicon region has a second conductivity type; forming an electrode in the heavily doped polysilicon region; and forming a source electrode, a drain electrode and a grid electrode in the first substrate layer.
Further, the substrate is made of an SOI substrate and a silicon substrate.
Further, the forming a substrate includes: providing an SOI substrate, wherein the SOI substrate comprises an upper silicon layer, an oxide layer and a silicon substrate layer from top to bottom; heavily doping the upper silicon layer of the SOI substrate to form a heavily doped layer; forming an oxide layer on the surface of the heavily doped layer; providing a silicon substrate, wherein the surface of the silicon substrate is provided with an oxide layer; bonding the oxide layer of the silicon substrate with the oxide layer of the SOI substrate to form an initial substrate, wherein the initial substrate sequentially comprises the silicon substrate, the oxide layer, the heavily doped layer, a second oxide layer and a second substrate layer from top to bottom; forming the well region, the drift region and the body region in the silicon substrate; and etching the two sides of the silicon substrate and the oxide layer by utilizing an etching process.
Further, the method further comprises: and after the oxide layer of the silicon substrate is bonded with the oxide layer of the SOI substrate, thinning the thickness of the silicon substrate to a set thickness.
A third aspect of the invention provides a chip comprising a lateral double diffused field effect transistor as described above.
A fourth aspect of the invention provides a circuit comprising a lateral double diffused field effect transistor as described above.
Through the technical scheme provided by the invention, the invention at least has the following technical effects:
the transverse double-diffusion field effect transistor comprises a substrate, wherein the substrate sequentially comprises a first substrate layer, a first oxidation layer, a heavily doped layer, a second oxidation layer and a second substrate layer from top to bottom, the first substrate layer and the first oxidation layer protrude out of the surface of the heavily doped layer, the first substrate layer and the second substrate layer are of a first conduction type, the heavily doped layer is of a second conduction type different from the first conduction type, and a well region, a body region, a drift region, a source electrode, a drain electrode and a grid electrode are formed in the first substrate layer. And the oxidation isolation layer is formed on two sides of the first substrate layer and the first oxidation layer, the bottom of the oxidation isolation layer is in contact with the heavily doped layer, a heavily doped polysilicon region is formed on the outer side of the oxidation isolation layer, the bottom of the heavily doped polysilicon region is in contact with the heavily doped layer, the heavily doped polysilicon region has a second conduction type, and an electrical electrode is formed in the heavily doped polysilicon region. The invention arranges two oxide layers in a substrate and a heavily doped layer between the two oxide layers, the first oxide layer is connected with the oxide isolation layers on the two sides to form the oxide isolation layer, the area in the first substrate layer is used as an active area, and the second oxide layer plays a role of isolation to isolate the heavily doped layer from the second substrate layer. The heavily doped polysilicon regions on the two sides are connected with the grid through the connecting electrodes, the heavily doped layers are used as field plates, and the surface electric field is introduced into the silicon substrate, so that the surface electric field can be effectively reduced, and the breakdown voltage is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1 is a cross-sectional view of an oxide layer formed on an SOI substrate in a method for fabricating a lateral double diffused field effect transistor according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view of an initial substrate formed in a method of fabricating a lateral double diffused field effect transistor according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view of a well region formed in a method of fabricating a lateral double diffused field effect transistor according to an embodiment of the present invention;
fig. 4 is a cross-sectional view of a body region and a drift region formed in a method for fabricating a lateral double diffused field effect transistor according to an embodiment of the present invention;
FIG. 5 is a cross-sectional view of a substrate formed in a method of fabricating a lateral double diffused field effect transistor according to an embodiment of the present invention;
FIG. 6 is a cross-sectional view of an oxide isolation layer and a heavily doped polysilicon region formed in a method for fabricating a lateral double diffused field effect transistor according to an embodiment of the present invention;
fig. 7 is a cross-sectional view of a lateral double diffused field effect transistor formed in a method for fabricating a lateral double diffused field effect transistor according to an embodiment of the present invention;
fig. 8 is a flowchart of a method for fabricating a lateral double diffused field effect transistor according to an embodiment of the invention.
Description of the reference numerals
1-a second substrate layer; 2-a second oxide layer; 3-heavily doped layer; 4-an oxide layer; 5-a silicon substrate; 6-well region; 7-a drift region; an 8-body region; 9-shallow trench isolation; 10-micro shallow trench isolation; 11-a first oxide layer; 12-a first substrate layer; 13-oxidizing the isolation layer; 14-heavily doped polysilicon region; 15-connecting an electrode; 16-a source electrode; 17-a drain electrode; 18-a gate; 19-a first guard ring; 20-second guard ring.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
In the present invention, unless specified to the contrary, use of the terms of orientation such as "upper, lower, top, bottom" or the like are generally described with respect to the orientation shown in the drawings or the positional relationship of the components with respect to each other in the vertical, or gravitational direction.
The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
Referring to fig. 7, an embodiment of the present invention provides a lateral double diffused field effect transistor, which includes: the substrate comprises a first substrate layer 12, a first oxide layer 11, a heavily doped layer 3, a second oxide layer 2 and a second substrate layer 1 from top to bottom in sequence, wherein the first substrate layer 12 and the first oxide layer 11 protrude out of the surface of the heavily doped layer 3, the first substrate layer 12 and the second substrate layer 1 are of a first conductive type, and the heavily doped layer 3 is of a second conductive type different from the first conductive type; a well region 6, a body region 8, a drift region 7, a source electrode 16, a drain electrode 17 and a grid electrode 18 are formed in the first substrate layer 12; an oxide isolation layer 13 formed on both sides of the first substrate layer 12 and the first oxide layer 11, wherein the bottom of the oxide isolation layer 13 is in contact with the heavily doped layer 3; a heavily doped polysilicon region 14 is formed outside the oxidation isolation layer 13, the bottom of the heavily doped polysilicon region 14 is in contact with the heavily doped layer 3, and the heavily doped polysilicon region 14 has a second conductivity type; an electrical electrode 15 is formed in the heavily doped polysilicon region 14.
Specifically, in the embodiment of the present invention, the substrate includes, in order from top to bottom, a first substrate layer 12, a first oxide layer 11, a heavily doped layer 3, a second oxide layer 2, and a second substrate layer 1, where the first substrate layer 12 and the first oxide layer 11 protrude from the surface of the heavily doped layer 3, the first substrate layer 12 and the second substrate layer 1 have a first conductivity type, and the heavily doped layer 3 has a second conductivity type different from the first conductivity type. Oxide isolation layers 13 are formed on two sides of the first substrate layer 12 and the first oxide layer 11, the bottom of each oxide isolation layer 13 is in contact with the heavily doped layer 3, the oxide isolation layers 13 on the two sides are connected with the first oxide layer 11 to play an isolation role, and a well region 6, a body region 8, a drift region 7, a source electrode 16, a drain electrode 17 and a grid electrode 18 are formed in the first substrate layer 12. The heavily doped layer 3 is connected with a high level, the second substrate layer 1 is connected with a low level, and the second oxide layer 2 plays a role in isolating the heavily doped layer 3 from the second substrate layer 1. The heavily doped polysilicon regions 14 on two sides are connected with the gate 18 through the connecting electrode 15, the heavily doped layer 3 is used as a field plate, a surface electric field is introduced into the silicon substrate, and part of the surface electric field is shared, so that the surface electric field can be effectively reduced, and the breakdown voltage is improved.
Furthermore, a shallow trench isolation 9 is formed on one side of the drift region 7 away from the body region 8. The shallow trench isolation 9 is used for isolation.
Further, the number of the shallow trench isolations 9 is at least two; a first guard ring 19 is formed between two adjacent shallow trench isolations 9, the first guard ring 19 having the second conductivity type. The protective ring is connected with a high level to perform voltage protection on the transverse double-diffusion field effect transistor.
Further, a second guard ring 20 is formed outside the shallow trench isolation 9, and the second guard ring 20 has the first conductivity type. The protective ring is connected with the low level and is connected with the substrate to perform voltage protection on the transverse double-diffusion field effect transistor.
Furthermore, a micro shallow trench isolation 10 is formed in the drift region 7, and the micro shallow trench isolation 10 is covered by polysilicon of a part of the gate 18.
Further, the thickness of the first oxide layer 11 is between 1000 and 1500 angstroms.
Specifically, in the embodiment of the invention, the thickness of the first oxide layer 11 is between 1000-. If the first oxide layer 11 is too thick, the effect of sharing the electric field is poor, which is not beneficial to reducing the surface electric field, and if the first oxide layer 11 is too thin, there is a risk of breakdown.
Further, the thickness of the oxide isolation layer 13 is between 1500-200 angstroms.
Specifically, in the embodiment of the present invention, the thickness of the oxide isolation layer 13 is between 1500-.
Referring to fig. 1 to fig. 8, a second aspect of the present invention provides a method for fabricating a lateral double diffused field effect transistor, the method comprising: s101: forming a substrate, wherein the substrate sequentially comprises a first substrate layer 12, a first oxide layer 11, a heavily doped layer 3, a second oxide layer 2 and a second substrate layer 1 from top to bottom, the first substrate layer 12 and the first oxide layer 11 protrude out of the surface of the heavily doped layer 3, the first substrate layer 12 and the second substrate layer 1 have a first conductivity type, and the heavily doped layer 3 has a second conductivity type different from the first conductivity type; a well region 6, a body region 8 and a drift region 7 are formed in the first substrate layer 12; s102: forming an oxidation isolation layer 13 on two sides of the first substrate layer 12 and the first oxidation layer 11, wherein the bottom of the oxidation isolation layer 13 is in contact with the heavily doped layer 3; s103: forming a heavily doped polysilicon region 14 outside the oxide isolation layer 13, wherein the bottom of the heavily doped polysilicon region 14 is in contact with the heavily doped layer 3, and the heavily doped polysilicon region 14 has a second conductivity type; s104: forming an electrical electrode 15 in the heavily doped polysilicon region 14; s105: a source 16, a drain 17 and a gate 18 are formed within the first substrate layer 12.
Step S101 is first executed: forming a substrate, wherein the substrate sequentially comprises a first substrate layer 12, a first oxide layer 11, a heavily doped layer 3, a second oxide layer 2 and a second substrate layer 1 from top to bottom, the first substrate layer 12 and the first oxide layer 11 protrude out of the surface of the heavily doped layer 3, the first substrate layer 12 and the second substrate layer 1 have a first conductivity type, and the heavily doped layer 3 has a second conductivity type different from the first conductivity type; well regions 6, body regions 8 and drift regions 7 are formed in the first substrate layer 12.
Further, the substrate is made of an SOI substrate and a silicon substrate.
Further, the forming a substrate includes: providing an SOI substrate, wherein the SOI substrate comprises an upper silicon layer, an oxide layer and a silicon substrate layer 1 from top to bottom; heavily doping the upper silicon layer of the SOI substrate to form a heavily doped layer 3; forming an oxide layer on the surface of the heavily doped layer 3; providing a silicon substrate, wherein the surface of the silicon substrate is provided with an oxide layer; bonding the oxide layer of the silicon substrate with the oxide layer on the surface of the SOI substrate to form an initial substrate, wherein the initial substrate sequentially comprises a silicon substrate 5, an oxide layer 4, a heavily doped layer 3, a second oxide layer 2 and a second substrate layer 1 from top to bottom; forming the well region 6, the drift region 7 and the body region 8 in the silicon substrate; and etching the two sides of the silicon substrate 5 and the oxide layer 4 by using an etching process.
Further, the method further comprises: and after the oxide layer of the silicon substrate is bonded with the oxide layer of the SOI substrate, thinning the thickness of the silicon substrate to a set thickness.
Specifically, the lateral double-diffused field effect transistor provided in the embodiment of the invention can be an N-type lateral double-diffused field effect transistor and can also be a P-type lateral double-diffused field effect transistor. When the transverse double-diffusion field effect transistor is an N-type transverse double-diffusion field effect transistor, the first doping type is a P type, and the second doping type is an N type; when the lateral double-diffused field effect transistor is a P-type lateral double-diffused field effect transistor, the first doping type is an N-type, and the second doping type is a P-type.
In the embodiment of the invention, the substrate is made of an SOI substrate and a silicon substrate, firstly, the SOI substrate is provided and comprises upper silicon, an oxide layer and a silicon substrate layer 1 from top to bottom, then, N-type heavy doping is carried out on the upper silicon of the SOI substrate to form a heavy doping layer 3, a second oxide layer 2 is arranged between the heavy doping layer 3 and the silicon substrate layer 1, as shown in figure 1, and then the oxide layer is formed on the surface of the heavy doping layer 3. And then providing a silicon substrate, wherein an oxide layer is formed on the surface of the silicon substrate, turning the silicon substrate, and bonding the oxide layer on the surface of the silicon substrate with the oxide layer on the surface of the SOI substrate to form an initial substrate, wherein the initial substrate sequentially comprises a silicon substrate 5, an oxide layer 4, a heavily doped layer 3, a second oxide layer 2 and a second substrate layer 1 from top to bottom. If the thickness of the silicon substrate 5 is greater than the required thickness, the thickness of the silicon substrate 5 is thinned to a set thickness, as shown in fig. 2.
Next, a thin silicon dioxide layer (not shown) is oxidized on the surface of the silicon substrate to protect the silicon substrate, then a photoresist is formed on the surface of the silicon substrate, the photoresist is etched to form an injection window of the well region 6, and then N-type ion injection is performed to form the well region 6, as shown in fig. 3.
Then removing the thin silicon dioxide, oxidizing a layer of thick silicon dioxide (not shown in the figure) again, performing vapor deposition on silicon nitride, performing photoetching on the active region, performing dry etching on the silicon nitride and the silicon dioxide, and performing dry etching on the silicon substrate 5 to form a trench of the shallow trench isolation 9. And photoetching the active region again, and etching the silicon nitride and the silicon dioxide by a dry method to manufacture the groove of the micro shallow groove isolation 10. High-density plasma chemical vapor deposition of a silicon dioxide medium, high-temperature annealing, chemical mechanical polishing to remove the silicon dioxide medium on the surface, and wet removal of silicon nitride and thick silicon dioxide to form shallow trench isolation 9 and micro shallow trench isolation 10.
And oxidizing again to form relatively thick silicon dioxide (not shown), forming photoresist on the surface, performing photolithography to form an implantation window, and performing P-type ion implantation through the implantation window to form the body region 8. And forming photoresist on the surface, forming an injection window by photoetching, performing N-type ion injection through the injection window to form a drift region 7, and removing the photoresist on the surface to form the structure shown in fig. 4.
Both sides of the silicon substrate 5 and the oxide layer 4 are etched by means of an etching process. A substrate comprising a first substrate layer 12, a first oxide layer 13, a heavily doped layer 3, a second oxide layer 2 and a second substrate layer 1 is formed.
Then, step S102 is executed: and forming an oxidation isolation layer 13 on two sides of the first substrate layer 12 and the first oxidation layer 11, wherein the bottom of the oxidation isolation layer 13 is in contact with the heavily doped layer 3.
Step S103 is then executed: a heavily doped polysilicon region 14 is formed outside the oxide isolation layer 13, the bottom of the heavily doped polysilicon region 14 is in contact with the heavily doped layer 3, and the heavily doped polysilicon region 14 has the second conductivity type. As shown in fig. 6.
Specifically, in the embodiment of the present invention, N-type heavily doped polysilicon is deposited by low pressure chemical vapor deposition, and then the surface of the polysilicon is polished by chemical mechanical polishing to form the heavily doped polysilicon region 14.
Then, step S104 is executed: an electrical electrode 15 is formed within the heavily doped polysilicon region 14.
Then, step S105 is executed: a source 16, a drain 17 and a gate 18 are formed within the first substrate layer 12. As shown in fig. 7.
Specifically, in the embodiment of the present invention, the gate electrode 18 is formed on the upper surfaces of the body region 8 and the drift region 7. Carry out N+Ion implantation, forming contact electrode 15 in the heavily doped polysilicon region 14, drain electrode 17 in the drift region 7, source electrode 16 in the body region 8, and N between two adjacent shallow trench isolations 9+And a first guard ring 19 connected to a high level for voltage protection of the lateral double diffused field effect transistor. Carry out P+Ion implantation, forming a second guard ring 20 outside the shallow trench isolation 9, wherein the second guard ring 20 is P-type heavily doped, and forming P on two sides of the well region 6+And the protective ring is connected with the low level and is connected with the substrate to carry out voltage protection on the transverse double-diffusion field effect transistor.
A third aspect of the invention provides a chip comprising a lateral double diffused field effect transistor as described above.
A fourth aspect of the invention provides a circuit comprising a lateral double diffused field effect transistor as described above.
The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, however, the present invention is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are within the protective scope of the present invention.
It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and the invention is not described in any way for the possible combinations in order to avoid unnecessary repetition.
In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as the disclosure of the present invention as long as it does not depart from the spirit of the present invention.
Claims (13)
1. A lateral double diffused field effect transistor, comprising:
the substrate comprises a first substrate layer, a first oxidation layer, a heavily doped layer, a second oxidation layer and a second substrate layer from top to bottom in sequence, wherein the first substrate layer and the first oxidation layer protrude out of the surface of the heavily doped layer, the first substrate layer and the second substrate layer are of a first conduction type, and the heavily doped layer is of a second conduction type different from the first conduction type; a well region, a body region, a drift region, a source electrode, a drain electrode and a grid electrode are formed in the first substrate layer;
the oxidation isolation layer is formed on two sides of the first substrate layer and the first oxidation layer, and the bottom of the oxidation isolation layer is in contact with the heavily doped layer;
a heavily doped polysilicon region is formed outside the oxidation isolation layer, the bottom of the heavily doped polysilicon region is in contact with the heavily doped layer, and the heavily doped polysilicon region has a second conductivity type; and an electrical electrode is formed in the heavily doped polysilicon region.
2. The lateral double diffused field effect transistor of claim 1 wherein a side of the drift region remote from the body region is formed with shallow trench isolation.
3. The lateral double diffused field effect transistor of claim 2 wherein the shallow trench isolations are at least two; a first protection ring is formed between two adjacent shallow trench isolations and has a second conduction type.
4. The lateral double diffused field effect transistor of claim 2 wherein a second guard ring is formed outside the shallow trench isolation, the second guard ring having the first conductivity type.
5. The lateral double diffused field effect transistor of claim 1 wherein a micro shallow trench isolation is further formed in the drift region, the micro shallow trench isolation being covered by a portion of the gate polysilicon.
6. The lateral double diffused field effect transistor of claim 1 wherein the thickness of the first oxide layer is between 1000 and 1500 angstroms.
7. The lateral double diffused field effect transistor of claim 1 wherein the thickness of the oxide isolation layer is between 1500-200 angstroms.
8. A method for manufacturing a transverse double-diffused field effect transistor is characterized by comprising the following steps:
forming a substrate, wherein the substrate sequentially comprises a first substrate layer, a first oxidation layer, a heavily doped layer, a second oxidation layer and a second substrate layer from top to bottom, the first substrate layer and the first oxidation layer protrude out of the surface of the heavily doped layer, the first substrate layer and the second substrate layer are of a first conduction type, and the heavily doped layer is of a second conduction type different from the first conduction type; a well region, a body region and a drift region are formed in the first substrate layer;
forming an oxidation isolation layer on two sides of the first substrate layer and the first oxidation layer, wherein the bottom of the oxidation isolation layer is in contact with the heavily doped layer;
forming a heavily doped polysilicon region outside the oxide isolation layer, wherein the bottom of the heavily doped polysilicon region is in contact with the heavily doped layer, and the heavily doped polysilicon region has a second conductivity type;
forming an electrode in the heavily doped polysilicon region;
and forming a source electrode, a drain electrode and a grid electrode in the first substrate layer.
9. The method of claim 8 wherein the substrate is fabricated from an SOI substrate and a silicon substrate.
10. The method of claim 8, wherein the forming a substrate comprises:
providing an SOI substrate, wherein the SOI substrate comprises an upper silicon layer, an oxide layer and a silicon substrate layer from top to bottom;
heavily doping the upper silicon layer of the SOI substrate to form a heavily doped layer;
forming an oxide layer on the surface of the heavily doped layer;
providing a silicon substrate, wherein the surface of the silicon substrate is provided with an oxide layer;
bonding the oxide layer of the silicon substrate with the oxide layer of the SOI substrate to form an initial substrate, wherein the initial substrate sequentially comprises the silicon substrate, the oxide layer, the heavily doped layer, a second oxide layer and a second substrate layer from top to bottom;
forming the well region, the drift region and the body region in the silicon substrate;
and etching the two sides of the silicon substrate and the oxide layer by utilizing an etching process.
11. The method of fabricating a lateral double diffused field effect transistor according to claim 10, further comprising:
and after the oxide layer of the silicon substrate is bonded with the oxide layer of the SOI substrate, thinning the thickness of the silicon substrate to a set thickness.
12. A chip comprising a lateral double diffused field effect transistor according to any one of claims 1 to 7.
13. A circuit comprising a lateral double diffused field effect transistor according to any one of claims 1 to 7.
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| CN115020478A (en) * | 2022-08-08 | 2022-09-06 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
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| CN101699631A (en) * | 2009-11-19 | 2010-04-28 | 苏州远创达科技有限公司 | LDMOS power device with buried layer |
| US20140070312A1 (en) * | 2012-09-07 | 2014-03-13 | Freescale Semiconductor, Inc. | Semiconductor device and related fabrication methods |
| US20170125584A1 (en) * | 2015-10-29 | 2017-05-04 | Freescale Semiconductor, Inc. | Self-adjusted isolation bias in semiconductor devices |
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| CN101699631A (en) * | 2009-11-19 | 2010-04-28 | 苏州远创达科技有限公司 | LDMOS power device with buried layer |
| US20140070312A1 (en) * | 2012-09-07 | 2014-03-13 | Freescale Semiconductor, Inc. | Semiconductor device and related fabrication methods |
| US20170125584A1 (en) * | 2015-10-29 | 2017-05-04 | Freescale Semiconductor, Inc. | Self-adjusted isolation bias in semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115020478A (en) * | 2022-08-08 | 2022-09-06 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
| CN115020478B (en) * | 2022-08-08 | 2022-10-04 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
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