CN213212170U - Cellular structure, power semiconductor device and electronic equipment - Google Patents
Cellular structure, power semiconductor device and electronic equipment Download PDFInfo
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- CN213212170U CN213212170U CN202022753217.3U CN202022753217U CN213212170U CN 213212170 U CN213212170 U CN 213212170U CN 202022753217 U CN202022753217 U CN 202022753217U CN 213212170 U CN213212170 U CN 213212170U
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Abstract
The utility model relates to a semiconductor field discloses a cellular structure, power semiconductor device and electronic equipment, this cellular structure, include: an epitaxial layer; a P + voltage-resistant region formed on one side of the epitaxial layer; the first polysilicon gate layer and the second polysilicon gate layer are positioned on two sides of the P + voltage-withstanding region; the polycrystalline silicon connecting lead layer is formed on one side, away from the epitaxial layer, of the P + voltage-withstanding region and is used for connecting the first polycrystalline silicon gate layer with the second polycrystalline silicon gate layer; the silicon dioxide layer is formed on one side, away from the epitaxial layer, of the polycrystalline silicon connecting lead layer, and a connecting hole is formed in the silicon dioxide layer so that the polycrystalline silicon connecting lead layer is exposed; and the metal layer is formed on one side of the silicon dioxide layer, which is far away from the epitaxial layer, so that the metal layer is connected with the polycrystalline silicon connecting lead layer. The method is used for solving the problem that the short-circuit resistance is poor due to the reduction of the cell size and the increase of the current density.
Description
Technical Field
The utility model relates to the field of semiconductor technology, in particular to cellular structure, power semiconductor device and electronic equipment.
Background
With the development of modern energy technology, electric energy has become one of the most dominant energy forms at present. In the processes of generation, transmission, use and the like of electric energy, parameters such as voltage, current, frequency and the like need to be regulated, and the regulation processes do not depend on the development of power electronic technology. With the development of power electronics technology, the applications of various inverter circuits and chopper circuits have been expanding, and various power semiconductor devices, such as switching devices such as Insulated Gate Bipolar Transistors (IGBTs), have been widely used in these circuits.
At present, the IGBT is mainly developed towards miniaturization, high current density and high reliability. The IGBT has the advantages of both MOS transistor and bipolar transistor, and consists of two parts, one is the MOS part of the input pole and the other is the BJT part of the output pole, so that the IGBT can be switched fast under small driving condition and has lower saturation voltage drop.
Among the existing IGBTs, a Trench-FS IGBT having both a Trench structure and an FS structure is the mainstream in the industry, and various manufacturers are now dedicated to improving the current density of the Trench-FS IGBT, wherein the most important point for improving the current density is to reduce the cell size.
However, due to the limitation of the process level, the cell size cannot be further reduced when the cell size is reduced to a certain size. When the cell size is reduced, the current density is increased, and the short-circuit resistance of the chip is reduced.
SUMMERY OF THE UTILITY MODEL
The utility model discloses a cell structure, power semiconductor device and electronic equipment for solve because the cell size reduces, the problem that the anti short circuit performance that the current density increase leads to worsens.
In order to achieve the above purpose, the utility model provides the following technical scheme:
in a first aspect, the present invention provides a cellular structure, including:
an epitaxial layer;
a P + voltage-resistant region formed on one side of the epitaxial layer;
the first polysilicon gate layer and the second polysilicon gate layer are positioned on two sides of the P + voltage-withstanding region;
the polycrystalline silicon connecting lead layer is formed on one side, away from the epitaxial layer, of the P + voltage-withstanding region and is used for connecting the first polycrystalline silicon gate layer with the second polycrystalline silicon gate layer;
the silicon dioxide layer is formed on one side, away from the epitaxial layer, of the polycrystalline silicon connecting lead layer, and a connecting hole is formed in the silicon dioxide layer so that the polycrystalline silicon connecting lead layer is exposed;
and the metal layer is formed on one side of the silicon dioxide layer, which is far away from the epitaxial layer, so that the metal layer is connected with the polycrystalline silicon connecting lead layer.
A P + voltage-withstanding area, a first polysilicon gate layer and a second polysilicon gate layer are arranged on one side of the epitaxial layer, and the first polysilicon gate layer and the second polysilicon gate layer are positioned on two sides of the P + voltage-withstanding area; the polysilicon connection lead layer is formed on one side, away from the epitaxial layer, of the P + voltage-resistant area and is used for connecting the first polysilicon gate layer with the second polysilicon gate layer, a connecting hole is formed in the silicon dioxide layer, the polysilicon connection lead layer is exposed, and a metal layer is formed in the connecting hole in the structure and is connected with the polysilicon connection lead layer; and the problem of poor short-circuit resistance caused by the reduction of the cell size and the increase of the current density can be solved by adopting the interconnection mode.
Optionally, the epitaxial layer has a first trench and a second trench;
the first groove and the second groove are positioned on two sides of the P + voltage-resistant area;
the first polycrystalline silicon gate layer is arranged in the first groove, and the second polycrystalline silicon gate layer is arranged in the second groove;
an oxide layer is arranged between the inner wall of the first groove and the first polycrystalline silicon grid layer, and an oxide layer is arranged between the inner wall of the second groove and the second polycrystalline silicon grid layer.
Optionally, the method further comprises: and the Pbody area is formed outside the first groove and the second groove which are far away from the P + voltage-resisting area.
Optionally, the method further comprises: and an N + emission region formed on the side of the Pbody region, which faces away from the epitaxial layer.
Optionally, the method further comprises: and the field stop layer is formed on one side of the epitaxial layer, which is far away from the P + voltage-resistant area.
Optionally, the method further comprises: and the P + collector region is formed on one side, away from the epitaxial layer, of the field stop layer.
Optionally, the method further comprises: and the metal electrode layer is formed on one side of the P + collector region, which is far away from the epitaxial layer.
In a second aspect, the present invention provides a power semiconductor device, including: the cellular structure of any one of the first aspect.
In a second aspect, the present invention provides an electronic device, including: the cellular structure of any one of the first aspect.
Drawings
Fig. 1 is a top view of a cell structure according to an embodiment of the present invention;
fig. 2 is a cross-sectional view of a cell structure taken along the plane a-a in fig. 1 according to an embodiment of the present invention;
fig. 3 to 8 illustrate a cell structure according to an embodiment of the present invention.
Icon: 100-epitaxial layer; 110 — a first trench; 120-a second trench; 200-P + voltage-resistant area; 300-a first polysilicon gate layer; 400-a second polysilicon gate layer; 500-polysilicon connecting lead layer; 600-a silicon dioxide layer; 610-connecting hole; 700-a metal layer; 800-an oxide layer; 900-Pbody area; a 1000-N + emitter region; 1100-field stop layer; a 1200-P + collector region; 1300-metal electrode layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
As shown in fig. 1 and fig. 2, in a first aspect, an embodiment of the present invention provides a cell structure, including:
an epitaxial layer 100; a P + voltage-withstanding region 200 formed on one side of the epitaxial layer 100;
a first polysilicon gate layer 300 and a second polysilicon gate layer 400 located on both sides of the P + voltage withstanding region 200;
a polysilicon connecting lead layer 500 formed on the side of the P + voltage-withstanding region 200 away from the epitaxial layer 100, the polysilicon connecting lead layer 500 being used for connecting the first polysilicon gate layer 300 and the second polysilicon gate layer 400;
a silicon dioxide layer 600 formed on the side of the polysilicon connecting lead layer 500 away from the epitaxial layer 100, wherein a connecting hole 610 is formed in the silicon dioxide layer 600 to expose the polysilicon connecting lead layer 500;
and the metal layer 700 is formed on the side of the silicon dioxide layer 600 away from the epitaxial layer 100, so that the metal layer 700 is connected with the polysilicon connecting lead layer 500.
It should be noted that, here, a P + voltage withstanding region 200, a first polysilicon gate layer 300 and a second polysilicon gate layer 400 are disposed on one side of the epitaxial layer 100 and located on both sides of the P + voltage withstanding region 200; the polysilicon connection lead layer 500 is formed on the side, away from the epitaxial layer 100, of the P + voltage-withstanding region 200, the polysilicon connection lead layer 500 is used for connecting the first polysilicon gate layer 300 with the second polysilicon gate layer 400, a connection hole 610 is formed in the silicon dioxide layer 600, the polysilicon connection lead layer 500 is exposed, and a metal layer 700 is formed in the connection hole 610 in the structure, so that the metal layer 700 is connected with the polysilicon connection lead layer 500, and the connection mode can solve the problem that the metal layer 700 cannot be directly interconnected with the polysilicon connection layer lead due to the reduction of the cell size; and the problem of poor short-circuit resistance caused by the reduction of the cell size and the increase of the current density can be solved by adopting the interconnection mode.
As shown in fig. 3, the specific process for fabricating the P + voltage-withstanding region 200 is: the epitaxial layer 100 is subjected to processes such as photoetching, etching, cleaning, ion implantation and the like, and then enters a furnace tube for field oxygen growth and high-temperature junction pushing to form a P + pressure-resistant area 200.
As shown in fig. 4 and 5, optionally, the epitaxial layer 100 has a first trench 110 and a second trench 120;
the first trench 110 and the second trench 120 are located on both sides of the P + voltage-resistant region 200;
a first polysilicon gate layer 300 is arranged in the first trench 110, and a second polysilicon gate layer 400 is arranged in the second trench 120;
an oxide layer 800 is disposed between the inner wall of the first trench 110 and the first polysilicon gate layer 300, and an oxide layer 800 is disposed between the inner wall of the second trench 120 and the second polysilicon gate layer 400.
Specifically, the photoresist is coated, an AA photomask is used for exposure and development, then etching is performed, the oxide layer 800 is deposited after etching, then the photoresist is coated, a Trench photomask is used for exposure and development, then Trench etching is performed, the oxide layer 800 is removed after etching is completed, and then the gate oxide layer 800 grows.
After the steps are completed, a layer of polycrystalline silicon is deposited, then glue is coated, a Poly photolithography mask is used for exposure and development, and then the polycrystalline silicon is etched. Thereby forming a first polysilicon gate layer 300 and a second polysilicon gate layer 400, and a polysilicon connection lead layer 500 for connecting the first polysilicon gate layer 300 and the second polysilicon gate layer 400.
As shown in fig. 6, the Pbody region 900 is formed outside the first trench 110 and the second trench 120 away from the P + voltage-withstand region 200.
An N + emitter region 1000 is formed on a side of the Pbody region 900 facing away from the epitaxial layer 100.
And performing B ion implantation, then entering a furnace tube for knot pushing, and then performing As ion implantation to form an N + emission region 1000.
Specifically, the specific operations of the silicon dioxide layer 600 formed on the side of the polysilicon connecting lead layer 500 away from the epitaxial layer 100 are: depositing a layer of silicon dioxide on the surface, and carrying out high-temperature reflux.
As shown in fig. 7, a connection hole 610 is formed in the silicon dioxide layer 600 to expose the polysilicon connection lead layer 500; the specific operation steps of the connecting hole 610 are as follows: after the silicon dioxide layer 600 is finished, gluing, exposing and developing by using a Contact photolithography mask, and then etching the oxide layer 800 to manufacture a connecting hole 610; then, metal deposition is performed to form the metal layer 700 on the side of the silicon dioxide layer 600 away from the epitaxial layer 100, so as to connect the metal layer 700 with the polysilicon connection lead layer 500. And coating glue after the deposition is finished, and carrying out exposure and development by using a Metal photomask and then etching to form the grid electrode and the emitter electrode.
Referring to fig. 8, the back surface of the epitaxial layer 100 is thinned, P ion implantation is performed to form a field stop layer 1100 after the thinning is completed, then B ion implantation is performed to form a P + collector region 1200, and then metal is deposited to form a metal electrode layer 1300.
In a second aspect, the present invention provides a power semiconductor device, including: the cellular structure of any one of the first aspect.
In a second aspect, an electronic device includes: the cellular structure of any one of the first aspect.
It will be apparent to those skilled in the art that various changes and modifications may be made to the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. A cellular structure, comprising:
an epitaxial layer;
a P + voltage-resistant region formed on one side of the epitaxial layer;
the first polysilicon gate layer and the second polysilicon gate layer are positioned on two sides of the P + voltage-withstanding region;
the polycrystalline silicon connecting lead layer is formed on one side, away from the epitaxial layer, of the P + voltage-withstanding region and is used for connecting the first polycrystalline silicon gate layer with the second polycrystalline silicon gate layer;
the silicon dioxide layer is formed on one side, away from the epitaxial layer, of the polycrystalline silicon connecting lead layer, and a connecting hole is formed in the silicon dioxide layer so that the polycrystalline silicon connecting lead layer is exposed;
and the metal layer is formed on one side of the silicon dioxide layer, which is far away from the epitaxial layer, so that the metal layer is connected with the polycrystalline silicon connecting lead layer.
2. The cell structure of claim 1, wherein the epitaxial layer has a first trench and a second trench;
the first groove and the second groove are positioned on two sides of the P + voltage-resistant area;
the first polycrystalline silicon gate layer is arranged in the first groove, and the second polycrystalline silicon gate layer is arranged in the second groove;
an oxide layer is arranged between the inner wall of the first groove and the first polycrystalline silicon grid layer, and an oxide layer is arranged between the inner wall of the second groove and the second polycrystalline silicon grid layer.
3. The cellular structure of claim 2, further comprising: and the Pbody area is formed outside the first groove and the second groove which are far away from the P + voltage-resisting area.
4. The cellular structure of claim 3, further comprising: and an N + emission region formed on the side of the Pbody region, which faces away from the epitaxial layer.
5. The cellular structure of claim 4, further comprising: and the field stop layer is formed on one side of the epitaxial layer, which is far away from the P + voltage-resistant area.
6. The cellular structure of claim 5, further comprising: and the P + collector region is formed on one side, away from the epitaxial layer, of the field stop layer.
7. The cellular structure of claim 6, further comprising: and the metal electrode layer is formed on one side of the P + collector region, which is far away from the epitaxial layer.
8. A power semiconductor device, comprising: the cellular structure of any one of claims 1-7.
9. An electronic device, comprising: the cellular structure of any one of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022753217.3U CN213212170U (en) | 2020-11-24 | 2020-11-24 | Cellular structure, power semiconductor device and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022753217.3U CN213212170U (en) | 2020-11-24 | 2020-11-24 | Cellular structure, power semiconductor device and electronic equipment |
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| Publication Number | Publication Date |
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| CN213212170U true CN213212170U (en) | 2021-05-14 |
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| CN202022753217.3U Active CN213212170U (en) | 2020-11-24 | 2020-11-24 | Cellular structure, power semiconductor device and electronic equipment |
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