CN104637793A - Manufacturing method of terminal structure of silicon carbide device - Google Patents
Manufacturing method of terminal structure of silicon carbide device Download PDFInfo
- Publication number
- CN104637793A CN104637793A CN201410857086.XA CN201410857086A CN104637793A CN 104637793 A CN104637793 A CN 104637793A CN 201410857086 A CN201410857086 A CN 201410857086A CN 104637793 A CN104637793 A CN 104637793A
- Authority
- CN
- China
- Prior art keywords
- mask material
- silicon carbide
- groove
- etching
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 127
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 125
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 239000000463 material Substances 0.000 claims abstract description 227
- 239000000758 substrate Substances 0.000 claims abstract description 116
- 238000005530 etching Methods 0.000 claims abstract description 63
- 230000007704 transition Effects 0.000 claims abstract description 25
- 238000004140 cleaning Methods 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 72
- 239000004065 semiconductor Substances 0.000 claims description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 18
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 18
- 239000002131 composite material Substances 0.000 claims description 13
- 238000010276 construction Methods 0.000 claims description 13
- 238000001039 wet etching Methods 0.000 claims description 13
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- 239000004411 aluminium Substances 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 9
- 239000011651 chromium Substances 0.000 claims description 9
- 229910052804 chromium Inorganic materials 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 239000010931 gold Substances 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 229910052697 platinum Inorganic materials 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 229910052709 silver Inorganic materials 0.000 claims description 9
- 239000004332 silver Substances 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- 239000010937 tungsten Substances 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 8
- 239000004642 Polyimide Substances 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 abstract description 10
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract 2
- 238000001020 plasma etching Methods 0.000 description 47
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 44
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 34
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 30
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 30
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 30
- 239000000460 chlorine Substances 0.000 description 30
- 238000009616 inductively coupled plasma Methods 0.000 description 30
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 24
- 230000005684 electric field Effects 0.000 description 21
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 20
- 229910052786 argon Inorganic materials 0.000 description 17
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 17
- 239000001301 oxygen Substances 0.000 description 17
- 229910052760 oxygen Inorganic materials 0.000 description 17
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 15
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 15
- 229910052801 chlorine Inorganic materials 0.000 description 15
- 238000010586 diagram Methods 0.000 description 15
- 239000001307 helium Substances 0.000 description 15
- 229910052734 helium Inorganic materials 0.000 description 15
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 15
- 230000001939 inductive effect Effects 0.000 description 15
- 238000010884 ion-beam technique Methods 0.000 description 15
- 238000000608 laser ablation Methods 0.000 description 15
- 238000003801 milling Methods 0.000 description 15
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 15
- 229910052757 nitrogen Inorganic materials 0.000 description 15
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 15
- 229960000909 sulfur hexafluoride Drugs 0.000 description 15
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 15
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 12
- IXCSERBJSXMMFS-UHFFFAOYSA-N hcl hcl Chemical compound Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 12
- 229960002163 hydrogen peroxide Drugs 0.000 description 12
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 10
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 10
- 238000005260 corrosion Methods 0.000 description 10
- 230000007797 corrosion Effects 0.000 description 10
- 239000007788 liquid Substances 0.000 description 10
- 229910017604 nitric acid Inorganic materials 0.000 description 10
- 238000004544 sputter deposition Methods 0.000 description 9
- 230000008020 evaporation Effects 0.000 description 7
- 238000001704 evaporation Methods 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- 238000007747 plating Methods 0.000 description 7
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 6
- 230000007423 decrease Effects 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 238000010894 electron beam technology Methods 0.000 description 5
- 238000001459 lithography Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000008236 heating water Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
Abstract
The invention provides a manufacturing method of a terminal structure of a silicon carbide device. The manufacturing method comprises the following steps of cleaning a silicon carbide substrate; depositing a first mask material; patterning the first mask material; depositing a second mask material; patterning the second mask material; etching the silicon carbide substrate to form a first groove and forming circular arc transition structures at corners of the bottom and the side wall of the first groove; removing the second mask material; etching the silicon carbide substrate to form a second groove and forming circular arc transition structures at corners of the bottom and the side wall of the second groove and at the corners of the bottom of the second groove and the side wall of the first groove, wherein the side wall of the second groove is approximately vertical and is approximately at a right angle with the surface of the silicon carbide substrate; removing the first mask material. By the manufacturing method of the terminal structure of the silicon carbide device, the step height of a photoetching technology in the manufacturing process can be effectively reduced and pattern line accuracy is improved; the manufacturing method is beneficial for reducing a chip area occupied by the terminal structure.
Description
[technical field]
The present invention relates to a kind of manufacture method of microelectronic component, specifically relate to a kind of manufacture method of edge termination structure of silicon carbide device.
[background technology]
Relative to taking silicon as the first generation semiconductor of representative and taking GaAs the second generation semiconductor of representative, the carborundum of third generation semiconductor and gallium nitride have larger energy gap and critical breakdown electric field, are comparatively applicable to manufacturing high temperature high power semiconductor device.At present, silicon carbide power device is international research and development focus.
For power device, edge terminal (edge termination) is needed to carry out good design.The edge termination of appropriate design is not only the key guaranteeing power device voltage endurance capability, is also the pith of guaranteed output device reliably working.Conventional silicon carbide device edge termination structure has field limiting ring (field limiting ring, FLR), tie terminal and extend (junction termination extension, and field plate (field plate, FP) etc. JTE).
Field limiting ring (FLR) is a kind of conventional power device edge termination structure, and this structure can make with the main interface of device simultaneously, and thus manufacturing step is simple, with low cost.But field limiting ring structure is very responsive for oxide-semiconductor interface electric charge.This problem is even more serious in silicon carbide device, because field oxide adopts the mode of deposition to make usually.In general, deposited oxide layer is lower than the quality of thermal growth oxide layer, and its carborundum-oxide interface has the charge density larger than silicon device.
It is a kind of very effective power device edge termination structure that knot terminal extends (JTE), can reduce the electric field being gathered in fringe region, reduces the interaction of depletion region and device surface.But knot terminal extends implantation dosage change very responsive, needs strictly to control the product of Effective Doping concentration and junction depth.And the photoetching of increase and implantation step can increase manufacturing cost.
Field plate (FP) is also a kind of conventional power device edge termination structure.In the field plate edge termination structure of routine, bear high electric field by the oxide layer under Metal field plate.This structure is applied in the relatively low silicon device of maximum electric field intensity, has good effect.But in silicon carbide power device, the maximum electric field intensity due to carborundum is very high (about 2MV/cm), and this bears higher electric field by causing oxide layer, and will cause integrity problem.Therefore, field plate edge termination structure is not suitable for silicon carbide power device.
[summary of the invention]
For the problems referred to above, the invention provides a kind of method adopting etching technics to make silicon carbide power device edge termination, photoetching process shoulder height can be reduced, improve pattern line precision, meanwhile, simplification of flowsheet, reduce manufacturing cost, be applicable to mass production.
For achieving the above object, the technical solution used in the present invention is as follows:
A manufacture method for silicon carbide device terminal structure, comprises the following steps successively:
S101. cleaning sic substrate, described silicon carbide substrates comprises the first and second surfaces;
S102. deposit the first mask material, described first mask material covers the first surface of described silicon carbide substrates;
S103. the first mask material is graphical, exposes the first surface of partially carbonized silicon substrate;
S104. the second mask material is deposited, the first mask material of described second mask material cover graphics and the silicon carbide substrates first surface exposed;
S105. the second mask material is graphical, exposes the first surface of partially carbonized silicon substrate, the first mask material of the part or all of cover graphics of described patterned second mask material;
S106. etching silicon carbide substrate forms the first groove, and the corner of described first bottom portion of groove and sidewall forms circular arc transition structure;
S107. remove the second mask material, expose the first surface of patterned first mask material and silicon carbide substrates;
S108. etching silicon carbide substrate forms the second groove;
S109. the first mask material is removed.
Preferably, formed in the second groove at described step S108 etching silicon carbide substrate, the corner of described second bottom portion of groove and sidewall and the corner of the second bottom portion of groove and the first recess sidewall form circular arc transition structure.
Preferably, formed in the second groove at described step S108 etching silicon carbide substrate, the second recess sidewall near normal, is approximated to right angle with silicon carbide substrates first surface, and the angle namely between the second recess sidewall and silicon carbide substrates first surface is 80 ~ 95 °.
Preferably, remove in the second mask material at described step S107, optionally remove the second mask material, and do not damage the first mask material and silicon carbide substrates.
Preferably, after described step S105 second mask material is graphical, also comprise step: deposition the 3rd mask material is also graphical, the second mask material of the part or all of cover graphics of described patterned 3rd mask material and the first mask material.
Preferably, before described step S106 etching silicon carbide substrate forms the first groove, also comprise step: etching silicon carbide substrate forms the 3rd groove, remove the 3rd mask material.
Preferably, before each etching silicon carbide substrate step, also comprise wet etching or dry etching mask material, form the transition pattern of the arc-shaped of mild projection at mask material edge.
Preferably, described silicon carbide substrates is nude film, or comprise different doped regions, described doped region is N-shaped or p-type doping, different regions has different doping contents, or comprising epitaxial loayer at the first surface of substrate and/or second surface, described epitaxial loayer is N-shaped or p-type, and different epitaxial layer region has different doping contents.
Preferably, the first surface of described silicon carbide substrates and/or second surface comprise insulating barrier and/or metal level, described insulating barrier is silica, silicon nitride, polyimides or its composite construction, described metal level and manufacturing silicon carbide semiconductor surface form Schottky contacts and/or ohmic contact, and described metal level is tungsten, chromium, platinum, titanium, silver, gold, aluminium, nickel, copper or its alloy and composite construction.
With immediate prior art ratio, beneficial effect of the present invention is:
1, successive sedimentation also first, second mask material graphical, then silicon carbide substrates etching is carried out, avoid in silicon carbide substrates after etching and carry out photoetching process, significantly reduce the shoulder height of photoetching process in manufacturing process, pattern line precision can be improved, be conducive to the chip area that reduction terminal structure takies;
2, in inside lock and the outer corner formation circular arc transition structure of etching step, decrease electric field and gather, electric fields uniform is distributed, be conducive to the withstand voltage improving power device;
3, form approximate right angle and vertical sidewall at etching step with silicon carbide substrate surface place, avoid the formation of negative angle bevel termination, make Electric Field Distribution even, be conducive to the withstand voltage improving power device;
4, simplify technological process, reduce manufacturing cost, be applicable to mass production;
5, the withstand voltage of device can improve about 7%, and the process window of all right extended device processing simultaneously, improves the consistency of device performance.。
[accompanying drawing explanation]
Fig. 1 is the flow chart of the inventive method;
Fig. 2 is the schematic diagram of the silicon carbide substrates provided in embodiment 1;
Fig. 3 makes the first mask material in embodiment 1 and patterned schematic diagram on silicon carbide substrates;
Fig. 4 makes the second mask material in embodiment 1 and patterned schematic diagram on silicon carbide substrates;
Fig. 5 is the schematic diagram that in embodiment 1, etching silicon carbide substrate forms the first groove;
Fig. 6 is the schematic diagram of the second mask material removed in embodiment 1 in silicon carbide substrates;
Fig. 7 is the schematic diagram that in embodiment 1, etching silicon carbide substrate forms the second groove;
Fig. 8 is the schematic diagram of the first mask material removed in embodiment 1 in silicon carbide substrates;
Fig. 9 is the schematic diagram of the silicon carbide substrates provided in embodiment 2;
Figure 10 makes the first mask material in embodiment 2 and patterned schematic diagram on silicon carbide substrates;
Figure 11 makes the second mask material in embodiment 2 and patterned schematic diagram on silicon carbide substrates;
Figure 12 makes the 3rd mask material and patterned schematic diagram on silicon carbide substrates in embodiment 2;
Figure 13 is that in embodiment 2, etching silicon carbide substrate forms the first groove and removes the schematic diagram of the 3rd mask material;
Figure 14 is that in embodiment 2, etching silicon carbide substrate forms the second groove and removes the schematic diagram of the second mask material;
Figure 15 is that in embodiment 2, etching silicon carbide substrate forms the 3rd groove and removes the schematic diagram of the first mask material;
Figure 16 is the silicon carbide diode device of the terminal structure that the employing embodiment of the present invention of emulation provides and the puncture voltage comparison diagram adopting routine to etch terminal part.。
[embodiment]
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples for illustration of the present invention, but do not limit the scope of the invention.
As shown in Figure 1, silicon carbide device terminal structure manufacture method of the present invention, comprises step: S101. cleaning sic substrate, and described silicon carbide substrates comprises the first and second surfaces; S102. deposit the first mask material, described first mask material covers the first surface of described silicon carbide substrates; S103. the first mask material is graphical, exposes the first surface of partially carbonized silicon substrate; S104. the second mask material is deposited, the first mask material of described second mask material cover graphics and the silicon carbide substrates first surface exposed; S105. the second mask material is graphical, exposes the first surface of partially carbonized silicon substrate, the first mask material of the part or all of cover graphics of described patterned second mask material; S106. etching silicon carbide substrate forms the first groove, and the corner of described first bottom portion of groove and sidewall forms circular arc transition structure; S107. remove the second mask material, expose the first surface of patterned first mask material and silicon carbide substrates; S108. etching silicon carbide substrate forms the second groove, the corner of described second bottom portion of groove and sidewall and the corner of the second bottom portion of groove and the first recess sidewall form circular arc transition structure, second recess sidewall near normal, is approximated to right angle with silicon carbide substrates first surface; S109. the first mask material is removed.
In one embodiment, after described step S105 second mask material is graphical, also step is comprised: deposition the 3rd mask material is also graphical.
In another embodiment, before described step S106 etching silicon carbide substrate forms the first groove, also comprise step: etching silicon carbide substrate forms the 3rd groove, remove the 3rd mask material.
In another embodiment, before each etching silicon carbide substrate step, also comprise wet etching or dry etching mask material, form mild transition pattern at mask material edge.
Embodiment 1:
1) first, as shown in Figure 2, a silicon carbide semiconductor substrate 110 is provided, silicon carbide semiconductor substrate 110 is cleaned.Cleaning can use the methods such as the oxidation of ultrasonic, plasma etching, sacrifice, heating water bath or hot plate heating, and the material of use comprises ammoniacal liquor NH
4oH, oxydol H
2o
2, hydrochloric acid HCl, sulfuric acid H
2sO
4, acetone, isopropyl alcohol, deionized water, argon Ar, oxygen O
2, hydrofluoric acid HF or above-mentioned two kinds and above material mixture etc., but be not limited to above-mentioned material and method.
Silicon carbide semiconductor substrate 110 can be standard thickness, from 400 microns to 1000 microns not etc., also can be through thinning, and thickness is not from 10 microns to 400 microns etc.Silicon carbide semiconductor substrate 110 has first surface 111 and second surface 112.Silicon carbide semiconductor substrate 110 can comprise different doped regions, does not illustrate in the drawings.Described doped region can be N-shaped or p-type doping, and different regions can have different doping contents, from 1 × 10
14/ cm
3to 1 × 10
19/ cm
3not etc.Doped region adopts the mode of high temperature tension to make usually, and by high-temperature annealing activation foreign ion.First surface 111 and the second surface 112 of silicon carbide semiconductor substrate 110 can comprise epitaxial loayer, do not illustrate in the drawings.Epitaxial loayer comprises N-shaped and p-type, and different epitaxial layer region can have different doping contents, from 1 × 10
14/ cm
3to 1 × 10
17/ cm
3not etc.First surface 111 and the second surface 112 of silicon carbide semiconductor substrate 110 can comprise insulating barrier, do not illustrate in the drawings.Thickness of insulating layer is not from 0.1 micron to 10 microns etc., it can be oxide, nitride, organic substance or its composite construction, comprise silica, silicon nitride, the materials such as polyimides, ald (atomic layer deposition can be adopted, ALD), low-pressure chemical vapor deposition (low pressure chemical vapor deposition, LPCVD), plasma reinforced chemical vapour deposition (plasma enhanced chemical vapor deposition, PECVD), the modes such as sputtering or heat growth make, but be not limited to above-mentioned material and manufacture method.First surface 111 and the second surface 112 of silicon carbide semiconductor substrate 110 can also comprise metal level, do not illustrate in the drawings.Metal layer thickness from 0.1 micron to 10 microns not etc., can define Schottky contacts or ohmic contact with manufacturing silicon carbide semiconductor surface.Metal level can be tungsten, chromium, platinum, titanium, silver, gold, aluminium, nickel, copper and alloy thereof or its composite construction, the modes such as evaporation, sputtering or plating can be adopted to make, but be not limited to above-mentioned material and manufacture method.
2) then, the first surface 111 of silicon carbide semiconductor substrate 110 deposits the first mask material 120, described first mask material 120 covers the first surface 111 of silicon carbide semiconductor substrate 110.Described first mask material 120 thickness is not from 0.1 micron to 10 microns etc., can be metal, oxide, nitride, nitrogen oxide or its composite construction, comprise the materials such as tungsten, chromium, platinum, titanium, silver, gold, aluminium, nickel, copper, polysilicon, silica, silicon nitride or silicon oxynitride, the modes such as evaporation, sputtering or plating can be adopted to make, but be not limited to above-mentioned material and manufacture method.
3) then, as shown in Figure 3, carry out graphically, exposing the first surface 111 of partially carbonized silicon semiconductor substrate 110 to the first mask material 120.The graphic method of described first mask material 120 comprises the steps such as photoetching, corrosion or etching.Described lithography step comprises to be made to wait material with photoresist, adopts the modes such as ultraviolet light, laser or electron beam, produces required figure.Described lithographic method comprises reactive ion etching (reactive ion etching, RIE), inductively coupled plasma (inductive coupled plasma, ICP) etching, laser ablation or ion beam millings etc., the material of use comprises argon Ar, oxygen O
2, nitrogen N
2, helium He, chlorine Cl
2, sulphur hexafluoride SF
6, carbon tetrafluoride CF
4, fluoroform CHF
3, Nitrogen trifluoride NF
3deng, but be not limited to above-mentioned different materials.The material that described wet etching method uses comprises phosphoric acid H
3pO
4, hydrofluoric acid HF, buffered hydrofluoric acid BOE, sulfuric acid H
2sO
4, nitric acid HNO
3, hydrochloric acid HCl, acetic acid CH
3cOOH, oxydol H
2o
2deng, the corrosive liquid of variable concentrations proportioning is selected according to different materials.
4) then, the second mask material 130 is deposited, the first mask material 120 of cover graphics and the silicon carbide substrates first surface 111 exposed.Described second mask material 130 thickness is not from 0.1 micron to 10 microns etc., can be metal, oxide, nitride, nitrogen oxide or its composite construction, comprise the materials such as tungsten, chromium, platinum, titanium, silver, gold, aluminium, nickel, copper, polysilicon, silica, silicon nitride or silicon oxynitride, the modes such as evaporation, sputtering or plating can be adopted to make, but be not limited to above-mentioned material and manufacture method.Described second mask material 130 can select different materials from the first mask material 120, optionally can remove the second mask material 130, and not remove the first mask material 120.
5) then, as shown in Figure 4, carry out graphically, exposing the first surface 111 of partially carbonized silicon substrate to the second mask material 130, the first mask material 120 of the part or all of cover graphics of described patterned second mask material 130.The graphic method of described second mask material 130 comprises the steps such as photoetching, corrosion or etching.Described lithography step comprises to be made to wait material with photoresist, adopts the modes such as ultraviolet light, laser or electron beam, produces required figure.Described lithographic method comprises reactive ion etching (reactive ion etching, RIE), inductively coupled plasma (inductive coupled plasma, ICP) etching, laser ablation or ion beam millings etc., the material of use comprises argon Ar, oxygen O
2, nitrogen N
2, helium He, chlorine Cl
2, sulphur hexafluoride SF
6, carbon tetrafluoride CF
4, fluoroform CHF
3, Nitrogen trifluoride NF
3deng, but be not limited to above-mentioned different materials.The material that described wet etching method uses comprises phosphoric acid H
3pO
4, hydrofluoric acid HF, buffered hydrofluoric acid BOE, sulfuric acid H
2sO
4, nitric acid HNO
3, hydrochloric acid HCl, acetic acid CH
3cOOH, oxydol H
2o
2deng, the corrosive liquid of variable concentrations proportioning is selected according to different materials.
6) then, as shown in Figure 5, etching silicon carbide Semiconductor substrate 110 forms the first groove 113, and the corner of described first bottom portion of groove and sidewall forms circular arc transition structure 114.Described circular arc transition structure 114 decreases electric field and gathers, and electric fields uniform is distributed, and is conducive to the withstand voltage improving power device.The degree of depth of described first groove 113 is not from 0.5 micron to 50 microns etc.Described lithographic method comprises reactive ion etching (reactive ion etching, RIE), inductively coupled plasma (inductive coupled plasma, ICP) etching, laser ablation or ion beam millings etc., the material of use comprises argon Ar, oxygen O
2, nitrogen N
2, helium He, chlorine Cl
2, sulphur hexafluoride SF
6, carbon tetrafluoride CF
4, fluoroform CHF
3, Nitrogen trifluoride NF
3deng, but be not limited to above-mentioned different materials.
7) then, as shown in Figure 6, remove the second mask material 130, expose the first surface 111 of patterned first mask material 120 and silicon carbide substrates.The method removing the second mask material 130 comprises the steps such as corrosion or etching, optionally can remove the second mask material 130, and not remove the first mask material 120.Described lithographic method comprises reactive ion etching (reactive ion etching, RIE), inductively coupled plasma (inductive coupled plasma, ICP) etching, laser ablation or ion beam millings etc., the material of use comprises argon Ar, oxygen O
2, nitrogen N
2, helium He, chlorine Cl
2, sulphur hexafluoride SF
6, carbon tetrafluoride CF
4, fluoroform CHF
3, Nitrogen trifluoride NF
3deng, but be not limited to above-mentioned different materials.The material that described wet etching method uses comprises phosphoric acid H
3pO
4, hydrofluoric acid HF, buffered hydrofluoric acid BOE, sulfuric acid H
2sO
4, nitric acid HNO
3, hydrochloric acid HCl, acetic acid CH
3cOOH, oxydol H
2o
2deng, the corrosive liquid of variable concentrations proportioning is selected according to different materials.
8) then, as shown in Figure 7, etching silicon carbide Semiconductor substrate 110 forms the second groove 115, the corner 116 of described second bottom portion of groove and sidewall and the corner 117 of the second bottom portion of groove and the first recess sidewall form circular arc transition structure, second recess sidewall near normal, is approximated to right angle 118 with silicon carbide substrates first surface.Described circular arc transition structure 116 and 117 decreases electric field and gathers, and electric fields uniform is distributed, and is conducive to the withstand voltage improving power device.Described second recess sidewall near normal, is approximated to right angle 118 with silicon carbide substrates first surface, avoids the formation of negative angle bevel termination, makes Electric Field Distribution even, is also conducive to the withstand voltage improving power device.The degree of depth of described second groove 115 is not from 0.5 micron to 50 microns etc.Described lithographic method comprises reactive ion etching (reactive ion etching, RIE), inductively coupled plasma (inductive coupled plasma, ICP) etching, laser ablation or ion beam millings etc., the material of use comprises argon Ar, oxygen O
2, nitrogen N
2, helium He, chlorine Cl
2, sulphur hexafluoride SF
6, carbon tetrafluoride CF
4, fluoroform CHF
3, Nitrogen trifluoride NF
3deng, but be not limited to above-mentioned different materials.
9) then, as shown in Figure 8, remove the first mask material 120, expose the first surface 111 of silicon carbide substrates.The method removing the first mask material 120 comprises the steps such as corrosion or etching, optionally can remove the first mask material 120, and not damage silicon carbide substrates 110.Described lithographic method comprises reactive ion etching (reactive ion etching, RIE), inductively coupled plasma (inductive coupled plasma, ICP) etching, laser ablation or ion beam millings etc., the material of use comprises argon Ar, oxygen O
2, nitrogen N
2, helium He, chlorine Cl
2, sulphur hexafluoride SF
6, carbon tetrafluoride CF
4, fluoroform CHF
3, Nitrogen trifluoride NF
3deng, but be not limited to above-mentioned different materials.The material that described wet etching method uses comprises phosphoric acid H
3pO
4, hydrofluoric acid HF, buffered hydrofluoric acid BOE, sulfuric acid H
2sO
4, nitric acid HNO
3, hydrochloric acid HCl, acetic acid CH
3cOOH, oxydol H
2o
2deng, the corrosive liquid of variable concentrations proportioning is selected according to different materials.
10) then, other processing steps of silicon carbide power device making can be carried out, comprising the combination of any order of a step in the steps such as insulating barrier making, passivation layer making, metal electrode making, scribing or some steps, also can be the manufacture craft of other silicon carbide power devices.Do not repeat them here.
As shown in figure 16, application business software TCAD simulates adopting the silicon carbide diode device of terminal structure provided by the invention, and contrasts with adopting the conventional device etching terminal.From simulation result, for different etching terminal length, adopt device terminal structure provided by the invention, at least the withstand voltage of silicon carbide diode device can be improved about 7%.This shows, adopt device terminal structure provided by the invention, larger withstand voltage surplus can be provided for power device, thus ensure that stability and the reliability of power device.
Embodiment 2:
1) first, as shown in Figure 9, a silicon carbide semiconductor substrate 210 is provided, silicon carbide semiconductor substrate 210 is cleaned.Cleaning can use the methods such as the oxidation of ultrasonic, plasma etching, sacrifice, heating water bath or hot plate heating, and the material of use comprises ammoniacal liquor NH
4oH, oxydol H
2o
2, hydrochloric acid HCl, sulfuric acid H
2sO
4, acetone, isopropyl alcohol, deionized water, argon Ar, oxygen O
2, hydrofluoric acid HF or above-mentioned two kinds and above material mixture etc., but be not limited to above-mentioned material and method.
Silicon carbide semiconductor substrate 210 can be standard thickness, from 400 microns to 1000 microns not etc., also can be through thinning, and thickness is not from 10 microns to 400 microns etc.Silicon carbide semiconductor substrate 210 has first surface 211 and second surface 212.Silicon carbide semiconductor substrate 210 is N-shaped, comprises p-type doped region 220.Described doped region 220 can have uneven doping content, from 1 × 10
14/ cm
3to 1 × 10
19/ cm
3not etc.The degree of depth of described doped region 220 is not from 0.05 micron to 5 microns etc.Doped region adopts the mode of high temperature tension to make usually, and by high-temperature annealing activation foreign ion.First surface 211 and the second surface 212 of silicon carbide semiconductor substrate 210 can comprise epitaxial loayer, do not illustrate in the drawings.Epitaxial loayer comprises N-shaped and p-type, and different epitaxial layer region can have different doping contents, from 1 × 10
14/ cm
3to 1 × 10
17/ cm
3not etc.First surface 211 and the second surface 212 of silicon carbide semiconductor substrate 210 can comprise insulating barrier, do not illustrate in the drawings.Thickness of insulating layer is not from 0.1 micron to 10 microns etc., it can be oxide, nitride, organic substance or its composite construction, comprise silica, silicon nitride, the materials such as polyimides, ald (atomic layer deposition can be adopted, ALD), low-pressure chemical vapor deposition (low pressure chemical vapor deposition, LPCVD), plasma reinforced chemical vapour deposition (plasma enhanced chemical vapor deposition, PECVD), the modes such as sputtering or heat growth make, but be not limited to above-mentioned material and manufacture method.First surface 211 and the second surface 212 of silicon carbide semiconductor substrate 210 can also comprise metal level, do not illustrate in the drawings.Metal layer thickness from 0.1 micron to 10 microns not etc., can define Schottky contacts or ohmic contact with manufacturing silicon carbide semiconductor surface.Metal level can be tungsten, chromium, platinum, titanium, silver, gold, aluminium, nickel, copper and alloy thereof or its composite construction, the modes such as evaporation, sputtering or plating can be adopted to make, but be not limited to above-mentioned material and manufacture method.
2) then, as shown in Figure 10, the first surface 211 of silicon carbide semiconductor substrate 210 deposits the first mask material 230, and carry out graphically, exposing the first surface 211 of partially carbonized silicon semiconductor substrate 210 to the first mask material 230.Described first mask material 230 thickness is not from 0.1 micron to 10 microns etc., can be metal, oxide, nitride, nitrogen oxide or its composite construction, comprise the materials such as tungsten, chromium, platinum, titanium, silver, gold, aluminium, nickel, copper, polysilicon, silica, silicon nitride or silicon oxynitride, the modes such as evaporation, sputtering or plating can be adopted to make, but be not limited to above-mentioned material and manufacture method.
The graphic method of described first mask material 230 comprises the steps such as photoetching, corrosion or etching.Described lithography step comprises to be made to wait material with photoresist, adopts the modes such as ultraviolet light, laser or electron beam, produces required figure.Described lithographic method comprises reactive ion etching (reactive ion etching, RIE), inductively coupled plasma (inductive coupled plasma, ICP) etching, laser ablation or ion beam millings etc., the material of use comprises argon Ar, oxygen O
2, nitrogen N
2, helium He, chlorine Cl
2, sulphur hexafluoride SF
6, carbon tetrafluoride CF
4, fluoroform CHF
3, Nitrogen trifluoride NF
3deng, but be not limited to above-mentioned different materials.The material that described wet etching method uses comprises phosphoric acid H
3pO
4, hydrofluoric acid HF, buffered hydrofluoric acid BOE, sulfuric acid H
2sO
4, nitric acid HNO
3, hydrochloric acid HCl, acetic acid CH
3cOOH, oxydol H
2o
2deng, the corrosive liquid of variable concentrations proportioning is selected according to different materials.Described graphic method can form mild transition pattern at mask material edge.
3) then, as shown in figure 11, deposit the second mask material 240, the first mask material 230 of cover graphics and the silicon carbide substrates first surface 211 exposed, and carry out graphically, exposing the first surface 211 of partially carbonized silicon substrate to the second mask material 240.First mask material 230 of the part or all of cover graphics of described patterned second mask material 240.Described second mask material 240 thickness is not from 0.1 micron to 10 microns etc., can be metal, oxide, nitride, nitrogen oxide or its composite construction, comprise the materials such as tungsten, chromium, platinum, titanium, silver, gold, aluminium, nickel, copper, polysilicon, silica, silicon nitride or silicon oxynitride, the modes such as evaporation, sputtering or plating can be adopted to make, but be not limited to above-mentioned material and manufacture method.Described second mask material 240 can select different materials from the first mask material 230, optionally can remove the second mask material 240, and not remove the first mask material 230.
The graphic method of described second mask material 240 comprises the steps such as photoetching, corrosion or etching.Described lithography step comprises to be made to wait material with photoresist, adopts the modes such as ultraviolet light, laser or electron beam, produces required figure.Described lithographic method comprises reactive ion etching (reactive ion etching, RIE), inductively coupled plasma (inductive coupled plasma, ICP) etching, laser ablation or ion beam millings etc., the material of use comprises argon Ar, oxygen O
2, nitrogen N
2, helium He, chlorine Cl
2, sulphur hexafluoride SF
6, carbon tetrafluoride CF
4, fluoroform CHF
3, Nitrogen trifluoride NF
3deng, but be not limited to above-mentioned different materials.The material that described wet etching method uses comprises phosphoric acid H
3pO
4, hydrofluoric acid HF, buffered hydrofluoric acid BOE, sulfuric acid H
2sO
4, nitric acid HNO
3, hydrochloric acid HCl, acetic acid CH
3cOOH, oxydol H
2o
2deng, the corrosive liquid of variable concentrations proportioning is selected according to different materials.Described graphic method can form mild transition pattern at mask material edge.
4) then, as shown in figure 12, deposit the 3rd mask material 250, first mask material 230 of cover graphics, patterned second mask material 240 and the silicon carbide substrates first surface 211 exposed, and carry out graphically, exposing the first surface 211 of partially carbonized silicon substrate to the 3rd mask material 250.Second mask material 240 of the part or all of cover graphics of described patterned 3rd mask material 250 and patterned first mask material 230.Described 3rd mask material 250 thickness is not from 0.1 micron to 10 microns etc., can be metal, oxide, nitride, nitrogen oxide or its composite construction, comprise the materials such as tungsten, chromium, platinum, titanium, silver, gold, aluminium, nickel, copper, polysilicon, silica, silicon nitride or silicon oxynitride, the modes such as evaporation, sputtering or plating can be adopted to make, but be not limited to above-mentioned material and manufacture method.Described 3rd mask material 250 can select different materials from the second mask material 240, first mask material 230, optionally can remove the 3rd mask material 250, and not remove the second mask material 240.
The graphic method of described 3rd mask material 250 comprises the steps such as photoetching, corrosion or etching.Described lithography step comprises to be made to wait material with photoresist, adopts the modes such as ultraviolet light, laser or electron beam, produces required figure.Described lithographic method comprises reactive ion etching (reactive ion etching, RIE), inductively coupled plasma (inductive coupled plasma, ICP) etching, laser ablation or ion beam millings etc., the material of use comprises argon Ar, oxygen O
2, nitrogen N
2, helium He, chlorine Cl
2, sulphur hexafluoride SF
6, carbon tetrafluoride CF
4, fluoroform CHF
3, Nitrogen trifluoride NF
3deng, but be not limited to above-mentioned different materials.The material that described wet etching method uses comprises phosphoric acid H
3pO
4, hydrofluoric acid HF, buffered hydrofluoric acid BOE, sulfuric acid H
2sO
4, nitric acid HNO
3, hydrochloric acid HCl, acetic acid CH
3cOOH, oxydol H
2o
2deng, the corrosive liquid of variable concentrations proportioning is selected according to different materials.Described graphic method can form mild transition pattern at mask material edge.
5) then, as shown in figure 13, etching silicon carbide Semiconductor substrate 210 forms the first groove 260, the corner of described first bottom portion of groove and sidewall forms circular arc transition structure 261, and remove the 3rd mask material 250, expose the first surface 211 of patterned second mask material 240 and silicon carbide substrates.Described circular arc transition structure 261 decreases electric field and gathers, and electric fields uniform is distributed, and is conducive to the withstand voltage improving power device.The degree of depth of described first groove 260 is not from 0.5 micron to 50 microns etc.Described lithographic method comprises reactive ion etching (reactive ion etching, RIE), inductively coupled plasma (inductive coupled plasma, ICP) etching, laser ablation or ion beam millings etc., the material of use comprises argon Ar, oxygen O
2, nitrogen N
2, helium He, chlorine Cl
2, sulphur hexafluoride SF
6, carbon tetrafluoride CF
4, fluoroform CHF
3, Nitrogen trifluoride NF
3deng, but be not limited to above-mentioned different materials.
The method of described removal the 3rd mask material 250 comprises the steps such as corrosion or etching, optionally can remove the 3rd mask material 250, and not remove the second mask material 240.Described lithographic method comprises reactive ion etching (reactive ion etching, RIE), inductively coupled plasma (inductive coupled plasma, ICP) etching, laser ablation or ion beam millings etc., the material of use comprises argon Ar, oxygen O
2, nitrogen N
2, helium He, chlorine Cl
2, sulphur hexafluoride SF
6, carbon tetrafluoride CF
4, fluoroform CHF
3, Nitrogen trifluoride NF
3deng, but be not limited to above-mentioned different materials.The material that described wet etching method uses comprises phosphoric acid H
3pO
4, hydrofluoric acid HF, buffered hydrofluoric acid BOE, sulfuric acid H
2sO
4, nitric acid HNO
3, hydrochloric acid HCl, acetic acid CH
3cOOH, oxydol H
2o
2deng, the corrosive liquid of variable concentrations proportioning is selected according to different materials.
6) then, as shown in figure 14, etching silicon carbide Semiconductor substrate 210 forms the second groove 262, the corner 263 of described second bottom portion of groove and sidewall and the corner 264 of the second bottom portion of groove and the first recess sidewall form circular arc transition structure, and remove the second mask material 240, expose the first surface 211 of patterned first mask material 230 and silicon carbide substrates.Described circular arc transition structure 263 and 264 decreases electric field and gathers, and electric fields uniform is distributed, and is conducive to the withstand voltage improving power device.The degree of depth of described second groove 262 is not from 0.5 micron to 50 microns etc.Described lithographic method comprises reactive ion etching (reactive ion etching, RIE), inductively coupled plasma (inductive coupled plasma, ICP) etching, laser ablation or ion beam millings etc., the material of use comprises argon Ar, oxygen O
2, nitrogen N
2, helium He, chlorine Cl
2, sulphur hexafluoride SF
6, carbon tetrafluoride CF
4, fluoroform CHF
3, Nitrogen trifluoride NF
3deng, but be not limited to above-mentioned different materials.
The method of described removal second mask material 240 comprises the steps such as corrosion or etching, optionally can remove the second mask material 240, and not remove the first mask material 230.Described lithographic method comprises reactive ion etching (reactive ion etching, RIE), inductively coupled plasma (inductive coupled plasma, ICP) etching, laser ablation or ion beam millings etc., the material of use comprises argon Ar, oxygen O
2, nitrogen N
2, helium He, chlorine Cl
2, sulphur hexafluoride SF
6, carbon tetrafluoride CF
4, fluoroform CHF
3, Nitrogen trifluoride NF
3deng, but be not limited to above-mentioned different materials.The material that described wet etching method uses comprises phosphoric acid H
3pO
4, hydrofluoric acid HF, buffered hydrofluoric acid BOE, sulfuric acid H
2sO
4, nitric acid HNO
3, hydrochloric acid HCl, acetic acid CH
3cOOH, oxydol H
2o
2deng, the corrosive liquid of variable concentrations proportioning is selected according to different materials.
8) then, as shown in figure 15, etching silicon carbide Semiconductor substrate 210 forms the 3rd groove 265, the corner 266 of described 3rd bottom portion of groove and sidewall and the corner 267 of the 3rd bottom portion of groove and the second recess sidewall form circular arc transition structure, 3rd recess sidewall near normal, be approximated to right angle 268 with silicon carbide substrates first surface, and remove the first mask material 230, expose the first surface 211 of silicon carbide substrates.The degree of depth of described 3rd groove 265 is greater than the degree of depth of doped region 220.Described circular arc transition structure 266 and 267 decreases electric field and gathers, and electric fields uniform is distributed, and is conducive to the withstand voltage improving power device.Described 3rd recess sidewall near normal, is approximated to right angle 268 with silicon carbide substrates first surface, avoids the formation of negative angle bevel termination, makes Electric Field Distribution even, is also conducive to the withstand voltage improving power device.The degree of depth of described 3rd groove 265 is not from 0.5 micron to 50 microns etc.Described lithographic method comprises reactive ion etching (reactive ion etching, RIE), inductively coupled plasma (inductive coupled plasma, ICP) etching, laser ablation or ion beam millings etc., the material of use comprises argon Ar, oxygen O
2, nitrogen N
2, helium He, chlorine Cl
2, sulphur hexafluoride SF
6, carbon tetrafluoride CF
4, fluoroform CHF
3, Nitrogen trifluoride NF
3deng, but be not limited to above-mentioned different materials.
The method of described removal first mask material 230 comprises the steps such as corrosion or etching, optionally can remove the first mask material 230, and not damage silicon carbide substrates 210.Described lithographic method comprises reactive ion etching (reactive ion etching, RIE), inductively coupled plasma (inductive coupled plasma, ICP) etching, laser ablation or ion beam millings etc., the material of use comprises argon Ar, oxygen O
2, nitrogen N
2, helium He, chlorine Cl
2, sulphur hexafluoride SF
6, carbon tetrafluoride CF
4, fluoroform CHF
3, Nitrogen trifluoride NF
3deng, but be not limited to above-mentioned different materials.The material that described wet etching method uses comprises phosphoric acid H
3pO
4, hydrofluoric acid HF, buffered hydrofluoric acid BOE, sulfuric acid H
2sO
4, nitric acid HNO
3, hydrochloric acid HCl, acetic acid CH
3cOOH, oxydol H
2o
2deng, the corrosive liquid of variable concentrations proportioning is selected according to different materials.
9) then, other processing steps of silicon carbide power device making can be carried out, comprising the combination of any order of a step in the steps such as insulating barrier making, passivation layer making, metal electrode making, scribing or some steps, also can be the manufacture craft of other silicon carbide power devices.Do not repeat them here.
According to specific exemplary embodiment, invention has been described herein.It will be apparent under not departing from the scope of the present invention, carrying out suitable replacement to one skilled in the art or revise.Exemplary embodiment is only illustrative, instead of the restriction to scope of the present invention, and scope of the present invention is defined by appended claim.
Claims (9)
1. a manufacture method for silicon carbide device terminal structure, comprises the following steps successively:
S101. cleaning sic substrate, described silicon carbide substrates comprises the first and second surfaces;
S102. deposit the first mask material, described first mask material covers the first surface of described silicon carbide substrates;
S103. the first mask material is graphical, exposes the first surface of partially carbonized silicon substrate;
S104. the second mask material is deposited, the first mask material of described second mask material cover graphics and the silicon carbide substrates first surface exposed;
S105. the second mask material is graphical, exposes the first surface of partially carbonized silicon substrate, the first mask material of the part or all of cover graphics of described patterned second mask material;
S106. etching silicon carbide substrate forms the first groove, and the corner of described first bottom portion of groove and sidewall forms circular arc transition structure;
S107. remove the second mask material, expose the first surface of patterned first mask material and silicon carbide substrates;
S108. etching silicon carbide substrate forms the second groove;
S109. the first mask material is removed.
2. the method for claim 1, it is characterized in that, formed in the second groove at described step S108 etching silicon carbide substrate, the corner of described second bottom portion of groove and sidewall and the corner of the second bottom portion of groove and the first recess sidewall form circular arc transition structure.
3. the method for claim 1, is characterized in that, formed in the second groove at described step S108 etching silicon carbide substrate, the angle between the second recess sidewall and silicon carbide substrates first surface is 80 ~ 95 °.
4. the method for claim 1, is characterized in that, removes in the second mask material at described step S107, removes the second mask material, and does not damage the first mask material and silicon carbide substrates.
5. the method for claim 1, it is characterized in that, also step is comprised: deposition the 3rd mask material is also graphical, the second mask material of the part or all of cover graphics of described patterned 3rd mask material and the first mask material after described step S105 second mask material is graphical.
6. method as claimed in claim 5, is characterized in that, before described step S106 etching silicon carbide substrate forms the first groove, also comprise step: etching silicon carbide substrate forms the 3rd groove, remove the 3rd mask material.
7. the method for claim 1, is characterized in that, before each etching silicon carbide substrate step, also comprises wet etching or dry etching mask material, forms the transition pattern of protruding arc-shaped at mask material edge.
8. the method according to any one of claim 1-7, it is characterized in that, described silicon carbide substrates is nude film, or comprise different doped regions, described doped region is N-shaped or p-type doping, and different regions has different doping contents, or comprises epitaxial loayer at the first surface of substrate and/or second surface, described epitaxial loayer is N-shaped or p-type, and different epitaxial layer region has different doping contents.
9. the method according to any one of claim 1-7, it is characterized in that, the first surface of described silicon carbide substrates and/or second surface comprise insulating barrier and/or metal level, described insulating barrier is silica, silicon nitride, polyimides or its composite construction, described metal level and manufacturing silicon carbide semiconductor surface form Schottky contacts and/or ohmic contact, and described metal level is tungsten, chromium, platinum, titanium, silver, gold, aluminium, nickel, copper or its alloy and composite construction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410857086.XA CN104637793A (en) | 2014-12-31 | 2014-12-31 | Manufacturing method of terminal structure of silicon carbide device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410857086.XA CN104637793A (en) | 2014-12-31 | 2014-12-31 | Manufacturing method of terminal structure of silicon carbide device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104637793A true CN104637793A (en) | 2015-05-20 |
Family
ID=53216394
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410857086.XA Pending CN104637793A (en) | 2014-12-31 | 2014-12-31 | Manufacturing method of terminal structure of silicon carbide device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104637793A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107516633A (en) * | 2017-04-17 | 2017-12-26 | 中国电子科技集团公司第五十五研究所 | A kind of gallium nitride lithographic method |
| CN109473354A (en) * | 2018-10-10 | 2019-03-15 | 华中科技大学 | A kind of preparation method and product of the drift step recovery diode based on silicon carbide |
| CN114639598A (en) * | 2022-05-10 | 2022-06-17 | 晶芯成(北京)科技有限公司 | Method for manufacturing semiconductor structure |
| CN116344437A (en) * | 2023-04-13 | 2023-06-27 | 中芯先锋集成电路制造(绍兴)有限公司 | Substrate processing method and semiconductor device manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5977605A (en) * | 1995-08-30 | 1999-11-02 | Asea Brown Boveri Ab | SiC Semiconductor device comprising a pn Junction with a voltage absorbing edge |
| JP2011029459A (en) * | 2009-07-27 | 2011-02-10 | Ulvac Japan Ltd | Method of manufacturing device |
| CN103474478A (en) * | 2013-09-17 | 2013-12-25 | 西安电子科技大学 | Silicon carbide SBD device |
-
2014
- 2014-12-31 CN CN201410857086.XA patent/CN104637793A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5977605A (en) * | 1995-08-30 | 1999-11-02 | Asea Brown Boveri Ab | SiC Semiconductor device comprising a pn Junction with a voltage absorbing edge |
| JP2011029459A (en) * | 2009-07-27 | 2011-02-10 | Ulvac Japan Ltd | Method of manufacturing device |
| CN103474478A (en) * | 2013-09-17 | 2013-12-25 | 西安电子科技大学 | Silicon carbide SBD device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107516633A (en) * | 2017-04-17 | 2017-12-26 | 中国电子科技集团公司第五十五研究所 | A kind of gallium nitride lithographic method |
| CN107516633B (en) * | 2017-04-17 | 2020-08-28 | 中国电子科技集团公司第五十五研究所 | Gallium nitride etching method |
| CN109473354A (en) * | 2018-10-10 | 2019-03-15 | 华中科技大学 | A kind of preparation method and product of the drift step recovery diode based on silicon carbide |
| CN114639598A (en) * | 2022-05-10 | 2022-06-17 | 晶芯成(北京)科技有限公司 | Method for manufacturing semiconductor structure |
| CN116344437A (en) * | 2023-04-13 | 2023-06-27 | 中芯先锋集成电路制造(绍兴)有限公司 | Substrate processing method and semiconductor device manufacturing method |
| CN116344437B (en) * | 2023-04-13 | 2023-10-20 | 中芯先锋集成电路制造(绍兴)有限公司 | Substrate processing method and semiconductor device manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI431797B (en) | Solar cell with selective emitter and fabrications thereof | |
| CN103493208B (en) | Semiconductor device and method for producing same | |
| CN106887470B (en) | Ga2O3Schottky diode device structure and preparation method thereof | |
| US9337380B2 (en) | Method for fabricating heterojunction interdigitated back contact photovoltaic cells | |
| TWI455342B (en) | Solar cell with selective emitter structure and manufacturing method thereof | |
| CN104637793A (en) | Manufacturing method of terminal structure of silicon carbide device | |
| CN103560078B (en) | The method of the steep property of a kind of accurate control carborundum high temperature tension mask | |
| CN104616978A (en) | Silicon-carbide power device terminal structure manufacturing method | |
| CN103515451A (en) | Double-concave groove type Schottky barrier element | |
| CN105047542A (en) | Method for manufacturing grooved silicon carbide MOSFET power device | |
| CN103985780B (en) | The manufacture method of solaode | |
| US20120094421A1 (en) | Method of manufacturing solar cell | |
| JPWO2016158226A1 (en) | Solar cell and manufacturing method thereof | |
| CN106876256A (en) | SiC double flute UMOSFET devices and preparation method thereof | |
| CN106057914A (en) | Double step field plate terminal based 4H-SiC Schottky diode and manufacturing method thereof | |
| CN111446331A (en) | Method for removing plating and method for preparing passivated contact solar cell | |
| CN109411342A (en) | A kind of silicon carbide groove etching method | |
| CN107230625A (en) | Gallium nitride transistor and its manufacture method | |
| JP6768432B2 (en) | Manufacturing method of silicon substrate | |
| CN106486365B (en) | The forming method of semiconductor devices | |
| CN108206220A (en) | The preparation method of diamond Schottky diode | |
| CN102916043B (en) | MOS-HEMT (Metal-oxide-semiconductor High-electron-mobility Transistor) device and manufacturing method thereof | |
| CN109509705A (en) | Low barrier height Schottky diode and preparation method thereof | |
| CN111180544B (en) | Passivated contact crystalline silicon solar cell and manufacturing method thereof | |
| CN105990134B (en) | A method of making diode |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20160325 Address after: 102211 Beijing city Changping District Xiaotangshan town big East Village Road No. 270 (future technology city) Applicant after: State Grid Smart Grid Institute Applicant after: State Grid Corporation of China Applicant after: State Grid Zhejiang Electric Power Company Address before: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Applicant before: State Grid Corporation of China Applicant before: State Grid Smart Grid Institute |
|
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150520 |
|
| RJ01 | Rejection of invention patent application after publication |