CN113921615A - Semiconductor device with internal isolation structure and manufacturing method thereof - Google Patents
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
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Abstract
The application discloses a semiconductor device with an inner isolation structure and a manufacturing method thereof, wherein the semiconductor device comprises: a semiconductor substrate; the epitaxial layer is arranged on one side surface of the semiconductor substrate and provided with a first surface and a second surface which are opposite; the first surface comprises a cellular region, a transition region and a terminal region which are sequentially arranged in a first direction; the first direction is parallel to the semiconductor substrate; an oxide layer disposed on the first surface, the oxide layer being located in the transition region; the oxide layer comprises a first gate oxide layer and a field oxide layer which are sequentially arranged in the first direction; a main region disposed within the first surface, the main region including a first main region and a second main region with an isolation structure therebetween. The distributed voltage drop near the first gate oxide during switching can be reduced, thereby improving the endurance of the device to high switching speeds or high dV/dt.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device with an inner isolation structure and a manufacturing method thereof.
Background
For a long time, Si materials have been the dominant semiconductor material and are used in high temperature, high frequency circuits. However, with the progress of technology and the expansion of application fields, Si-based devices are increasingly difficult to meet the requirements of more severe environments and higher performance, and people are looking to the wide bandgap semiconductors. The SiC material is considered as a potential third-generation semiconductor material, and has higher breakdown field strength, higher carrier saturation velocity and higher thermal conductivity than the Si material, so that the SiC power electronic device has the characteristics of high related outage voltage, small on-resistance, high switching frequency, high efficiency and good high-temperature performance compared with the similar device of Si. The SiC material still has very excellent performance under the harsh conditions, such as high temperature, high frequency, especially under the conditions of high power and high radiation, so that the SiC material has wider application prospect in the application fields of aerospace, communication, electric power, military and the like than other semiconductor materials in the future.
With the continuous development of SiC material technology, SiC power devices develop rapidly. The SiC MOSFET device has the advantages of high switching speed, small on-resistance and the like, can realize higher breakdown voltage level under smaller drift region thickness (relative to Si material), can greatly reduce the size of a power switch module, reduces energy consumption, and has obvious advantages in the application fields of power switches, converters and the like.
At present, due to its structural characteristics, SiC MOSFET devices are widely used at high switching speeds for the purpose of reducing the size of power supply systems, and the like. The internal physical processes realized by high switching speed can be partially understood as the charging and discharging processes of each distributed capacitor in the device, especially the charging and discharging processes forming each space charge area. In the prior art, in the charging and discharging processes of a PN junction space charge region formed by a surface P-type well region and an epitaxial layer, a large distributed resistance and charging and discharging current can cause various transient responses, one of which is transient oxide layer breakdown, which is an important factor for limiting the switching speed of a SiC MOSFET.
Disclosure of Invention
In view of the above, the present invention provides a semiconductor device having an inner isolation structure and a method for fabricating the same, in which the isolation structure is disposed between a first main junction and a second main junction, so that a distributed voltage drop near a first gate oxide layer during a switching process can be reduced, thereby improving a tolerance of the device to a high switching speed or a high dV/dt.
In order to achieve the purpose, the invention provides the following technical scheme:
a semiconductor device having an inner isolation structure, comprising:
a semiconductor substrate;
an epitaxial layer disposed on a side surface of the semiconductor substrate, the epitaxial layer having a first surface facing away from the semiconductor substrate and a second surface facing toward the semiconductor substrate; the first surface comprises a cellular region, a transition region and a terminal region which are sequentially arranged in a first direction; the first direction is parallel to the semiconductor substrate;
an oxide layer disposed on the first surface, the oxide layer being located in the transition region; the oxide layer comprises a first gate oxide layer and a field oxide layer which are sequentially arranged in the first direction;
a main region disposed within the first surface, the main region including a first main region and a second main region with an isolation structure therebetween.
Preferably, in the above semiconductor device, the thickness of the first gate oxide layer is smaller than the thickness of the field oxide layer;
in the direction vertical to the semiconductor substrate, the isolation structure is overlapped with the field oxide layer and is not overlapped with the first gate oxide layer.
Preferably, the semiconductor device further includes: a first source electrode and a second source electrode disposed on the first surface;
the first source electrode is positioned in the transition region, positioned on one side of the first gate oxide layer, which is far away from the terminal region, and contacted with the first main junction region;
the second source electrode is located the transition region, and is located the field oxide deviates from one side of cell region, with the contact of second main junction.
Preferably, in the semiconductor device described above, a size of the first source electrode is smaller than a size of the second source electrode.
Preferably, in the above semiconductor device, the isolation structure includes: a portion of the epitaxial layer located between the first main junction and the second main junction;
and/or, at least one spacer ring.
Preferably, in the above semiconductor device, the potential of the isolation ring is floating.
Preferably, in the semiconductor device described above, a doping type of the isolation ring is the same as a doping type of the first main junction and a doping type of the second main junction, and is different from a doping type of the epitaxial layer.
Preferably, in the above semiconductor device, the cell region includes:
a source region disposed within the first surface;
the first polycrystalline grid is arranged on one side, away from the semiconductor substrate, of the epitaxial layer;
a third source electrode disposed on the first surface.
Preferably, the semiconductor device further includes:
the second polycrystalline grid is arranged on one side of the first surface and is positioned in the transition region;
the grid electrode is arranged on the surface, away from the epitaxial layer, of the second polycrystalline grid electrode;
and a drain electrode disposed on the other side surface of the semiconductor substrate.
The present invention also provides a method for manufacturing a semiconductor device having an isolation structure, so the method includes:
providing a semiconductor substrate;
forming an epitaxial layer on one side surface of the semiconductor substrate, wherein the epitaxial layer is provided with a first surface facing away from the semiconductor substrate and a second surface facing towards the semiconductor substrate; the first surface comprises a cellular region, a transition region and a terminal region which are sequentially arranged in a first direction; the first direction is parallel to the semiconductor substrate;
forming an oxide layer on the first surface, wherein the oxide layer is positioned in the transition region; the oxide layer comprises a first gate oxide layer and a field oxide layer which are sequentially arranged in the first direction;
forming a main region in the first surface, the main region including a first main region and a second main region with an isolation structure therebetween.
As can be seen from the above description, in the semiconductor device with the inner isolation structure and the manufacturing method thereof provided in the technical solution of the present invention, by providing the isolation structure between the first main junction and the second main junction, the endurance capability of the device to a high switching speed or a high dV/dt can be improved; and the first main junction and the second main junction are respectively arranged to be contacted with the source, when the device is switched on or switched off, distributed current flows out from the source at two sides respectively, and as the size of the first source is smaller than that of the second source, main current flows out from the source deviated to the field oxide region, so that the current flowing out from the first gate oxide is greatly reduced, and the distributed voltage drop of the first gate oxide is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural view of a conventional semiconductor device;
FIG. 2 is a top view of a P + main junction in a conventional semiconductor device;
FIG. 3 is a schematic diagram of the current change in the transition region during the turn-on process of a conventional semiconductor device;
FIG. 4 is a schematic diagram of the current change in the transition region during turn-off of a conventional semiconductor device;
fig. 5 is a schematic structural diagram of a semiconductor device having inner isolation structures according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another semiconductor device having inner isolation structures according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another semiconductor device having inner isolation structures according to an embodiment of the present invention;
figure 8 is a top view of a P + main junction region in a semiconductor device according to an embodiment of the present invention;
figure 9 is a top view of a P + main junction in another semiconductor device according to an embodiment of the present invention;
figure 10 is a top view of a P + main junction region in yet another semiconductor device according to an embodiment of the present invention;
fig. 11 is a schematic diagram illustrating a current change in a transition region of a semiconductor device during a turn-on process according to an embodiment of the present invention;
fig. 12 is a schematic view illustrating a current change in a transition region of a semiconductor device during a turn-off process according to an embodiment of the present invention;
fig. 13-18 are process flow diagrams of a method for manufacturing a semiconductor device with an inner isolation structure according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The SiC power MOSFET is a unipolar voltage control device, is mainly applied to a power supply and a power processing system, and plays a role in controlling electric energy conversion. Compared with the conventional Si-based power device, the SiC device more easily realizes high voltage, low loss, and high power density, and thus is gradually becoming the mainstream of the market.
Due to its own structural characteristics, SiC MOSFET devices are widely used at high switching speeds for the purpose of reducing the size of power supply systems, and the like. The internal physical processes realized by high switching speed can be partially understood as the charging and discharging processes of each distributed capacitor in the device, especially the charging and discharging processes forming each space charge area. In the SiC material, the difficulty of forming P-type doping is much higher than that of the conventional semiconductor material, so that the ohmic contact and the doping resistance of the P-type doping region of the SiC device are much higher than those of the conventional Si device. Therefore, most intuitively, in the charging and discharging process of a PN junction space charge region formed by the surface P-type well region and the epitaxial layer, a large distributed resistance and charging and discharging current can cause multiple transient responses, one of which is transient oxide layer breakdown, which is an important factor for limiting the switching speed of the SiC MOSFET. In all P-type doping, the physical dimensions of the transition region between the cell region and the terminal region and the main surface regions are much higher than those of the cell region structure in the chip, so that the cell region structure has higher distributed current and larger series distributed resistance, and the region is also the junction region of the thin gate oxide layer and the thick field oxide layer, so that the cell region structure is the sensitive position where the failures are most likely to occur. As shown in fig. 1, a typical transition region structure is given, and its physical process of failure occurs under conditions of high switching speed.
As shown in fig. 1 and 2, fig. 1 is a schematic structural diagram of a conventional semiconductor device, and fig. 2 is a top view of a P + main junction region in the conventional semiconductor device. The semiconductor device includes: the epitaxial layer 02 is provided with a cell region A on the surface of one side of the epitaxial layer 02 departing from the semiconductor substrate 01, a first transition region B, a second transition region C and a terminal region D, a P + main junction 03 arranged in the epitaxial layer 02, a first gate oxide 04 arranged on the surface of one side of the epitaxial layer 02 departing from the semiconductor substrate 01, a field oxide 05 and a metal source 07, a first polycrystalline gate 06 and a metal gate 08 arranged on one side of the epitaxial layer 02 departing from the semiconductor substrate 01, a drain 09 arranged on the surface of one side of the semiconductor substrate 01 departing from the epitaxial layer 02, a well region 11 arranged in the cell region A, a source region 12, a P-type ohmic contact layer 13, a second gate oxide 14, a second polycrystalline gate 15 and an isolation dielectric layer 16, and a plurality of field limiting ring structures 10 arranged in the terminal region D. Wherein, the dotted line frame in fig. 2 represents the boundary of the first gate oxide layer 04 and the field oxide layer 05.
Fig. 1 shows a typical structure of a cell region a, a terminal region D and a transition region in a SiC MOSFET (taking an N-type planar gate SiC MOSFET as an example, or a gate control device or other types of MOSFETs similar thereto), where the cell region a is a main region for carrying current and implementing a gate control function, and is generally composed of a large number of repeating units, and the size of a single cell is from several micrometers to several tens of micrometers. The termination region D is designed to prevent breakdown voltage reduction due to edge effect when the device is in a blocking state, and fig. 1 only shows a basic field limiting ring structure, which is not a key point of the present invention. Between the cell region a and the terminal region D, a transition region is usually required to be designed to achieve the functions of gate interconnection and the like. As shown in fig. 1, a structure is shown in which the gate potential crosses the height difference with the field oxide layer 05 from the first poly gate 06 on the surface of the first gate oxide layer 04 to realize connection with the metal gate 08. This connection can be present in either the Gate BUS region where Gate interconnection is achieved or the Gate PAD region where the Gate is wire bonded, and can range from tens to hundreds of microns in size. The SiC material surface directly under this region usually needs to be covered with large P + doping to meet the breakdown voltage requirement of this region. As shown in fig. 3 and 4, the physical processes of the transition region in the device turn-on and turn-off process are shown. Fig. 3 is a schematic view showing a current change in a transition region during an on process of a conventional semiconductor device, and fig. 4 is a schematic view showing a current change in a transition region during an off process of a conventional semiconductor device.
The on and off processes of the device are all states corresponding to the cell area A, and potential changes among the grid G, the drain D and the source S are reflected in the transition area. Taking the device turn-on process as an example, before turn-on, the drain 09 (bottom surface under the device) is at a high potential, the metal source 07 is at a 0 potential, and the metal gate 08 is usually at a 0 or negative potential. At this time, the transition region PN junction is in a charged state, and the space charge region depletion region is the largest.
During the turn-on process, a positive voltage is applied to the grid G, and meanwhile, the voltage of the drain D is continuously reduced, so that the space charge area is reduced. The space charge region is discharged at this time, creating a transient distributed current that flows from the metal source 07 to the drain 09. Specifically, a hole current flowing from the metal source 07 to the PN junction space charge region of several hundred micrometers is formed in the illustrated large-area P + main junction region 03. The faster the turn-on speed, or the greater the dV/dt of drain 09, the greater the current. There are distributed well resistance and ohmic contact resistance inside the P + main junction 03 and at the position where the metal source 07 contacts the P + main junction 03, respectively. Therefore, under the action of distributed current, a lateral voltage drop with a negative value relative to the metal source electrode 07 is formed in the P + main junction 03, and the farther the relative position is away from the ohmic contact metal, the larger the sum of two kinds of distributed resistance is, or the faster the switching speed is (the larger dV/dt) is, a higher voltage drop is formed locally. The positive voltage of the grid G and the distributed negative voltage form a superposition effect to generate a voltage difference of the oxide layer far higher than the cell area A. At this time, if a transient voltage exceeding the critical breakdown field of the thin gate oxide is formed in the first transition region B, the oxide layer of the device will fail. For the second transition region C, the voltage required to exceed the critical field strength is higher due to the thicker field oxide layer, and therefore the tolerance to this failure mode is higher.
The turn-off process of the device is opposite to the turn-on process, the current direction is from the drain D to the source S, the direction of the generated transient voltage drop is also opposite, and a similar failure mode can be generated in the same way. Meanwhile, although the grid potential is 0 or negative electricity with lower potential is only needed when the device is turned off, the negative critical breakdown field strength of the grid is lower for the device made of the SiC material, so that the device has no stronger endurance capacity and is still in a competitive relationship with a failure mode in the turning-on process.
Accordingly, in order to solve the above problems, the present invention provides a semiconductor device having an isolation structure and a method for fabricating the same, which can improve the endurance of the device to a high switching speed or a high dV/dt by providing an isolation structure between a first main junction and a second main junction; and the first main junction and the second main junction are respectively arranged to be contacted with the source, when the device is switched on or switched off, distributed current flows out from the source at two sides respectively, and as the size of the first source is smaller than that of the second source, main current flows out from the source deviated to the field oxide region, so that the current flowing out from the first gate oxide is greatly reduced, and the distributed voltage drop of the first gate oxide is reduced.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.
Referring to fig. 5 to 7, fig. 5 is a schematic structural diagram of a semiconductor device having an inner isolation structure according to an embodiment of the present invention, fig. 6 is a schematic structural diagram of another semiconductor device having an inner isolation structure according to an embodiment of the present invention, and fig. 7 is a schematic structural diagram of another semiconductor device having an inner isolation structure according to an embodiment of the present invention.
As shown in fig. 5 to 7, the semiconductor device includes:
a semiconductor substrate 21; the semiconductor substrate 21 is doped with N + and may be a SiC substrate;
an epitaxial layer 22 disposed on a surface of one side of the semiconductor substrate 21, the epitaxial layer 22 being N-doped and may be a SiC layer, the epitaxial layer 22 having a first surface facing away from the semiconductor substrate 21 and a second surface facing toward the semiconductor substrate 21; the first surface comprises a cell region 100, a transition 200 and a terminal region 300 arranged in sequence in a first direction; the first direction is parallel to the semiconductor substrate 21;
an oxide layer disposed on the first surface, the oxide layer being located in the transition region 200; the oxide layer comprises a first gate oxide layer 26 and a field oxide layer 27 which are sequentially arranged in the first direction;
a main region disposed within the first surface, the main region may be P + doped, the main region comprising a first main region 23 and a second main region 24, the first main region 23 and the second main region 24 having an isolation structure 25 therebetween.
In the embodiment of the present invention, the thickness of the first gate oxide layer 26 is smaller than the thickness of the field oxide layer 27; in the direction perpendicular to the semiconductor substrate 21, the isolation structure 25 overlaps the field oxide layer 27, and does not overlap the first gate oxide layer 26.
As shown in fig. 5, the semiconductor device further includes: a first source electrode 31 and a second source electrode 29 disposed on the first surface; the first source 31 is located in the transition region 200, and is located on the side of the first gate oxide layer 26 away from the termination region 300, and is in contact with the first main junction region 23; the second source 29 is located in the transition region 200, and is located on the side of the field oxide layer 27 departing from the cell region 100, and contacts with the second main junction 24.
Wherein the size of the first source 31 is smaller than the size of the second source 29.
The invention divides the complete main junction area in the traditional structure into two independent parts from the vicinity of the sensitive position, and the two parts are respectively provided with contacts with the source electrode. I.e. at the interface of the first gate oxide 26 and the field oxide 27, an isolation structure 25 is provided in the main region, which is offset to the field oxide 27 portion, dividing the main region into a first main region 23 and a second main region 24, and being provided in contact with a first source 31 and a second source 29, respectively. At this time, when the device is on or off, the distributed current will flow from the first source 31 and the second source 29 on both sides, respectively. Since the size of the first source 31 is smaller than that of the second source 29 and the thickness of the first gate oxide 26 of the transition region 200 is only a few or a dozen microns, while the thickness of the field oxide 27 is tens or even hundreds of microns, the main current will flow only from the second source 29 biased to the field oxide 27 region. In this way, the current flowing from the first gate oxide layer 26 will be greatly reduced, thereby reducing the distributed voltage drop of the first gate oxide layer 26, and at the same time, the endurance of the structure to high switching speeds or high dv/dt can be improved.
In this embodiment of the present invention, the isolation structure 25 includes: a portion of the epitaxial layer 22 located between the first main junction 23 and the second main junction 24; and/or at least one spacer ring 40.
As shown in fig. 5, the isolation structure 25 includes: a portion of the epitaxial layer 22 located between the first main region 23 and the second main region 24.
As shown in fig. 6, the isolation structure 25 includes: a portion of said epitaxial layer 22 located between said first main region 23 and said second main region 24, and an isolation ring 40.
As shown in fig. 7, the isolation structure 25 includes: a portion of said epitaxial layer 22 located between said first main region 23 and said second main region 24, and two isolation rings 40.
Wherein the potential of the isolating ring 40 is floating, i.e. not in direct contact with any electrode.
In this scheme, two aspects need to be considered for the design method of the partition (i.e., the epitaxial layer 22 between the first main junction 23 and the second main junction 24), the isolation ring 40, or the plurality of isolation rings 40: (1) firstly, the setting of the ring width and the ring spacing should firstly ensure the requirement of the breakdown voltage, so that the reduction of the breakdown voltage caused by the edge effect is avoided. (2) Secondly, in the process of switching on or switching off, the left side and the right side of the main region which is divided form transverse voltage drops respectively. Due to the difference of current density and distributed resistance, the two parts have obvious voltage drop at the nearest position, and the arrangement of the partition or the isolation ring 40 ensures that the breakdown voltage between the two parts is higher than the maximum voltage drop of the device at the highest switching speed, so that no current flows between the left part and the right part. The width of wall can be by 0.1~10um inequality, if can be 5um, the width of isolating ring 40 can reach tens um even, can set for based on the demand.
It should be noted that the design of the isolation structure 25 and the number of the isolation rings 40 can be set based on the requirement, and are not limited to the manner described in the present application.
In the embodiment of the present invention, the doping type of the isolation ring 40 is the same as the doping type of the first main junction 23 and the second main junction 24, and is different from the doping type of the epitaxial layer 22. The isolation ring 40, the first main junction 23, and the second main junction 24 are all doped P-type, and the epitaxial layer 22 is doped N-type.
In the embodiment of the present invention, the cell area 100 includes:
a P-well region 33, a source region 34 and a P-type ohmic contact layer 35 disposed in the first surface, wherein the P-well region 33 is located in the first surface, the source region 34 is located in a surface of the P-well region 33 facing away from the semiconductor substrate 21, the P-type ohmic contact layer 35 is located in a middle region between the source region 34 and the P-well region 33, one end of the P-type ohmic contact layer 35 extends to a side surface of the P-well region 33 facing the semiconductor substrate 21, and the other end extends to a side surface of the source region 34 facing away from the semiconductor substrate 21;
the second gate oxide layer 36, the first polycrystal gate 37, the isolation dielectric layer 38 and the third source electrode 39 are arranged on the first surface, the second gate oxide layer 36 is arranged on the first surface, the first polycrystal gate 37 is arranged on the surface, deviating from the epitaxial layer 22, of the second gate oxide layer 36, the isolation dielectric layer 38 is arranged on the surface, deviating from the second gate oxide layer 36, of the first polycrystal gate 37 and the side walls of the first polycrystal gate 37 and the second gate oxide layer 36, and the third source electrode 39 is arranged on the first surface and surrounds the isolation dielectric layer 38. The isolation dielectric layer 38 may be a silicon dioxide layer.
Wherein the first source 31 and the third source 39 are two portions on the same source.
In the embodiment of the present invention, the terminal area includes: a plurality of field limiting ring structures 41 located within the first surface, and a field oxide layer 27 located on the first surface.
Based on fig. 5 to 7, the semiconductor device further includes:
a second poly gate 28 disposed on a side surface of said first gate oxide 26 and said field oxide 27 facing away from said epitaxial layer 22, said second poly gate 28 being located in said transition region 200;
a gate 30 disposed on a surface of the second poly gate 26 facing away from the field oxide 27, the gate being located in the transition region 200;
and a drain 32 disposed on the other side surface of the semiconductor substrate 21.
Referring to fig. 8 to 10, fig. 8 is a top view of a P + main junction in a semiconductor device according to an embodiment of the present invention, fig. 9 is a top view of a P + main junction in another semiconductor device according to an embodiment of the present invention, and fig. 10 is a top view of a P + main junction in another semiconductor device according to an embodiment of the present invention.
Fig. 8-10 show the overall view of the chip, showing only the P + main junction and associated structures. In fig. 8, the second source electrode 29 is disposed on a side surface of the second main junction region 24 that is offset from the isolation structure 25, for example, in the manner shown in fig. 5-7; in fig. 9 and 10, the second source electrode 29 is disposed on one side surface of the second main junction region 24 near the isolation structure 25.
Compared with the mode shown in fig. 2, in the present scheme, by arranging the isolation structure 25 between the first main junction 23 and the second main junction 24, and arranging the contacts between the first main junction 23 and the second main junction 24 and the corresponding sources, respectively, when the device is turned on or turned off, the distributed current will flow out from the sources on both sides, respectively, and since the size of the first source 31 is smaller than that of the second source 29, the main current will flow out from the source biased to the field oxide 27 area, and the current flowing out from the first gate oxide 26 will be greatly reduced, thereby reducing the distributed voltage drop of the first gate oxide 26.
Referring to fig. 11 and 12, fig. 11 is a schematic view of a current change in a transition region of a semiconductor device during an on process according to an embodiment of the present invention, and fig. 12 is a schematic view of a current change in a transition region of a semiconductor device during an off process according to an embodiment of the present invention. During the turn-on process, the current direction is from the source to the drain. During turn-off, the current flow is from drain to source.
In the manner shown in fig. 11 and 12, the first main region 23 and the second main region 24 on both sides will form a physical partition due to the presence of the isolation structure 25, while having a certain mutual withstand voltage function. The separated first main junction region 23 and second main junction region 24 will only form charge and discharge current from the corresponding source, thereby greatly reducing the total amount of current flowing through the first gate oxide layer 26, achieving the effect of reducing additional voltage drop and improving the dV/dt endurance of the region.
Based on the foregoing embodiment, another embodiment of the present invention further provides a manufacturing method of a semiconductor device, as shown in fig. 5 and fig. 13 to 18, where fig. 13 to 18 are process flow diagrams of a manufacturing method of a semiconductor device with an inner isolation structure according to an embodiment of the present invention, and taking the semiconductor device shown in fig. 5 as an example, the manufacturing method includes:
step S11: as shown in fig. 13, a semiconductor substrate 21 is provided; the semiconductor substrate 21 is doped N-type and may be a SiC substrate;
step S12: as shown in fig. 14, an epitaxial layer 22 is formed on one side surface of the semiconductor substrate 21, the epitaxial layer 22 may be a SiC layer, the epitaxial layer 22 has a first surface facing away from the semiconductor substrate 21 and a second surface facing toward the semiconductor substrate 21; the first surface comprises a cellular region 100, a transition region 200 and a terminal region 300 which are sequentially arranged in a first direction; the first direction is parallel to the semiconductor substrate 21;
step S13: forming main regions in the first surface, the main regions including a first main region 23 and a second main region 24 with an isolation structure 25 between the first main region 23 and the second main region 24, as shown in fig. 15; the main junction may be doped with P +;
meanwhile, a P well region 33, a source region 34, a P type ohmic contact layer 35 and a field limiting ring structure 41 are formed in the first surface; the P-well region 33, the source region 34 and the P-type ohmic contact layer 35 are all located in the cell region 200, and the field limiting ring structure 41 is located in the terminal region 300.
Wherein the isolation structure 25 may be a portion of the epitaxial layer 22 between the first main region 23 and the second main region 24, and/or at least one isolation ring 40. May be set based on demand.
Step S14: as shown in fig. 16, an oxide layer is formed on the first surface, and the oxide layer includes a second gate oxide layer 36, a first gate oxide layer 26, and a field oxide layer 27, which are sequentially arranged in the first direction. The first gate oxide layer 26 is located in the transition region 200, the second gate oxide layer 36 is located in the cell region 100, and the first gate oxide layer 26 and the second gate oxide layer 36 are two parts of the same gate oxide layer.
Wherein the thickness of the first gate oxide layer 26 is smaller than that of the field oxide layer 27; in the direction perpendicular to the semiconductor substrate 21, the isolation structure 25 overlaps the field oxide layer 27, and does not overlap the first gate oxide layer 26.
Based on the above description, the manufacturing method further includes:
step S15: as shown in fig. 17, a first source electrode 31 and a second source electrode 29 are formed on the first surface; the first source 31 is located in the transition region 200, and is located on the side of the first gate oxide layer 26 away from the termination region 300, and is in contact with the first main junction region 23; the second source 29 is located in the transition region 200, and is located on the side of the field oxide layer 27 departing from the cell region 100, and contacts with the second main junction 24.
Meanwhile, a first polycrystalline grid 37, a second polycrystalline grid 28, an isolation medium layer 38 and a third source 39 are formed on one side of the first surface; the first poly gate 37, the isolation dielectric layer 38 and the third source 39 are all located in the cell region 100, and the second poly gate 28 is located in the transition region 200. The first source 31 and the third source 39 are two parts on the same source.
Step S16: as shown in fig. 18, a gate 30 is formed on a surface of the second poly gate 26 facing away from the field oxide layer 27, where the gate is located in a transition region 200;
step S17: as shown in fig. 5, a drain electrode 32 is formed on the other side surface of the semiconductor substrate 21.
As can be seen from the above description, in the method for manufacturing a semiconductor device with an isolation structure according to the present invention, by providing the isolation structure 25 between the first main junction region 23 and the second main junction region 24, the endurance of the device to high switching speed or high dV/dt can be improved; and the first main junction region 23 and the second main junction region 24 are respectively arranged to be contacted with the corresponding source, when the device is in the process of switching on or switching off, the distributed current respectively flows out from the first source 31 and the second source 29 at two sides, and as the size of the second source 29 is larger than that of the first source 31, the main current flows out from the source which is deviated to the field oxide 27 area, so that the current flowing out from the first gate oxide 26 is greatly reduced, and the distributed voltage drop of the first gate oxide 26 is reduced.
The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other. The manufacturing method disclosed by the embodiment corresponds to the semiconductor device disclosed by the embodiment, so that the description is relatively simple, and the relevant points can be referred to the partial description of the semiconductor device.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A semiconductor device having an inner isolation structure, comprising:
a semiconductor substrate;
an epitaxial layer disposed on a side surface of the semiconductor substrate, the epitaxial layer having a first surface facing away from the semiconductor substrate and a second surface facing toward the semiconductor substrate; the first surface comprises a cellular region, a transition region and a terminal region which are sequentially arranged in a first direction; the first direction is parallel to the semiconductor substrate;
an oxide layer disposed on the first surface, the oxide layer being located in the transition region; the oxide layer comprises a first gate oxide layer and a field oxide layer which are sequentially arranged in the first direction;
a main region disposed within the first surface, the main region including a first main region and a second main region with an isolation structure therebetween.
2. The semiconductor device of claim 1, wherein a thickness of the first gate oxide layer is less than a thickness of the field oxide layer;
in the direction vertical to the semiconductor substrate, the isolation structure is overlapped with the field oxide layer and is not overlapped with the first gate oxide layer.
3. The semiconductor device according to claim 1, further comprising: a first source electrode and a second source electrode disposed on the first surface;
the first source electrode is positioned in the transition region, positioned on one side of the first gate oxide layer, which is far away from the terminal region, and contacted with the first main junction region;
the second source electrode is located the transition region, and is located the field oxide deviates from one side of cell region, with the contact of second main junction.
4. The semiconductor device according to claim 3, wherein a size of the first source is smaller than a size of the second source.
5. The semiconductor device of claim 1, wherein the isolation structure comprises: a portion of the epitaxial layer located between the first main junction and the second main junction;
and/or, at least one spacer ring.
6. The semiconductor device according to claim 5, wherein a potential of the isolation ring is floating.
7. The semiconductor device of claim 6, wherein a doping type of the isolation ring is the same as a doping type of the first main junction and the second main junction and is different from a doping type of the epitaxial layer.
8. The semiconductor device according to claim 1, wherein the cell region comprises:
a source region disposed within the first surface;
the first polycrystalline grid is arranged on one side, away from the semiconductor substrate, of the epitaxial layer;
a third source electrode disposed on the first surface.
9. The semiconductor device according to claim 1, further comprising:
the second polycrystalline grid is arranged on one side of the first surface and is positioned in the transition region;
the grid electrode is arranged on the surface, away from the epitaxial layer, of the second polycrystalline grid electrode;
and a drain electrode disposed on the other side surface of the semiconductor substrate.
10. A method of fabricating a semiconductor device having an inner spacer structure, the method comprising:
providing a semiconductor substrate;
forming an epitaxial layer on one side surface of the semiconductor substrate, wherein the epitaxial layer is provided with a first surface facing away from the semiconductor substrate and a second surface facing towards the semiconductor substrate; the first surface comprises a cellular region, a transition region and a terminal region which are sequentially arranged in a first direction; the first direction is parallel to the semiconductor substrate;
forming an oxide layer on the first surface, wherein the oxide layer is positioned in the transition region; the oxide layer comprises a first gate oxide layer and a field oxide layer which are sequentially arranged in the first direction;
forming a main region in the first surface, the main region including a first main region and a second main region with an isolation structure therebetween.
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