JP2016162855A - Semiconductor device and power conversion device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with an excellent effect of reducing a switching loss, and to provide a power conversion device using the same.SOLUTION: A semiconductor device 100 comprises: a plurality of trenches 104 that penetrate through a p-type channel layer 103 from a surface of the p-type channel layer 103 and reach an n-type drift layer 101; first and second gate electrodes 107 and 108 each configured to include an insulating film 106 formed around a conductor 105 formed inside the trench 104; and a p-type floating region 112 adjacent to the first and second gate electrodes 107 and 108 in the n-type drift layer 101, and selectively formed at a lower part of the trench 104.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a power conversion device using the same.

In recent years, switching elements for power conversion, represented by IGBT (Insulated Gate Bipolar Transistor), have a wide range of applications, from small power devices such as home air conditioners and microwave ovens to high power devices used in railways and steelworks. It came to be. In order to promote the use of renewable energy and energy saving, power conversion from direct current to alternating current or from alternating current to direct current is indispensable. It is a key component for realizing.
By the way, when the IGBT is applied to a power conversion device such as a converter or an inverter, a conduction loss associated with the on-resistance occurs during conduction, and a switching loss associated with the switching operation occurs during switching. Therefore, in order to increase the efficiency and size of the inverter, it is necessary to reduce conduction loss and switching loss.

  Patent Document 1 describes an IGBT that can reduce a switching loss by dividing a trench gate into a pair of two gates and driving each gate with different control signals. The semiconductor device described in Patent Document 1 discharges a part of the accumulated carriers prior to turn-off of the entire element by supplying an off signal to one set of gates prior to the other set when conducting. . At the time of turning off the entire device, it is only necessary to turn off the remaining set of gates. Since there are few stored carriers, switching loss can be reduced.

WO2014 / 038064

  However, according to studies by the inventors of the present application, the IGBT having the structure disclosed in Patent Document 1 is not sufficient in reducing the switching loss, and a semiconductor device having a structure that can further reduce the switching loss is desired.

  This invention is made | formed in view of such a situation, and it aims at providing the semiconductor device which is excellent in the reduction effect of switching loss, and a power converter device using the same.

  In order to solve the above problems, a semiconductor device of the present invention is formed around a plurality of trenches that reach the drift layer from the surface of the channel layer to the drift layer, and a conductor formed inside the trench. First and second gate electrodes each including an insulating film formed, and selectively formed in the drift layer adjacent to the first and second gate electrodes and below the trench A floating region, and when a voltage at which a potential difference of 0 V with respect to the potential of the emitter electrode is applied to the first and second gate electrodes is applied between the channel layer and the floating region. The drift layer is interposed in a state of the first conductivity type, and a voltage is applied to the first gate electrode so that a potential difference with reference to the potential of the emitter electrode is a positive value. When a voltage is applied to the second gate electrode such that the potential difference with respect to the potential of the emitter electrode is a negative value, the channel layer and the floating region adjacent to the second gate electrode The gaps are connected to each other through the drift layer inverted to the second conductivity type.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device excellent in the reduction effect of switching loss and a power converter device using the same can be provided.

1 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a first embodiment of the present invention. FIG. 4 is a diagram showing a connection relationship between the first insulated gate set, the second insulated gate set, the first gate electrode and the second gate electrode extracted from the semiconductor device according to the first embodiment. is there. The conductors included in the first insulated gate set and the second insulated gate set of the semiconductor device according to the first embodiment are assembled, and the first gate electrode and the second gate electrode are structured. It is a perspective view which shows an example. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the said 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the said 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the said 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the said 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the said 1st Embodiment. It is a cross-sectional schematic diagram in the 1st conduction | electrical_connection state of the semiconductor device which concerns on the said 1st Embodiment. It is a cross-sectional schematic diagram in the 2nd conduction | electrical_connection state of the semiconductor device which concerns on the said 1st Embodiment. It is a figure which compares and shows the distribution of the charge density inside an n-type drift layer when the semiconductor device which concerns on the said 1st Embodiment is a 1st conduction | electrical_connection state or a 2nd conduction | electrical_connection state. It is a figure which compares and shows the voltage-current characteristic when the semiconductor device which concerns on the said 1st Embodiment is a 1st conduction | electrical_connection state or a 2nd conduction | electrical_connection state. It is a figure which shows the example of the circuit diagram symbol of the switching element for power conversion. It is a circuit diagram of the switching element for power conversion. FIG. 15 is a drive voltage and operation waveform diagram of the circuit shown in FIG. 14. It is a figure which shows typically the cross-section of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the power converter device which concerns on the said 2nd Embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to the first embodiment of the present invention.
The semiconductor device of this embodiment is an example when applied to a switching element for power conversion. In addition, although it demonstrates based on the diode using an n-type Si substrate, it is not limited to this. Similarly, when a p-type Si substrate is used, it can be handled. The same can be applied to the IGBT electrode structure in which current flows in the vertical direction.
As shown in FIG. 1, the semiconductor device 100 is formed on a first conductivity type (here, n-type) n-type drift layer 101 (first semiconductor layer) and a first surface 101 a of the n-type drift layer 101. A p-type collector layer 102 (second semiconductor layer) of the second conductivity type (here p-type) and a second conductivity type p-type channel layer 103 (first type) formed on the second surface 101b of the n-type drift layer 101. 3 semiconductor layers) and a plurality of trenches 104 that reach the n-type drift layer 101 through the p-type channel layer 103 from the surface of the p-type channel layer 103.

  In addition, the semiconductor device 100 includes at least two gate electrodes 107 and 108 including a conductor 105 formed inside the trench 104 and an insulating film 106 formed around the conductor 105, and a p-type channel. In the surface of the layer 103, in the first conductivity type n-type source region 111 (fourth semiconductor layer) formed adjacent to (in contact with) the gate electrodes 107 and 108, and in the n-type drift layer 101, the gate A p-type floating region 112 (fifth semiconductor layer) of the second conductivity type, which is adjacent to the electrodes 107 and 108 and selectively formed without being in contact with the p-type channel layer 103.

  In addition, the semiconductor device 100 includes an emitter electrode 114 formed on the surface of the p-type channel layer 103 and a collector electrode 113 formed on the surface of the p-type collector layer 102, and at least two gate electrodes 107 and 108. Is configured to include a first gate electrode 109 and a second gate electrode 110 in which applied voltages are controlled independently of each other.

  In the semiconductor device 100, when a voltage is applied to the first gate electrode 109 and the second gate electrode 110 so that the potential difference with respect to the potential of the emitter electrode 114 is 0 V, the p-type channel layer 103 and the p-type channel layer 103 An n-type drift layer 101 is interposed between the floating region 112 and the first conductivity type. Further, in the semiconductor device 100, a voltage is applied to the first gate electrode 109 so that the potential difference with reference to the potential of the emitter electrode 114 is a positive value, and the potential of the emitter electrode 114 is applied to the second gate electrode 110. When a voltage having a negative reference potential difference is applied, the p-type channel layer 103 and the p-type floating region 112 adjacent to the second gate electrode 110 (that is, the p-type channel layer) are applied. 103 and the p-type floating region 112) are connected to each other via the n-type drift layer 101 inverted to the second conductivity type.

As shown in FIG. 1, in a semiconductor device 100, a p-type collector layer 102 is formed on one surface (first surface 101a) of an n-type drift layer 101 formed of an n-type semiconductor, and the other surface (second surface). A p-type channel layer 103 is formed in 101b). A plurality of trenches 104 are formed from the surface of the p-type channel layer 103 to reach the n-type drift layer 101 through the p-type channel layer 103.
The trench 104 includes a first insulating gate set 107 including a conductor 105 formed inside the trench 104 and an insulating film 106 formed around the conductor 105 and a second insulating gate. A set 108 is formed. The conductors 105 included in the first insulated gate set 107 and the second insulated gate set 108 are gathered in regions not shown in FIG. 1, respectively, and the first gate electrode 109 and the second gate electrode 110 are assembled. Are connected to each.

FIG. 2 is a diagram illustrating a connection relationship between the first insulated gate set 107, the second insulated gate set 108, the first gate electrode 109, and the second gate electrode 110. FIG.
As shown in FIG. 2, a first insulated gate set 107 and a second insulated gate set 108 are connected to a first gate electrode 109 and a second gate electrode 110, respectively.
Various structures can be considered in which the conductors 105 included in the first insulated gate set 107 and the second insulated gate set 108 are assembled and connected to the first gate electrode 109 and the second gate electrode 110, respectively. obtain. For example, the structure shown in FIG. 3 is illustrated.

FIG. 3 shows an example of the structure of the first gate electrode 109 and the second gate electrode 110 by collecting the conductors 105 included in the first insulated gate set 107 and the second insulated gate set 108, respectively. It is a perspective view shown. In FIG. 3, a part of the structure is omitted or shown transparently.
As shown in FIGS. 2 and 3, the conductor 105 filling the trench 104 is connected to a plurality of contact regions 115 and 116 formed of a conductor on the insulating film 106. The plurality of contact regions 115 are gathered at the first gate electrode 109 via the contact 117 formed of a conductor and are connected to each other. Similarly, the plurality of contact regions 116 are gathered on the second gate electrode 110 via contacts 118 made of a conductor and are connected to each other.

  Returning to FIG. 1, an n-type source region 111 is formed in an island shape (that is, “selectively formed”) adjacent to the insulating film 106 on a part of the surface of the p-type channel layer 103. A p-type floating region 112 that is a part of the n-type drift layer 101 and is adjacent to the insulating film 106 and is not in contact with the p-type channel layer 103 is formed in an island shape. A collector electrode 113 is formed on the surface of the p-type collector layer 102 and an emitter electrode 114 is formed on the surface of the n-type channel layer 103, respectively.

[Method of Manufacturing Semiconductor Device 100]
Next, a method for manufacturing the semiconductor device 100 according to the first embodiment of the present invention will be described.
Various processes can be considered for manufacturing the power conversion switching element (semiconductor device 100) according to the present embodiment. For example, the steps shown in FIGS. 4 to 8 are illustrated.
4 to 8 are cross-sectional views showing the manufacturing process of the semiconductor device 100.
As shown in FIG. 4A, a silicon oxide film 119 that is an insulator is deposited on the surface of n-type silicon forming the n-type drift layer 101.
As shown in FIG. 4B, a plurality of openings 120 are formed in the oxide film 119 by etching.
As shown in FIG. 4C, a plurality of trenches 104 are formed by etching.

As shown in FIG. 5A, an oxide film 121 is formed by thermal oxidation. Here, the oxide film 121 is thinner than the oxide film 119.
As shown in FIG. 5B, the p-type floating region 112 is formed by ion implantation.
As shown in FIG. 5C, since the oxide film 121 is thinner than the oxide film 119, the island-like floating region 112 can be formed under the trench without using photoresist processing. The oxide films 119 and 121 are removed by etching.

As shown in FIG. 6A, an oxide film 106 is formed by thermal oxidation.
As shown in FIG. 6B, polycrystalline silicon 105 as a conductor is deposited.
As shown in FIG. 6C, a p-type channel layer 103 is formed by ion implantation.
As shown in FIG. 7A, an n-type source region 111 is formed by ion implantation.
As shown in FIG. 7B, an oxide film 122 is deposited.
As shown in FIG. 7C, a part of the oxide film 122 is removed by etching to form an emitter contact 123.

As shown in FIG. 8A, the emitter electrode 114 is formed by depositing aluminum as a conductor.
As shown in FIG. 8B, a p-type collector layer 102 is formed by ion implantation.
After the steps shown in FIGS. 4 to 8, aluminum is deposited to form the collector electrode 113, thereby obtaining the power conversion switching element (semiconductor device 100) shown in FIG.

Next, the operation of the power conversion switching element (semiconductor device 100) will be described.
[Description of Operation of Semiconductor Device 100]
The power conversion switching element (semiconductor device 100) is characterized in that two different conductive states are obtained by independently controlling voltages applied to the first gate electrode 109 and the second gate electrode 110.
A conduction state when a positive voltage is applied to the first gate electrode 109 and the second gate electrode 110 with reference to the potential of the emitter electrode 114 is referred to as a “first conduction state”, and the first gate electrode 109 When the positive voltage is applied to the second gate electrode 110 with reference to the potential of the emitter electrode 114 and the negative voltage is applied to the second gate electrode 110 with reference to the potential of the emitter electrode 114, the second conductive state is referred to as “second conductive state”. "

<First conduction state>
FIG. 9 is a schematic cross-sectional view of the power conversion switching element (semiconductor device 100) in the first conduction state. In FIG. 9, a positive voltage is applied to the collector electrode 113 by the voltage source 124 with reference to the potential of the emitter electrode 114. A positive voltage is applied to the first gate electrode 109 by the voltage source 125 with reference to the potential of the emitter electrode 114. Further, a positive voltage is applied to the second gate electrode 110 by the voltage source 126 with reference to the potential of the emitter electrode 114.

  At this time, since a positive voltage is applied to the first gate electrode 109 with reference to the potential of the emitter electrode 114, it opposes the conductor 105 through the insulating film 106 around the first insulating gate 107. Electrons (see “-” surrounded by circles) aggregate at the portion to be formed to form an electron channel 127. In addition, since a positive voltage is also applied to the second gate electrode 110 with reference to the potential of the emitter electrode 114, it faces the conductor 105 through the insulating film 106 around the second insulating gate 108. Electrons (see “-” surrounded by circles) aggregate at the portion to be formed, and the electron channel 127 is similarly formed.

Here, since a positive voltage is applied to the collector electrode 113 with reference to the potential of the emitter electrode 114, electrons pass through the path of the emitter electrode 114 -n-type source region 111 -electron channel 127 -n-type drift layer 101. (Refer to “-” surrounded by a circle) is implanted into the n-type drift layer 101. In response to the injection of electrons, holes (see “+” surrounded by circles) are injected into the n-type drift layer 101 through the path of the collector electrode 113 -p-type collector layer 102 -n-type drift layer 101. A part of the holes injected into the n-type drift layer 101 is discharged through the path of the n-type drift layer 101-p-type channel layer 103-emitter electrode 114.
In the n-type drift layer 101, electrons and holes accumulate at a concentration that balances injection and discharge. The n-type drift layer 101 undergoes conductivity modulation due to the accumulated electrons and holes, and the resistance thereof decreases, so that a current flows from the collector electrode 113 to the emitter electrode 114.

<Second conduction state>
FIG. 10 is a schematic cross-sectional view of the power conversion switching element (semiconductor device 100) in the second conduction state. In FIG. 10, a positive voltage is applied to the collector electrode 113 by the voltage source 124 with reference to the potential of the emitter electrode 114. A positive voltage is applied to the first gate electrode 109 by the voltage source 125 with reference to the potential of the emitter electrode 114. Further, a negative voltage with respect to the emitter electrode 114 is applied to the second gate electrode 110 by the voltage source 128.

  At this time, since a positive voltage is applied to the first gate electrode 109 with reference to the potential of the emitter electrode 114, it opposes the conductor 105 through the insulating film 106 around the first insulating gate 107. Electrons (see “-” surrounded by circles) aggregate at the portion to be formed to form an electron channel 127. On the other hand, since a negative voltage is applied to the second gate electrode 110 with reference to the potential of the emitter electrode 114, it opposes the conductor 105 through the insulating film 106 around the second insulating gate 108. Holes (see “+” surrounded by circles) are aggregated in the portion to form a hole channel 129.

Here, since a positive voltage is applied to the collector electrode 113 with reference to the potential of the emitter electrode 114, electrons pass through the path of the emitter electrode 114 -n-type source region 111 -electron channel 127 -n-type drift layer 101. Is injected into the n-type drift layer 101. However, since the number of electron channels 127 is small in the second conduction state as compared with the first conduction state (1/2 in the case of FIG. 10), injection of electrons (see “-” surrounded by circles) is performed. The amount is also reduced in the second conduction state compared to the first conduction state.
In response to the injection of electrons, holes are injected into the n-type drift layer 101 through the path of the collector electrode 113 -p-type collector layer 102 -n-type drift layer 101. However, since the injection amount of electrons is smaller in the second conduction state than in the first conduction state, the injection amount of holes (see “+” surrounded by a circle) is also smaller than that in the first conduction state. Less in the second conduction state.

  A part of the holes injected into the n-type drift layer 101 is discharged through the path of the n-type drift layer 101-p-type channel layer 103-emitter electrode 114. In addition, some of the holes injected into the n-type drift layer 101 are discharged through the path of the n-type drift layer 101 -p-type floating region 112 -hole channel 129 -p-type channel layer 103 -emitter electrode 114. The Therefore, the amount of discharged holes is larger in the second conductive state than in the first conductive state.

  In the n-type drift layer 101, electrons and holes accumulate at a concentration that balances injection and discharge. However, in the second conduction state, the injection amount of electrons and holes is small compared to the first conduction state, and the hole The amount of emissions is large. Therefore, the amount of electrons and holes accumulated in the n-type drift layer 101 in the second conduction state is smaller than that in the first conduction state. For this reason, the n-type drift layer 101 undergoes conductivity modulation due to the accumulated electrons and holes, and its resistance is lowered, so that a current flows from the collector electrode 113 to the emitter electrode 114, but in the second conduction state, the conduction conductivity is reduced. The degree of degree modulation and resistance reduction is small compared to the first conduction state.

FIG. 11 is a diagram showing a comparison of charge density distributions in the n-type drift layer 101 when the switching element for power conversion (semiconductor device 100) is in the first conduction state or the second conduction state. In FIG. 11, the horizontal axis represents the charge density, and the vertical axis represents the depth with the direction from the emitter electrode 114 to the collector electrode 113 being positive.
As shown in FIG. 11, the charge density distribution 131 in the second conduction state is smaller than the charge density distribution 130 in the first conduction state. That is, the charge density distribution 131 has a smaller charge density at any depth.

FIG. 12 is a diagram comparing voltage-current characteristics when the power conversion switching element (semiconductor device 100) is in the first conduction state or the second conduction state. In FIG. 12, the horizontal axis indicates the voltage of the collector electrode 113 with respect to the potential of the emitter electrode 114, and the vertical axis indicates the collector current with the direction of flowing from the collector electrode 113 to the emitter electrode 114 being positive.
As shown in FIG. 12, the voltage-current characteristic 133 in the second conduction state has less current flowing when the current at the same voltage is compared with the voltage-current characteristic 132 in the first conduction state. This is because the resistance value increases in the second conduction state because the number of stored carriers is small in the n-type drift layer and the degree of conductivity modulation is small in the second conduction state as compared with the first conduction state.

  FIG. 13 is a diagram illustrating an example of a circuit diagram symbol of the power conversion switching element. As shown in FIG. 13, a collector terminal 134 connected to the collector electrode 113, an emitter terminal 135 connected to the emitter electrode 114, a first gate terminal 136 connected to the first gate electrode 109, and a second gate. It is described as a four-terminal element with a second gate terminal 137 connected to the electrode 110.

Next, the reason why the turn-off loss is reduced by the power conversion switching element (semiconductor device 100) will be described using the circuit shown in FIG.
[Reduction of turn-off loss of semiconductor device 100]
FIG. 14 is a circuit diagram of a switching element for power conversion. FIG. 15 is a drive voltage and operation waveform diagram of the circuit shown in FIG.
As shown in FIG. 14, the cathode terminal of the diode 139 is connected to the positive electrode of the DC voltage source 138, the collector terminal of the power conversion switching element (semiconductor device 100) is connected to the anode terminal of the diode 139, and switching for power conversion is performed. The negative electrode of the DC voltage source 138 is connected to the emitter terminal of the element (semiconductor device 100). An inductor 141 is connected in parallel with the diode 139. The first drive voltage source 142 is connected between the first gate terminal and the emitter terminal of the power conversion switching element (semiconductor device 100), and the second drive voltage source is connected between the second gate terminal and the emitter terminal. 143 is connected.

As the initial state of the circuit shown in FIG. 14, the voltages (Vg1 and Vg2 respectively) of the first drive voltage source 142 and the second drive voltage source 143 are the switching elements for power conversion according to the first embodiment of the present invention. Assume that the potential of the emitter terminal of 140 is + 15V with reference to the potential.
A positive voltage is applied to the first gate terminal and the second gate terminal of the power conversion switching element (semiconductor device 100) with reference to the potential of the emitter terminal, and the power conversion switching element (semiconductor device 100). ) Is the first conduction state. The voltage of the DC voltage source 138 is Vcc, and it is assumed that the current I0 flows through the inductor 141. No current flows through the diode 139, and therefore all current I0 flowing through the inductor 141 flows through the power conversion switching element (semiconductor device 100). That is, the current value Is of the power conversion switching element (semiconductor device 100) is assumed to be equal to I0.

  The initial state is the state at time t = t0, and the drive voltages shown in FIGS. 15A and 15B are applied to the first drive voltage source 142 and the second drive voltage source 143. As described above, since the power conversion switching element (semiconductor device 100) is in the first conduction state at t = t0, it operates with low conduction loss. As described above, the low conduction loss operation is achieved in the first conduction state. At t = t1, the voltage of the second drive voltage source 143 is switched from + 15V to −15V.

Thereby, as shown in FIG.15 (c), the switching element (semiconductor device 100) for power conversion switches from a 1st conduction | electrical_connection state to a 2nd conduction | electrical_connection state. That is, the charge accumulated inside decreases. Thereafter, at t = t2, the voltage of the second drive voltage source 143 is switched from + 15V to −15V. As a result, all electron channels disappear and electron injection disappears, so that hole injection is also stopped and turn-off is started. During the turn-off, the accumulated charge is released to generate a tail current 144, and a loss (turn-off loss) determined by the product of the tail current 144 and the collector voltage occurs.
Here, in the power conversion switching element (semiconductor device 100), the internal charge is reduced by switching from the first conduction state to the second conduction state immediately before the turn-off. For this reason, the tail current generated due to the accumulated charge is reduced, and therefore the turn-off loss is also reduced.

  As described above, the semiconductor device 100 according to the present embodiment includes a plurality of trenches 104 that reach the n-type drift layer 101 from the surface of the p-type channel layer 103 through the p-type channel layer 103, and inside the trench 104. In the first and second gate electrodes 107 and 108 configured to include the insulating film 106 formed around the formed conductor 105, and in the n-type drift layer 101, the first and second gate electrodes 107 are formed. , 108 and a p-type floating region 112 selectively formed in the lower portion of the trench 104. When a voltage is applied to the first and second gate electrodes 107 and 108 such that the potential difference based on the potential of the emitter electrode 114 is 0 V, the p-type channel layer 103 and the p-type floating region 112 are applied. N-type drift layer 101 is interposed in a state of the first conductivity type, and a voltage is applied to first gate electrode 107 such that the potential difference with reference to the potential of emitter electrode 114 is a positive value, and When a voltage with a negative potential difference with respect to the potential of the emitter electrode 114 is applied to the second gate electrode 108, the p-type channel layer 103 and the p adjacent to the second gate electrode 110 are applied. The type floating region 112 is connected to each other via the n-type drift layer 101 inverted to the second conductivity type.

  As described above, since the internal charge is reduced by switching from the first conduction state to the second conduction state immediately before the turn-off, the tail current generated due to the accumulated charge is reduced, and the switching loss at the turn-off is reduced. Can be reduced. For example, by using the semiconductor device 100 of this embodiment for an IGBT, the effect of reducing the switching loss of the IGBT can be improved.

(Second Embodiment)
FIG. 16 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to the second embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals, and description of overlapping portions is omitted.
As shown in FIG. 16, the semiconductor device 200 is formed on a first conductivity type (here, p-type) p-type drift layer 201 (first semiconductor layer) and a first surface 201 a of the p-type drift layer 201. An n-type collector layer 202 (second semiconductor layer) of the second conductivity type (here, n-type) and an n-type channel layer 203 (second of the second conductivity type formed on the second surface 201b of the p-type drift layer 201). 3 semiconductor layers) and a plurality of trenches 104 that reach the p-type drift layer 201 through the n-type channel layer 203 from the surface of the n-type channel layer 203.

  In addition, the semiconductor device 200 includes at least two gate electrodes 107 and 108 configured to include a conductor 105 formed inside the trench 104 and an insulating film 106 formed around the conductor 105, and an n-type channel. In the surface of the layer 203, the first conductivity type p-type source region 211 (fourth semiconductor layer) formed adjacent to the gate electrodes 107 and 108, and the p-type drift layer 201 adjacent to the gate electrodes 107 and 108. The n-type floating region 212 (fifth semiconductor layer) of the second conductivity type that is selectively formed without being in contact with the n-type channel layer 203 and the emitter electrode 114 formed on the surface of the n-type channel layer 203 And a collector electrode 113 formed on the surface of the n-type collector layer 202.

  In addition, the semiconductor device 200 includes at least two gate electrodes 107 and 108 including a first gate electrode 109 and a second gate electrode 110 in which applied voltages are controlled independently of each other. When a voltage with a potential difference of 0 V with respect to the potential of the emitter electrode 114 is applied to the second gate electrode 110, the n-type drift layer 101 is interposed between the n-type channel layer 203 and the n-type floating region 212. Is interposed in the state of the first conductivity type. Further, in the semiconductor device 200, a voltage is applied to the first gate electrode 109 so that a potential difference with reference to the potential of the emitter electrode 114 is a negative value, and the potential of the emitter electrode 114 is applied to the second gate electrode 110. When a voltage that makes the reference potential difference a positive value is applied, the second conductivity type is between the n-type channel layer 203 and the n-type floating region 212 adjacent to the second gate electrode 110. Are connected to each other via the p-type drift layer 201 inverted to.

The semiconductor device 200 according to the present embodiment can take a configuration in which all the n-type and p-type of the semiconductor device 100 of FIG. 1 are inverted. In this case, all the voltages applied to the electrodes are also reversed in polarity.
As described above, even in the semiconductor device 200 in which all the n-type and p-type of the semiconductor device 100 are inverted, the internal charges are changed by switching from the first conduction state to the second conduction state immediately before the turn-off. Since it decreases, the switching loss at the time of turn-off can be reduced.

(Third embodiment)
A third embodiment in which the semiconductor device of the present invention is applied to a power conversion device will be described.
FIG. 17 is a circuit diagram showing a power conversion device 500 employing the power conversion switching element (semiconductor device 100) according to the first embodiment. FIG. 17 shows an example of a circuit configuration of the power conversion apparatus 500 of the present embodiment and a connection relationship between the DC power supply Vcc and the three-phase AC motor 330 (AC load).
In the power conversion device 500 of this embodiment, the semiconductor device 100 of the first embodiment is used as the power switching elements 501 to 506. The power switching elements 501 to 506 are, for example, IGBTs.

As shown in FIG. 17, the power conversion apparatus 500 of the second embodiment includes a pair of direct current terminals P terminal 531 and N terminal 532, and U terminals 533 that are the same number of AC terminals as the number of AC output phases. A V terminal 534 and a W terminal 535 are provided.
In addition, a switching leg is provided that includes a series connection of a pair of power switching elements 501 and 502 and outputs an U terminal 533 connected to the series connection point. Further, the power switching elements 503 and 504 having the same configuration are connected in series, and a switching leg having an output of a V terminal 534 connected to the series connection point is provided. Further, the power switching elements 505 and 506 having the same configuration are connected in series, and a switching leg having an output of a W terminal 535 connected to the series connection point is provided.

The switching legs for three phases including the power switching elements 501 to 506 are connected between the DC terminals of the P terminal 531 and the N terminal 532, and DC power is supplied from a DC power supply Vcc (not shown). The U terminal 533, the V terminal 534, and the W terminal 535, which are three-phase AC terminals of the power conversion device 500, are connected to the three-phase AC motor 530 as a three-phase AC power source.
Diodes 521 to 526 are connected in antiparallel to power switching elements 501 to 506, respectively. Driving circuits 511 to 516 control the input terminals of the gates of the power switching elements 501 to 506 made of IGBT. The drive circuits 511 to 516 are comprehensively controlled by an overall control circuit (not shown).
The power switching elements 501 to 506 are appropriately and comprehensively controlled by the drive circuits 511 to 516, respectively, and the DC power of the DC power supply 531 is converted into three-phase AC power, and the U terminal 533, the V terminal 534, and the W terminal 535 is output.

In the operation of the power conversion apparatus 500, it is possible to reduce the turn-off loss of each switching element by driving the power switching elements 501 to 506 by the method described in FIG. Thereby, a highly efficient power converter can be realized.
Note that the power conversion switching element (semiconductor device 200) according to the second embodiment may be used, and similar effects can be obtained.
Further, in the present embodiment, the case of the inverter device has been described as an application example of the semiconductor device of the present invention to the power conversion device. However, the present invention is not limited to this, and a DC-DC converter or an AC-DC converter is not limited thereto. It can also be applied to other power conversion devices.

(Other embodiments)
As mentioned above, although each embodiment was explained in full detail with reference to drawings, this invention is not limited to these embodiment, Even if there exist a process, manufacture, a design change, etc. of the range which does not deviate from the summary of this invention. Well, here are some examples:
For example, in the first embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, as in the second embodiment, the first conductivity type is p-type and the second conductivity type is The same holds true for n-type.

  The present invention can be applied not only to the IGBT but also to a semiconductor device having a trench gate structure.

  Further, a part of the configuration of an embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of an embodiment.

  In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment. In addition, the electrical wiring indicates what is considered necessary for the description, and does not necessarily indicate all electrical wiring on the product.

100, 200 Semiconductor device 101 n-type drift layer (first semiconductor layer)
102 p-type collector layer (second semiconductor layer)
103 p-type channel layer (third semiconductor layer)
104 trench 105 conductor 106 insulating film 107, 108 gate electrode 111 n-type source region (fourth semiconductor layer)
112 p-type floating region (fifth semiconductor layer)
109 First gate electrode 110 Second gate electrode 114 Emitter electrode 107 First insulated gate set 108 Second insulated gate set 115,116 Contact region 117,118 Contact 201 P-type drift layer (first semiconductor layer)
202 n-type collector layer (second semiconductor layer)
203 n-type channel layer (third semiconductor layer)
211 p-type source region (fourth semiconductor layer)
212 n-type floating region (fifth semiconductor layer)
500 Power Converter 501 to 506 Power Switching Element 521 to 526 Diode 511 to 516 Drive Circuit

Claims (5)

A plurality of trenches extending from the surface of the channel layer to the drift layer through the channel layer;
First and second gate electrodes each including an insulating film formed around a conductor formed inside the trench;
A floating region that is adjacent to the first and second gate electrodes and is selectively formed in a lower portion of the trench in the drift layer;
When a voltage with a potential difference of 0 V with respect to the potential of the emitter electrode is applied to the first and second gate electrodes, a drift layer is of the first conductivity type between the channel layer and the floating region. In the state of
A voltage is applied to the first gate electrode so that a potential difference based on the potential of the emitter electrode is a positive value, and a potential difference based on the potential of the emitter electrode is a negative value applied to the second gate electrode. When the voltage is applied, the channel layer and the floating region adjacent to the second gate electrode are connected to each other through the drift layer inverted to the second conductivity type. A semiconductor device. A first semiconductor layer of a first conductivity type;
A second conductivity type second semiconductor layer formed on the first surface of the first semiconductor layer;
A third semiconductor layer of a second conductivity type formed on the second surface of the first semiconductor layer;
A plurality of trenches reaching from the surface of the third semiconductor layer to the first semiconductor layer through the third semiconductor layer;
At least two gate electrodes configured to include a conductor formed inside the trench and an insulating film formed around the conductor;
A first conductivity type fourth semiconductor layer formed adjacent to the gate electrode on a surface of the third semiconductor layer;
A fifth semiconductor layer of a second conductivity type that is selectively formed in the first semiconductor layer adjacent to the gate electrode and without being in contact with the third semiconductor layer;
An emitter electrode formed on a surface of the third semiconductor layer;
A collector electrode formed on the surface of the second semiconductor layer,
At least two of the gate electrodes are configured to include a first gate electrode and a second gate electrode in which applied voltages are controlled independently of each other,
When a voltage is applied to the first gate electrode and the second gate electrode so that a potential difference based on the potential of the emitter electrode is 0 V, the third semiconductor layer and the fifth semiconductor layer A first semiconductor layer interposed in a state of the first conductivity type,
A voltage is applied to the first gate electrode so that a potential difference based on the potential of the emitter electrode is a positive value, and a potential difference based on the potential of the emitter electrode is applied to the second gate electrode as a negative value. When the voltage is applied, the first semiconductor layer is inverted to the second conductivity type between the third semiconductor layer and the fifth semiconductor layer adjacent to the second gate electrode. A semiconductor device connected to each other via a semiconductor device. A first semiconductor layer of a first conductivity type;
A second conductivity type second semiconductor layer formed on the first surface of the first semiconductor layer;
A third semiconductor layer of a second conductivity type formed on the second surface of the first semiconductor layer;
A plurality of trenches reaching from the surface of the third semiconductor layer to the first semiconductor layer through the third semiconductor layer;
At least two gate electrodes configured to include a conductor formed inside the trench and an insulating film formed around the conductor;
A first conductivity type fourth semiconductor layer formed adjacent to the gate electrode on a surface of the third semiconductor layer;
A fifth semiconductor layer of a second conductivity type that is selectively formed in the first semiconductor layer adjacent to the gate electrode and without being in contact with the third semiconductor layer;
An emitter electrode formed on a surface of the third semiconductor layer;
A collector electrode formed on the surface of the second semiconductor layer,
At least two of the gate electrodes are configured to include a first gate electrode and a second gate electrode in which applied voltages are controlled independently of each other,
When a voltage is applied to the first gate electrode and the second gate electrode so that a potential difference based on the potential of the emitter electrode is 0 V, the voltage is applied between the third semiconductor layer and the fifth semiconductor layer. The first semiconductor layer is interposed in a state of a first conductivity type;
A voltage is applied to the first gate electrode so that a potential difference with respect to the potential of the emitter electrode is a negative value, and a potential difference with respect to the potential of the emitter electrode is a positive value to the second gate electrode. When the voltage is applied, the first semiconductor layer is inverted to the second conductivity type between the third semiconductor layer and the fifth semiconductor layer adjacent to the second gate electrode. A semiconductor device connected to each other via From a state in which a voltage having a positive potential difference with respect to the potential of the emitter electrode is applied to the first gate electrode and the second gate electrode, the potential of the emitter electrode is referenced to the first gate electrode. When switching to a state where a negative voltage is applied,
A voltage based on the potential of the emitter electrode is applied to the second gate electrode prior to switching to a state where a voltage having a negative value based on the potential of the emitter electrode is applied to the first gate electrode. 4. The semiconductor device according to claim 1, further comprising: a drive circuit that switches to a state in which a voltage having a negative value is applied. 5. The first leg upper arm switching device and the first leg lower arm flywheel diode are the first pair,
The switching device of the lower arm of the first leg and the flywheel diode of the upper arm of the first leg are in a second pair,
The second leg upper arm switching device and the second leg lower arm flywheel diode in a third pair,
The switching device of the lower arm of the second leg and the flywheel diode of the upper arm of the second leg are a fourth pair,
The third leg upper arm switching device and the third leg lower arm flywheel diode are the fifth pair,
The sixth leg of the third leg lower arm switching device and the third leg upper arm flywheel diode,
A power conversion device configured to include first to sixth pairs,
Each of the first to sixth pairs is configured as part of a semiconductor device,
The semiconductor device includes:
A switching device;
A diode,
The switching device in each of the first to sixth pairs is configured by the semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device includes:
The flywheel diode in each of the first to sixth pairs is constituted by a diode included in the semiconductor device.

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