CN113838745A - 用于制造沟槽mosfet的方法 - Google Patents

用于制造沟槽mosfet的方法 Download PDF

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CN113838745A
CN113838745A CN202110635363.2A CN202110635363A CN113838745A CN 113838745 A CN113838745 A CN 113838745A CN 202110635363 A CN202110635363 A CN 202110635363A CN 113838745 A CN113838745 A CN 113838745A
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trench
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M·林
O·鲁施
T·埃尔巴赫尔
T·希莱杰夫斯基
H·施利希廷
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Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
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Abstract

在一种用于制造沟槽MOSFET的方法中，在单晶半导体层中产生沟槽，然后首先以散射氧化物层并且随后以多晶硅层在整个表面上覆盖表面，从而至少部分地以所述多晶硅填满所述沟槽。然后，将所述多晶硅层平坦化，直至所述沟槽之间的区域中的半导体层的表面为止。通过对所述沟槽中的多晶硅的裸露表面进行热氧化物，在所述多晶硅上产生厚的SiO2层，所述SiO2层用作用于后续注入步骤的注入掩模。随后进行用于产生源区和阱区的离子注入步骤以及用于完成所述MOSFET的其他步骤。所述方法使得能够以成本有利的方式在SiC中制造沟槽MOSFET，而无需用于产生所述源区和所述阱区的光刻设备。

Description

用于制造沟槽MOSFET的方法
技术领域
本发明涉及一种用于制造沟槽MOSFET的方法，在该方法中，在进行离子注入(Ionenimplantation)以产生源区和阱区之前，在单晶半导体层中产生沟槽，并且至少部分地以多晶硅填满该沟槽。
沟槽MOSFET(MOSFET：Metal-Oxide-Semiconductor Field-Effect Transistor，金属氧化物半导体场效应晶体管)是垂直构建的晶体管构件，其中，晶体管沟道垂直延伸。相对于平面式MOSFET，沟槽MOSFET具有以下优点：省去平面式MOSFET中存在的JFET区和与此相关的电阻。因此，沟槽MOSFET具有较低的电阻，并且由于其更大的集成密度而能够节省芯片面积并且因此节省制造成本。
背景技术
在沟槽MOSFET的制造中，至今经常使用光刻掩模，借助这些光刻掩模，所有待转移到构件中的结构都通过相应的透明和不透明的区进行限定。对于掩模匹配的结构转移，具有相应高的分辨能力和调整能力的光刻掩模是必要的，其中，在此也不能低于技术决定的限制。这导致相应高的成本。为了在通过离子注入产生源区和阱区时避免这种光刻掩模，已知自调整的制造工艺。
关于硅(Si)中的沟槽MOSFET的自调整制造工艺的现有技术是在完成沟槽结构的产生之后产生自调整的n+源极接触或p阱区，也称为“沟槽在先(Trench-First)”。US9735266 B2示出这种制造技术的示例。在此，首先将沟槽蚀刻到单晶硅层中直至40μm的深度，并且随后热生长薄的氧化物。随后沉积多晶硅层，以便至少部分地以多晶硅填满沟槽。通过干法蚀刻去除存在于沟槽之间的多晶硅。随后在整个表面上沉积薄氧化物层，并且在沟槽壁处借助湿法蚀刻工艺(BOE：Buffered-Oxide-Etch，缓冲氧化物刻蚀)将其去除。在将硅层局部地、各向同性地蚀刻直至多晶硅的表面为止之后，进行自调整的n+源极和p阱注入。该技术适用于硅中的沟槽MOSFET的产生，然而，由于不同的材料特性而不能相同地转移到碳化硅(SiC)上。
因此，对于由碳化硅制成的单晶层中的沟槽MOSFET的制造，至今使用不同的自调整制造技术，其中，在完成离子注入之后产生沟槽结构(“沟槽在后(Trench-Last)”)。在US5614749 A中描述这种制造技术的示例。原则上，在此首先将n+源极和p阱区在整个表面上注入到SiC层的有源区域中。然后，随后才将沟槽蚀刻到这些注入区域中。然而，在此，蚀刻工艺的控制是困难的，因为蚀刻工艺取决于区域的掺杂。
本发明的任务在于，说明一种用于制造沟槽MOSFET的方法，该方法适用于在单晶SiC层中制造沟槽MOSFET，在没有用于产生源区和阱区的光刻掩模的情况下也能够应对，并且使得能够制造均匀的沟槽结构。
发明内容
本发明借助一种用于制造沟槽MOSFET的方法来解决。该方法的有利构型可以从以下描述以及实施例中得出。在所提出的方法中，首先通过合适的蚀刻工艺在单晶的、尤其是外延的半导体层中产生沟槽。随后，优选地在整个表面上沉积散射氧化物层(Streuoxid-Schicht)并且随后沉积多晶硅层，从而至少部分地以多晶硅填满沟槽。然后，优选地通过干法蚀刻，将多晶硅层平坦化，直至沟槽之间的半导体层的表面为止。该方法的特征在于，在用于制造源区和阱区(尤其是n+源极和p阱)的注入步骤之前，通过对多晶硅的裸露表面进行热氧化在沟槽中的多晶硅上产生足够厚的SiO2层，该SiO2层用作用于后续注入步骤的注入掩模并且防止沟槽侧壁上的导电沟道的危险，否则，这些导电沟道可能作为未经完美平坦化的多晶硅表面的后果而形成。通过热氧化物层的厚度也能够影响晶体管沟道中的掺杂并且因此影响阈值电压和沟道长度。热氧化物层的厚度可以通过氧化时间和氧化时的温度来控制。在此，多晶硅的热氧化可以一直执行，直至热氧化物层的表面的水平达到沟槽之间(MESA结构)的半导体层表面的水平为止。通常——但是并非在任何情况下——产生具有>100nm厚度的热氧化物层。
所提出的制造方法在没有用于产生构件的源区和阱区的光刻步骤的情况下也能够应对，并且因此不取决于光刻设备的分辨能力和调整能力。通过借助沟槽中的氧化多晶硅(热氧化物层)进行的可靠注入掩蔽，将连贯的、直接邻接沟槽边缘的源区和阱区如此实现，使得消除在沟槽侧壁上形成导电沟道的风险。在所提出的方法中，也可以通过选择多晶硅上的热氧化物厚度来设置晶体管的沟道区域中的掺杂。这影响启动电压(Einsatzspannung)和作为沟道电阻的关键因素的沟道长度。同时，与“沟槽在后”工艺相比，在该方法中没有出现构件结构的介电强度的降低。在后者的情况下，阱掺杂的大小限于低的掺杂物浓度。
在所提出的方法的一种有利的构型中，在用于在沟槽中的多晶硅上产生足够厚的热SiO2层或氧化物层的热氧化之后，在整个表面上沉积薄的散射氧化物层，因为最初沉积的薄散射氧化物层可能在多晶硅的平坦化中在某些位置处已经去除。
在产生第一和第二掺杂类型的源区和阱区之后，将具有位于其上的热氧化物层的多晶硅从沟槽中去除。随后，可以通过掩蔽工艺通过离子注入产生p+区域，这些p+区域用作屏蔽。然后，将栅极氧化物层以及再次将多晶硅层沉积到沟槽中并且进行平坦化。作为后续步骤，施加合适的金属化以用于创建用于栅极、源极和漏极的欧姆接触。
所提出的方法特别适用于在单晶的、尤其是外延生长的SiC中产生沟槽MOSFET，然而，原则上，也可以用于在其他半导体材料(例如Si或GaN)中产生这种MOSFET。
附图说明
以下结合附图基于实施例再次更详细地阐述所提出的方法。在此示出：
图1.1-1.9示出用于根据所提出的方法制造沟槽MOSFET的各个制造步骤；以及
图2示出基于TCAD(Technology Computer-Aided Design，技术计算机辅助设计)工艺模拟的、具有和不具有所提出的方法的热氧化物层的n+源极注入的比较。
具体实施方式
以下基于图1.1至图1.9，再次通过示例阐述所提出的、用于在外延SiC层中制造沟槽MOSFET的方法。在此，MOSFET的制造在外延生长的SiC层2中进行，该外延生长的SiC层具有在由SiC制成的n+衬底1上的n-掺杂。首先，在SiC层2中产生沟槽3。为此，借助PECVD(PECVD：Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积)来施加在该示例中具有1000nm厚度的、由SiO2制成的硬掩膜4。然后，通过干法蚀刻在SiC层2中产生沟槽3，如这在图1.1中所表明的那样。通过高温处理使沟槽3的边缘平滑。随后，在整个表面上沉积薄的散射氧化物层5(参见图1.2)，这旨在防止后续注入步骤中的晶格引导效应(Gitterführungseffekte)(Channeling，沟道效应)。然后沉积由多晶硅6制成的、足够厚度的平坦化层，通过该平坦化层，至少部分地填满沟槽3。在此，沉积在整个表面上进行，即也在沟槽3之间的MESA结构上进行。随后，借助干法蚀刻工艺将表面平坦化，其中，从MESA结构去除多晶硅，如这在图1.3中可以看到的那样。干法蚀刻工艺相对于处于多晶硅层下方的氧化物层(散射氧化物5)表现出选择性，并且当MESA结构的氧化物表面从多晶硅层裸露出时结束。在此，处于沟槽3中的多晶硅6得以保留。
在下一工艺步骤中，在沟槽中进行多晶硅6的热氧化，以便在多晶硅6上产生足够厚的热SiO2层7。这在图1.4中示出，并且例如可以通过950℃下的湿法氧化进行。针对湿式氧化所选择的、相对较低的温度(<1000℃)具有以下优点：碳化硅在该温度下几乎不氧化(仅几纳米)，相反，多晶硅更加快速地或更加强烈地氧化。将该热SiO2层7产生得如此之厚，使得其形成可靠的注入掩蔽，以用于后续的、用于产生n+源区和p阱区的注入步骤。通过该层消除在沟槽侧壁上形成导电沟道的风险。在本示例中，随后还将薄的散射氧化物层8沉积在整个表面上，以便取代通过前述干法蚀刻工艺可能去除的散射氧化物。首先进行用于产生n+源区9的注入步骤(图1.5)，并且随后进行用于产生p阱区10的注入步骤(图1.6)。在该示例中，在将衬底倾斜+7°和-7°的角度的情况下进行用于产生p阱区10的离子注入，以便再次避免可能的晶格引导效应(沟道效应)。
在本示例中可以看到，使用+7°的通常的单向倾斜角导致不对称的注入区。两次注入(一次在+7°下，一次在-7°下，分别以一半剂量)开销相对较高。由于从产生n+源区9(图1.5)和p+屏蔽(p+区域11；图1.7)的模拟中得出，以+7°和-7°的注入相对于0°下的注入之间没有区别，因此选择0°的倾斜角用于进行注入以产生这些区域。相反地，从产生p阱区的模拟中得出，通过两次注入(一次在+7°下，一次在-7°下，分别以一半剂量)，与在0°的角度下进行注入的情况下相比，实现更大的沟道长度。因此，尽管开销更高，仍然将+7°和-7°的倾斜角用于注入以产生p阱区10(图1.6)。
然后，通过蚀刻步骤从沟槽3中去除具有处于其上的热氧化物层7的多晶硅6，并且借助光刻胶掩膜12执行p+区域11的注入(图1.7)。图1.8示出执行退火步骤之后的结果。在退火之后，由于扩散效应，p阱区10在沟槽侧壁附近向上翘曲，如这从图1.8中可以看到的那样。
随后，以已知的方式，将多晶硅层14沉积在先前所沉积的、用作栅极氧化物的SiO2层13上，以及施加金属化层以用于实现欧姆接触，如这针对源极接触15和漏极接触16而在图1.9中所示出的那样。
所提出的制造方法中的一个关键步骤在于在沟槽3中的多晶硅6上产生足够厚的热SiO2层7，通过该层消除在沟槽侧壁上形成导电沟道的风险。为此，图2基于KMC(Kinetic-Monte-Carlo，动力学蒙特卡洛)模拟示出该热氧化物层7对n+源区9的掺杂的变化过程的影响(在此以高度简化的方式示出)。在该图的左侧部分中可以看到在没有该氧化物层的情况下注入之后的情况，在该图的右侧部分中可以看到在具有该氧化物层的情况下注入之后的情况。能够清楚地看到n+源区9在沟槽3的侧壁上的不同翘曲。因此，通过该热氧化物层7的厚度可以影响或设置晶体管的沟道区17(参见图1.8)中的掺杂。这影响启动电压和作为沟道电阻的关键因素的沟道长度。
附图标记列表
1 SiC衬底
2 外延SiC层
3 沟槽
4 SiO2硬掩模
5 散射氧化物层(SiO2)
6 多晶硅
7 热SiO2层
8 散射氧化物层(SiO2)
9 n+区域
10 p阱区
11 p+区域
12 光刻胶掩模
13 SiO2层
14 多晶硅层
15 源极欧姆接触
16 漏极欧姆接触
17 沟道

Claims (8)

1.一种用于制造沟槽MOSFET的方法，所述方法具有以下步骤：
在单晶半导体层(2)中产生沟槽(3)，
沉积散射氧化物层(5)，并且随后
沉积多晶硅层，从而至少部分地以多晶硅(6)填满所述沟槽(3)，
将所述多晶硅层平坦化，直至所述沟槽(3)之间的半导体层的表面为止，
对所述沟槽(3)中的所述多晶硅(6)的裸露表面进行热氧化，以便在所述沟槽(3)中的所述多晶硅(6)上产生热SiO2层(7)，所述热SiO2层形成用于随后的注入步骤的注入掩模，
执行第一离子注入，以产生第一掺杂类型的源区(9)，
执行第二离子注入，以在所述源区(9)下方产生第二掺杂类型的阱区(10)，
从所述沟槽(3)中去除具有所述热SiO2层(7)的多晶硅(6)，以及
在所述沟槽(3)中，沉积氧化物层(13)，并且随后沉积多晶硅层(14)。
2.根据权利要求1所述的方法，
其特征在于，
将所述热SiO2层(7)产生得如此之厚，使得所述热SiO2层的表面位于所述沟槽(3)之间的半导体层的表面的水平上。
3.根据权利要求1或2所述的方法，
其特征在于，
通过所述第一离子注入进行n+掺杂，并且通过所述第二离子注入进行p型掺杂。
4.根据权利要求1至3中任一项所述的方法，
其特征在于，
在所述第二离子注入之后进行退火。
5.根据权利要求1至4中任一项所述的方法，
其特征在于，
在执行所述第一离子注入之前，在整个表面上沉积另一散射氧化物层(8)。
6.根据权利要求1至5中任一项所述的方法，
其特征在于，
通过湿法蚀刻进行所述沟槽(3)之间的区域中的多晶硅层的去除。
7.根据权利要求1至6中任一项所述的方法，
其特征在于，
在所述退火之前，通过掩蔽工艺和随后的第三离子注入，还产生第二掺杂类型的区域(11)，所述区域具有相对于所述阱区(10)提高的掺杂。
8.根据权利要求1至7中任一项所述的方法，所述方法用于在由碳化硅制成的半导体层(2)中制造沟槽MOSFET。
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