CN113823677B - 埋入式栅极通道的金属氧化物半导体场效晶体管及其制法 - Google Patents

埋入式栅极通道的金属氧化物半导体场效晶体管及其制法 Download PDF

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CN113823677B
CN113823677B CN202010558380.6A CN202010558380A CN113823677B CN 113823677 B CN113823677 B CN 113823677B CN 202010558380 A CN202010558380 A CN 202010558380A CN 113823677 B CN113823677 B CN 113823677B
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CN113823677A (zh
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熊昌铂
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United Microelectronics Corp
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Abstract

本发明公开一种埋入式栅极通道的金属氧化物半导体场效晶体管及其制法，其中该埋入式栅极通道的金属氧化物半导体场效晶体管，包含一介电层、一栅极以及一埋入式栅极通道区。介电层位于一基底上，其中介电层具有一凹槽。栅极设置于凹槽中，其中栅极包含一第一金属功函数层，其中第一金属功函数层具有一「一」字型剖面结构，且第一金属功函数层的各侧壁与凹槽的最接近的侧壁的一最小距离大于零。埋入式栅极通道区位于栅极正下方的基底中。

Description

埋入式栅极通道的金属氧化物半导体场效晶体管及其制法
技术领域
本发明涉及一种金属氧化物半导体场效晶体管及其制作方法，且特别是涉及一种埋入式栅极通道的金属氧化物半导体场效晶体管及其制作方法。
背景技术
在集成电路的制造过程中，场效晶体管(field effect transistor)是一种极重要的电子元件。现有的晶体管制作工艺是在基底上形成栅极结构之后，再在栅极结构相对两侧的基底中形成轻掺杂源/漏极结构(lightly doped drain,LDD)。接着，在栅极结构侧边形成间隙壁(spacer)，并以此栅极结构及间隙壁作为掩模，进行离子注入步骤，以于栅极结构及间隙壁侧边的基底中形成源极区以及漏极区。再者，如为埋入式通道的场效晶体管，会再另外掺杂通道区于栅极下方，以使载流子在源极区及漏极区流通时远离基底表面。
发明内容
本发明提出一种埋入式栅极通道的金属氧化物半导体场效晶体管及其制作方法，其在埋入式栅极通道正上方对应的部分栅极的区域形成金属功函数层，以降低漏电流并提升晶体管的可靠度。
本发明提供一种埋入式栅极通道的金属氧化物半导体场效晶体管，包含一介电层、一栅极以及一埋入式栅极通道区。介电层位于一基底上，其中介电层具有一凹槽。栅极设置于凹槽中，其中栅极包含一第一金属功函数层，其中第一金属功函数层具有一「一」字型剖面结构，且第一金属功函数层的各侧壁与凹槽的最接近的侧壁的一最小距离大于零。埋入式栅极通道区位于栅极正下方的基底中。
本发明提供一种制作埋入式栅极通道的金属氧化物半导体场效晶体管的方法，包含下述步骤。首先，提供一基底。接着，形成一埋入式栅极通道区于基底中。接续，形成一介电层于基底上，其中介电层具有一凹槽，且凹槽位于埋入式栅极通道区的正上方。之后，形成一第一金属功函数层于凹槽中，其中第一金属功函数层具有一「一」字型剖面结构，且第一金属功函数层的各侧壁与凹槽的最接近的侧壁的一最小距离大于零。
基于上述，本发明提出一种埋入式栅极通道的金属氧化物半导体场效晶体管及其制作方法，其形成具有一凹槽的一介电层于一基底上，设置一栅极于凹槽中，形成一埋入式栅极通道区于栅极正下方的基底中，其中此栅极包含一第一金属功函数层，第一金属功函数层具有一「一」字型剖面结构，且第一金属功函数层的各侧壁与凹槽的最接近的侧壁的一最小距离大于零。因此，在操作晶体管时所产生的热载流子可远离基底表面并流通于埋入式栅极通道区中，以降低对于栅极的冲击，减少次阈值漏电流(sub-threshold leakage)及栅极诱生漏极漏电流(gate induced drain leakage,GIDL)等漏电流，进而提升元件的可靠度。
附图说明
图1为本发明优选实施例中制作埋入式栅极通道的金属氧化物半导体场效晶体管的方法的剖面示意图；
图2为本发明优选实施例中制作埋入式栅极通道的金属氧化物半导体场效晶体管的方法的剖面示意图；
图3为本发明优选实施例中制作埋入式栅极通道的金属氧化物半导体场效晶体管的方法的剖面示意图；
图4为本发明优选实施例中制作埋入式栅极通道的金属氧化物半导体场效晶体管的方法的剖面示意图；
图5为本发明优选实施例中制作埋入式栅极通道的金属氧化物半导体场效晶体管的方法的剖面示意图；
图6为本发明优选实施例中制作埋入式栅极通道的金属氧化物半导体场效晶体管的方法的剖面示意图；
图7为本发明优选实施例中制作埋入式栅极通道的金属氧化物半导体场效晶体管的方法的剖面示意图；
图8为本发明优选实施例中制作埋入式栅极通道的金属氧化物半导体场效晶体管的方法的剖面示意图；
图9为本发明优选实施例中制作埋入式栅极通道的金属氧化物半导体场效晶体管的方法的剖面示意图。
主要元件符号说明
2：垫氧化层
10：量子阱
20：绝缘结构
30：埋入式栅极通道区
40、136a：氧化层
50：间隙壁
110：基底
122：轻掺杂源极区
124：轻掺杂漏极区
130：牺牲栅极
132：栅极介电层
132a：缓冲层
132b：高介电常数介电层
134：栅极电极
136：盖层
136b：氮化层
142：源极区
144：漏极区
150：介电层
162、162’、168：阻障层
164：第一金属功函数层
164’：金属功函数层
166：第二金属功函数层
166a：部分
169：低电阻率材料
d1：深度
d2：最小距离
t1、t2：厚度
E1、E2：端部
E3、E4：端
M：金属栅极
R：凹槽
S1：表面
S2、S4：侧壁
S3：底面
T1、T2：侧壁部
W：宽度
具体实施方式
图1～图9绘示本发明优选实施例中制作埋入式栅极通道的金属氧化物半导体场效晶体管的方法的剖面示意图。本实施例为形成一中电压(medium voltage)金属氧化物半导体场效晶体管，但本发明也可应用于逻辑(低电压)晶体管或输出/输入IO(高电压)晶体管等。如图1所示，提供一基底110，其中基底110例如是一硅基底、一含硅基底(例如SiC)、一三五族基底(例如GaN)、一三五族覆硅基底(例如GaN-on-silicon)、一石墨烯覆硅基底(graphene-on-silicon)、一硅覆绝缘(silicon-on-insulator，SOI)基底或一含外延层的基底等半导体基底。视欲形成的晶体管电性可掺杂深N阱或深P阱等一量子阱10于基底110中。在本实施例中，量子阱10可例如为一P型阱。
形成绝缘结构20于基底110中，以电性绝缘各晶体管。绝缘结构20可例如为一浅沟槽绝缘(shallow trench isolation,STI)结构，其例如以一浅沟槽绝缘制作工艺形成，但本发明不以此为限。形成绝缘结构20的方法可例如包含下述步骤，但本发明不限于此。形成一硬掩模层(未绘示)于基底110上。在本实施例中，硬掩模层(未绘示)由下而上包含堆叠的一垫氧化层(未绘示)以及一垫氮化层(未绘示)。继之，进行一蚀刻制作工艺，图案化垫氮化层(未绘示)以及垫氧化层(未绘示)，而形成图案化的一硬掩模层(未绘示)，其由下而上包含一垫氧化层2以及一垫氮化层(未绘示)，以定义出欲于基底110中形成的沟槽的位置。之后，进行一蚀刻制作工艺，而于基底110中形成沟槽，并将绝缘结构20形成于沟槽中。最后，移除垫氮化层(未绘示)。
形成一埋入式栅极通道区30于基底110中。在本实施例中，埋入式栅极通道区30具有N型，其可例如掺杂砷，但本发明不限于此。在一优选的实施例中，自基底110的一表面S1至埋入式栅极通道区30的一深度d1为400～900埃。如此，在操作晶体管时所产生的热载流子可远离基底110表面S1并流通于埋入式栅极通道区30中，以减少对于形成于基底110上的栅极的冲击，减少次阈值漏电流(sub-threshold leakage)及栅极诱生漏极漏电流(gateinduced drain leakage,GIDL)等漏电流，进而提升元件的可靠度。
如图2所示，进行例如一掺杂制作工艺，以形成一轻掺杂源极区122及一轻掺杂漏极区124于基底110中。在本实施例中，轻掺杂源极区122及轻掺杂漏极区124具有N型，其可例如掺杂砷，但本发明不限于此。
如图3～图4所示，形成一牺牲栅极130于基底110上，使轻掺杂源极区122以及轻掺杂漏极区124设置于牺牲栅极130侧边的基底110中并部分位于牺牲栅极130正下方。在本实施例中，如图3所示，先移除垫氧化层2，再形成一氧化层40于绝缘结构20之间的基底110上。如图4所示，形成牺牲栅极130于氧化层40上，再形成间隙壁50于牺牲栅极130侧边。牺牲栅极130可由下而上包含一栅极介电层132、一栅极电极134以及一盖层136，其中栅极介电层132可例如包含一缓冲层132a及一高介电常数介电层132b，栅极电极134可例如为一多晶硅栅极，而盖层136可例如包含一氧化层136a以及一氮化层136b；间隙壁50可例如为包含氧化硅、氮化硅或氮氧化硅等的单层或多层间隙壁，但本发明不限于此。形成牺牲栅极130以及间隙壁50的方法为本领域所熟知，在此不再赘述。
其后，进行例如一掺杂制作工艺，以形成一源极区142及一漏极区144于牺牲栅极130侧边的基底110中。在本实施例中，源极区142及漏极区144具有N型，其可例如掺杂砷，但本发明不限于此。
如图5所示，可先全面覆盖一毯覆式介电层(未绘示)于牺牲栅极130、间隙壁50以及基底110上，再例如以一化学机械研磨(chemical mechanical polishing,CMP)制作工艺平坦化毯覆式介电层，以形成一介电层150于牺牲栅极130侧边的基底110上，并同时完全移除氮化层136b以及选择性移除部分的氧化层136a以及部分的间隙壁50。在本实施例中介电层150为一层间介电层，其可例如为一氧化层。
之后，完全移除氧化层136a以及栅极电极134，以形成一凹槽R，并暴露出栅极介电层132，如图6所示。在本实施例中，凹槽R位于埋入式栅极通道区30的正上方，用以制作一埋入式栅极通道的金属氧化物半导体场效晶体管。
如图7～图8所示，形成一阻障层162’及一第一金属功函数层164于凹槽R中。如图7所示，可先依序形成阻障层162’以及一金属功函数层164’顺应覆盖凹槽R的侧壁S2、凹槽R的一底面S3以及介电层150。如图8所示，图案化金属功函数层164’，以移除金属功函数层164’覆盖底面S3的二端部E1/E2，以及金属功函数层164’覆盖凹槽R的侧壁S2以及介电层150的侧壁部T1/T2，因而形成第一金属功函数层164，其中第一金属功函数层164具有一「一」字型剖面结构，且第一金属功函数层164不接触凹槽R的侧壁S2。
换言之，第一金属功函数层164的各侧壁S4与凹槽R的最接近的侧壁S2的一最小距离d2大于零。较佳者，第一金属功函数层164垂直重叠轻掺杂漏极区124的一宽度W为最小距离的0-4倍。如此，本发明的第一金属功函数层164位于轻掺杂源极区122以及轻掺杂漏极区124之间，且第一金属功函数层164垂直重叠轻掺杂源极区122以及轻掺杂漏极区124的部分，以在轻掺杂源极区122以及轻掺杂漏极区124之间形成埋入式通道，而热载流子流通于其中。再者，本发明的第一金属功函数层164没有垂直重叠源极区142以及漏极区144，否则本发明将无法形成埋入式通道。
在一优选实施例中，第一金属功函数层164完全垂直重叠埋入式栅极通道区30，以提升降低漏电流的能力。更佳者，第一金属功函数层164的两端E3/E4突出埋入式栅极通道区30，以确保第一金属功函数层164完全垂直重叠埋入式栅极通道区30。第一金属功函数层的一厚度t1例如为50～100埃。
如图9所示，形成一第二金属功函数层166顺应覆盖第一金属功函数层164以及凹槽R的侧壁S2。第一金属功函数层164以及第二金属功函数层166具有不同导电型。例如，第一金属功函数层164具有P型，而第二金属功函数层166具有N型。在本实施例中，先依序覆盖一第二金属功函数层(未绘示)、一阻障层(未绘示)以及一低电阻率材料(未绘示)，再平坦化低电阻率材料(未绘示)、阻障层(未绘示)以及第二金属功函数层(未绘示)以及阻障层162’，以形成一阻障层162、第二金属功函数层166、一阻障层168以及一低电阻率材料169于凹槽R中，因而形成一金属栅极M。由于第一金属功函数层164的各侧壁S4与凹槽R的最接近的侧壁S2的最小距离d2大于零，第二金属功函数层166的部分166a位于第一金属功函数层164以及凹槽R的侧壁S2之间。第二金属功函数层的一厚度t2例如为50～150埃。
综上所述，本发明提出一种埋入式栅极通道的金属氧化物半导体场效晶体管及其制作方法，其形成具有一凹槽的一介电层于一基底上，设置一栅极于凹槽中，形成一埋入式栅极通道区于栅极正下方的基底中，其中此栅极包含一第一金属功函数层，第一金属功函数层具有一「一」字型剖面结构，且第一金属功函数层的各侧壁与凹槽的最接近的侧壁的一最小距离大于零。因此，在操作晶体管时所产生的热载流子可远离基底表面并流通于埋入式栅极通道区中，以降低对于栅极的冲击，减少次阈值漏电流(sub-threshold leakage)及栅极诱生漏极漏电流(gate induced drain leakage,GIDL)等漏电流，进而提升元件的可靠度。
较佳者，一轻掺杂源极区以及一轻掺杂漏极区设置于栅极侧边的基底中，且第一金属功函数层垂直重叠轻掺杂源极区以及轻掺杂漏极区的部分。更佳者，第一金属功函数层垂直重叠轻掺杂漏极区的一宽度为最小距离的0～4倍。是以，本发明可在轻掺杂源极区以及轻掺杂漏极区之间形成埋入式通道，而热载流子流通于其中。再者，本发明的第一金属功函数层没有垂直重叠源极区以及漏极区，否则本发明将无法形成埋入式通道。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (16)

1.一种埋入式栅极通道的金属氧化物半导体场效晶体管，其特征在于，包含：
介电层，位于基底上，其中该介电层具有凹槽；
栅极，设置于该凹槽中，其中该栅极包含第一金属功函数层，其中该第一金属功函数层具有「一」字型剖面结构，且该第一金属功函数层的各侧壁与该凹槽的最接近的侧壁的最小距离大于零；
埋入式栅极通道区，位于该栅极正下方的该基底中；以及
源极区以及漏极区，设置于该栅极侧边的该基底中，
其中该第一金属功函数层设置于该源极区以及该漏极区之间，其中该第一金属功函数层没有垂直重叠该源极区以及该漏极区。
2.如权利要求1所述的埋入式栅极通道的金属氧化物半导体场效晶体管，还包含：
轻掺杂源极区以及轻掺杂漏极区，设置于该栅极侧边的该基底中。
3.如权利要求2所述的埋入式栅极通道的金属氧化物半导体场效晶体管，其中该第一金属功函数层设置于该轻掺杂源极区以及该轻掺杂漏极区之间，其中该第一金属功函数层垂直重叠该轻掺杂源极区以及该轻掺杂漏极区的部分。
4.如权利要求3所述的埋入式栅极通道的金属氧化物半导体场效晶体管，其中该第一金属功函数层垂直重叠该轻掺杂漏极区的一宽度为该最小距离的0～4倍。
5.如权利要求1所述的埋入式栅极通道的金属氧化物半导体场效晶体管，其中该第一金属功函数层完全垂直重叠该埋入式栅极通道区。
6.如权利要求5所述的埋入式栅极通道的金属氧化物半导体场效晶体管，其中该第一金属功函数层的两端突出该埋入式栅极通道区。
7.如权利要求1所述的埋入式栅极通道的金属氧化物半导体场效晶体管，其中该第一金属功函数层的一厚度为50～100埃。
8.如权利要求1所述的埋入式栅极通道的金属氧化物半导体场效晶体管，还包含：
第二金属功函数层，顺应覆盖该第一金属功函数层以及该凹槽的侧壁。
9.如权利要求8所述的埋入式栅极通道的金属氧化物半导体场效晶体管，其中该第二金属功函数层的部分位于该第一金属功函数层以及该凹槽的该些侧壁之间。
10.如权利要求8所述的埋入式栅极通道的金属氧化物半导体场效晶体管，其中该第二金属功函数层的一厚度为50～150埃。
11.如权利要求1所述的埋入式栅极通道的金属氧化物半导体场效晶体管，其中自该基底的表面至该埋入式栅极通道区的一深度为400～900埃。
12.如权利要求8所述的埋入式栅极通道的金属氧化物半导体场效晶体管，其中该第一金属功函数层以及该第二金属功函数层具有不同导电型。
13.如权利要求12所述的埋入式栅极通道的金属氧化物半导体场效晶体管，其中该埋入式栅极通道区以及该第二金属功函数层具有N型，而该第一金属功函数层具有P型。
14.一种制作埋入式栅极通道的金属氧化物半导体场效晶体管的方法，包含：
提供基底；
形成埋入式栅极通道区于该基底中；
形成介电层于该基底上，其中该介电层具有凹槽，且该凹槽位于该埋入式栅极通道区的正上方；
形成第一金属功函数层于该凹槽中，其中该第一金属功函数层具有「一」字型剖面结构，且该第一金属功函数层的各侧壁与该凹槽的最接近的侧壁的一最小距离大于零；以及
形成轻掺杂源极区、轻掺杂漏极区、源极区以及漏极区于该第一金属功函数层侧边的该基底中，
其中该第一金属功函数层位于该轻掺杂源极区以及该轻掺杂漏极区之间，其中该第一金属功函数层垂直重叠该轻掺杂源极区以及该轻掺杂漏极区的部分，但该第一金属功函数层没有垂直重叠该源极区以及该漏极区。
15.如权利要求14所述的制作埋入式栅极通道的金属氧化物半导体场效晶体管的方法，其中该第一金属功函数层完全垂直重叠该埋入式栅极通道区。
16.如权利要求14所述的制作埋入式栅极通道的金属氧化物半导体场效晶体管的方法，还包含：
形成金属功函数层顺应覆盖该凹槽的侧壁、该凹槽的底面，以及该介电层；
图案化该金属功函数层，以移除该金属功函数层覆盖该底面的二端部，以及该金属功函数层覆盖该凹槽的该些侧壁以及该介电层的侧壁部，因而形成该第一金属功函数层，其中该第一金属功函数层具有该「一」字型剖面结构；以及
形成第二金属功函数层顺应覆盖该第一金属功函数层以及该凹槽的该些侧壁。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000353756A (ja) * 1999-06-14 2000-12-19 Toshiba Corp 半導体装置およびその製造方法
JP2001284580A (ja) * 2000-03-29 2001-10-12 Toshiba Corp 半導体装置およびその製造方法
CN102386095A (zh) * 2010-08-31 2012-03-21 中国科学院微电子研究所 半导体结构的制造方法
CN105470200A (zh) * 2014-09-09 2016-04-06 联华电子股份有限公司 具有金属栅极的半导体元件及其制作方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001352057A (ja) 2000-06-09 2001-12-21 Mitsubishi Electric Corp 半導体装置、およびその製造方法
JP3940565B2 (ja) 2001-03-29 2007-07-04 株式会社東芝 半導体装置及びその製造方法
US20080001173A1 (en) 2006-06-23 2008-01-03 International Business Machines Corporation BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH k GATE DIELECTRICS
US9059321B2 (en) 2012-05-14 2015-06-16 International Business Machines Corporation Buried channel field-effect transistors
CN106935646B (zh) * 2015-12-30 2020-10-30 中芯国际集成电路制造(北京)有限公司 埋藏沟道晶体管及其形成方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000353756A (ja) * 1999-06-14 2000-12-19 Toshiba Corp 半導体装置およびその製造方法
JP2001284580A (ja) * 2000-03-29 2001-10-12 Toshiba Corp 半導体装置およびその製造方法
CN102386095A (zh) * 2010-08-31 2012-03-21 中国科学院微电子研究所 半导体结构的制造方法
CN105470200A (zh) * 2014-09-09 2016-04-06 联华电子股份有限公司 具有金属栅极的半导体元件及其制作方法

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