CN113791927A - Watchdog control circuit, electronic device and watchdog control method - Google Patents
Watchdog control circuit, electronic device and watchdog control method Download PDFInfo
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- CN113791927A CN113791927A CN202111106926.5A CN202111106926A CN113791927A CN 113791927 A CN113791927 A CN 113791927A CN 202111106926 A CN202111106926 A CN 202111106926A CN 113791927 A CN113791927 A CN 113791927A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
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Abstract
The embodiment of the invention discloses a watchdog control circuit, electronic equipment and a watchdog control method, wherein the watchdog control circuit comprises a processor, a selection module, a self-locking module, a three-state output control module and a watchdog, and when the processor is powered on or starts to reset, the selection module outputs an unlocking signal to a self-locking module when a reset signal is input; the self-locking module is used for outputting an enable control release signal when an unlocking signal is input; the tri-state output control module is used for being in a high-impedance state when the enable control release signal is input; the watchdog is used for stopping outputting the reset signal when the three-state output control module is in a high impedance state. The unlocking signal is output to the self-locking module through the selection module when the program is burnt, debugged or powered on for starting, the self-locking module outputs the enabling control releasing signal to enable the tri-state output control module to be in the high-resistance state so as to disable the watchdog, manual intervention for disabling the watchdog and program modification are not needed so as to optimize starting efficiency, and the program can be normally started.
Description
Technical Field
The embodiment of the invention relates to the technical field of electronic circuit monitoring, in particular to a watchdog control circuit, electronic equipment and a watchdog control method.
Background
In the use process of the electronic equipment, in order to ensure the safe and reliable operation of the electronic equipment, a hardware watchdog is usually added to monitor the operation process of the electronic equipment, so that the electronic equipment is reset by triggering the watchdog to output a reset signal after an abnormality occurs in the operation process of the electronic equipment.
In practical application, the program in the electronic device is too long in debugging, burning and starting loading time, and the electronic device system cannot work normally due to the monitoring function of the watchdog. On one hand, in order to solve the problem that the watchdog cannot normally work in program debugging and burning, a jumper or a dial switch needs to be added on a reset signal output by the watchdog, when the program is debugged or burned, a reset signal loop is disconnected, the watchdog circuit cannot normally work, and when the program is burned or debugged, the reset signal loop is closed, so that the watchdog circuit normally works; on the other hand, for the overlong program starting and loading time, firstly, the program is optimized to improve the starting efficiency, and secondly, the output state of the GPIO port for feeding the dog is configured to determine the starting or closing of the watchdog function.
In summary, the control of the watchdog in the prior art at the program debugging, burning and starting stages has the following problems:
1) manual intervention is needed to add a jumper or a dial switch;
2) the starting efficiency of the optimization program is complex, and the program needs to be changed;
3) when the output state of the GPIO port for the watchdog is configured, after a program fails or a pin is damaged, the watchdog function has the risk of failure, and the reliability is low.
Disclosure of Invention
The embodiment of the invention aims to: the invention provides a watchdog control circuit, electronic equipment and a watchdog control method, aiming at solving the problems that the control of the existing watchdog in the stages of program debugging, burning and starting needs manual intervention, the efficiency of the program is complicated to optimize and the reliability is low, and in order to solve the problems, the embodiment of the invention adopts the following technical scheme:
in a first aspect, a watchdog control circuit is provided, which comprises a processor, a selection module, a self-locking module, a tri-state output control module and a watchdog, wherein the processor is provided with a dog feeding signal output end and a reset signal input end, the watchdog is provided with a dog feeding signal input end and a reset signal output end, the input end of the selection module is respectively connected with the dog feeding signal output end and the reset signal input end, the output end of the selection module is connected with the input end of the self-locking module, the signal input end of the tri-state output control module is connected with the dog feeding signal output end, the enable input end of the tri-state output control module is connected with the output end of the self-locking module, the output end of the tri-state output control module is connected with the dog feeding signal input end,
the selection module is used for outputting an unlocking signal to the self-locking module when a reset signal is input and outputting a locking signal to the self-locking module when a dog feeding signal is input when the processor is powered on or triggers reset;
the self-locking module is used for outputting an enabling control signal when the locking signal is input and outputting an enabling control releasing signal when the unlocking signal is input;
the tri-state output control module is used for outputting a dog feeding signal input from the dog feeding signal output end when the enable control signal is input, and outputting a high-resistance state signal to stop the watchdog monitoring function when the enable control release signal is input;
the watchdog is used for stopping the watchdog monitoring function when the tri-state output control module outputs a high-resistance state signal, and outputting a reset signal from the reset signal output end when no dog feeding signal is input at the dog feeding signal input end within a preset time length.
Optionally, the selection module is provided with a first input end, a second input end and a first output end, and the first input end and the second input end are respectively connected with the dog feeding signal output end and the reset signal input end;
the self-locking module is provided with a third input end and a second output end, and the third input end is connected with the first output end;
the tri-state output control module is provided with a third output end, the enabling input end is connected with the second output end, the signal input end is connected with the dog feeding signal output end, and the third output end is connected with the dog feeding signal input end.
Optionally, the selection module is configured to output a high-level lock signal from the first output terminal when a high-level dog feeding signal is input to the first input terminal, and output a high-impedance signal from the first output terminal when a low-level dog feeding signal is input to the first input terminal, and,
and when the second input end inputs a high-level reset signal, a high-impedance state signal is output from the first output end.
Optionally, the selection module includes a first diode, a second diode, and a first resistor connected in series in sequence, wherein a cathode of the first diode is connected to the reset signal input terminal, a cathode of the second diode is connected to an anode of the first diode, an anode of the second diode is connected to the dog feeding signal output terminal through the first resistor, the cathode of the first diode serves as the first input terminal, one end of the first resistor connected to the dog feeding signal output terminal serves as the second input terminal, and a common node of the first diode and the second diode serves as the first output terminal.
Optionally, the self-locking module is configured to output an enable control signal from the second output terminal and lock the second output terminal in a locked state of the output enable control signal after the third input terminal receives the lock signal output by the first output terminal, maintain the locked state of the second output terminal after the third input terminal receives the high impedance signal output by the first output terminal, and,
and after the third input end receives the unlocking signal output by the first output end, outputting an enable control release signal from the second output end and releasing the locking state of the second output end.
Optionally, the self-locking module includes a first triode, a second resistor, a third resistor, a fourth resistor, and a fifth resistor;
the emitting electrode of the first triode passes through the second resistor is connected with the power supply, the collecting electrode of the first triode passes through the third resistor ground, the collecting electrode of the second triode passes through the fifth resistor and is connected with the power supply, the emitting electrode of the second triode is grounded, the base electrode of the second triode passes through the fourth resistor and is connected with the collecting electrode of the first triode, the base electrode of the first triode and the collecting electrode of the second triode are connected, the collecting electrode of the first triode and the common node of the third resistor serve as the third input end, and the collecting electrode of the second triode and the common node of the second resistor serve as the second output end.
Optionally, the tri-state output control module includes a tri-state output control chip, the tri-state output control chip is provided with an enable pin, a dog feeding signal input pin and a dog feeding signal output pin, the enable pin serves as the enable input terminal, the dog feeding signal input pin serves as the signal input terminal, and the dog feeding signal output pin serves as the third output terminal.
Optionally, the watchdog comprises a watchdog chip, and the watchdog chip is provided with a dog feeding signal input end and a reset signal output end.
In a second aspect, an electronic device is provided, where the electronic device includes the watchdog control circuit of any one of the first aspects.
In a third aspect, a watchdog control method is provided, which is applied to the electronic device of the second aspect, and includes:
when the processor is powered on or triggers reset, the watchdog is controlled to output a reset signal;
when the reset signal is input into a selection module, controlling the selection module to output an unlocking signal;
when the unlocking signal is input into the self-locking module, controlling the self-locking module to output an enabling control release signal;
when the enable control release signal is input into the tri-state output control module, controlling the tri-state output control module to output a high-impedance state signal to stop the watchdog monitoring function;
and stopping the watchdog monitoring function when the tri-state output control module outputs a high-impedance state signal.
Optionally, the method further comprises:
when the processor is powered on or reset, controlling the processor to output a dog feeding signal and controlling a reset input end of the processor to be at a high level;
when the dog feeding signal is input into the selection module, controlling the selection module to output a locking signal;
when the locking signal is input into the self-locking module, controlling the self-locking module to output an enabling control signal;
when the enable control signal is input into the tri-state output control module, controlling the tri-state output control module to output the received dog feeding signal;
and outputting a dog feeding signal by the three-state output control module, and controlling the watchdog to output a reset signal when the watchdog does not receive the dog feeding signal within a preset time length.
The watchdog control circuit of the embodiment of the invention comprises a processor, a selection module, a self-locking module, a tri-state output control module and a watchdog, and realizes that when the watchdog function needs to be forbidden during program burning, debugging or power-on starting, the watchdog outputs a reset signal, then outputs an unlocking signal to a self-locking module through the selection module, outputs an enable control release signal from the self-locking module to enable the tri-state output control module to be in a high-impedance state so as to forbid the watchdog function, the watchdog stops outputting the reset signal, the processor does not receive the reset signal of the watchdog during program burning, debugging and starting, after the processor outputs a dog feeding signal after program burning, debugging or power-on starting, the selection module outputs a locking signal to the self-locking module, the self-locking module outputs an enable control signal to the tri-state output control module, and the tri-state output control module outputs the dog feeding signal to the watchdog, the watchdog works normally after the program is started. On one hand, the watchdog function is forbidden without manual intervention during program burning and debugging, so that the program burning and debugging efficiency is improved, on the other hand, the program is not required to be changed to optimize the starting efficiency and configure the watchdog signal output port to forbid and enable the watchdog, so that the normal starting of the program is ensured, and the reliability of the watchdog control circuit is improved.
Drawings
The invention is explained in more detail below with reference to the figures and examples.
Fig. 1 is a circuit block diagram of a watchdog control circuit according to an embodiment of the present invention.
Fig. 2 is a schematic circuit diagram of a watchdog control circuit according to an embodiment of the present invention.
Fig. 3 is a flowchart of a watchdog control method according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems solved, technical solutions adopted and technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, unless expressly stated or limited otherwise, the terms "connected," "connected," and "fixed" are to be construed broadly, e.g., as meaning permanently connected, removably connected, or integral to one another; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Fig. 1 is a circuit block diagram of a watchdog control circuit according to an embodiment of the present invention, and as shown in fig. 1, the watchdog control circuit according to the embodiment of the present invention includes a processor 10, a selection module 20, a self-locking module 30, a tri-state output control module 40, and a watchdog 50.
The processor 10 may be an integrated circuit with data processing capability running one or more application programs, the processor 10 is provided with a dog feeding signal output terminal WDI _ out and a reset signal input terminal reset _ in, the dog feeding signal output terminal WDI _ out is used for outputting a dog feeding signal to feed the watchdog 50, and the dog feeding signal output by the dog feeding signal output terminal WDI _ out may be a high-level signal. The watchdog 50 may be a hardware watchdog, the watchdog 50 is provided with a feeding dog signal input terminal WDI _ in and a reset signal output terminal reset _ out, and the reset signal output by the reset signal output terminal reset _ out may be a low level signal.
As shown in fig. 1, in the embodiment of the present invention, the input end of the selection module 20 is connected to the dog feeding signal output end WDI _ out and the reset signal input end reset _ in, the output end of the selection module 20 is connected to the input end of the self-mode locking module 30, the input end of the tri-state output control module 40 is connected to the output end of the self-mode locking module 30 and the dog feeding signal output end WDI _ out, and the output end of the tri-state output control module 40 is connected to the dog feeding signal input end WDI _ in.
Specifically, as shown In fig. 1, the selection module 20 is provided with a first input terminal In _1, a second input terminal In _2, and a first output terminal Out _1, the first input terminal In _1 and the second input terminal In _2 are respectively connected to a dog feeding signal output terminal WDI _ Out and a reset signal input terminal reset _ In, the self-locking module 30 is provided with a third input terminal In _3 and a second output terminal Out _2, the third input terminal In _3 is connected to the first output terminal Out _1, the tri-state output control module 40 is provided with an enable input terminal In _4, a signal input terminal In _5, and a third output terminal Out _3, the enable input terminal In _4 is connected to the second output terminal Out _2, the signal input terminal In _5 is connected to the dog feeding signal output terminal WDI _ Out, and the third output terminal Out _3 is connected to the dog feeding signal input terminal WDI _ In.
Wherein the selection module 20 is configured to output an unlock signal to the self-locking module 30 when a reset signal is input (the watchdog 50 outputs a reset signal when being powered on due to the characteristic of the watchdog 50) and output a lock signal to the self-locking module 30 when a dog-feeding signal is input, the self-locking module 30 is configured to output an enable control signal when the lock signal is input and output an enable control release signal when the unlock signal is input, the tri-state output control module 40 is configured to output a dog-feeding signal input from the dog-feeding signal output terminal WDI _ out when the enable control signal is input and output a high-resistance state signal to stop the watchdog monitoring function when the enable control release signal is input, the watchdog 50 is configured to stop the watchdog monitoring function when the high-resistance state signal is output by the tri-state output control module 40 and no dog-feeding signal is input at the dog signal input terminal WDI _ in for a preset time period when the processor 10 is powered on or triggers a reset, a reset signal is output from the reset signal output terminal reset _ out.
In order to make the principle of the watchdog control circuit according to the embodiment of the present invention more clearly understood by those skilled in the art, the operation principle of the watchdog control circuit is described below with reference to the circuit schematic diagrams of fig. 1 and fig. 2.
As shown In fig. 1, In the embodiment of the present invention, the selection module 20 is configured to output a high-level locking signal from the first output terminal Out _1 when a high-level dog feeding signal is input to the first input terminal In _1, output a high-resistance signal from the first output terminal Out _1 when a low-level dog feeding signal is input to the first input terminal In _1, input a low-level reset signal to the second input terminal In _2, output a low-level unlocking signal from the first output terminal Out _1, and output a high-resistance signal from the first output terminal Out _1 when a high-level reset signal is input to the second input terminal In _ 2.
As shown in fig. 2, in an implementable example, the selection module 20 includes a first diode VD1, a second diode VD2, and a first resistor R1 connected in series in sequence, wherein a cathode of the first diode VD1 is connected to the reset signal input terminal reset _ in, a cathode of the second diode VD2 is connected to an anode of the first diode VD1, an anode of the second diode VD2 is connected to the dog feeding signal output terminal WDI _ out through a first resistor R1, a cathode of the first diode VD1 serves as a first input terminal of the selection module 20, an end of the first resistor R1 connected to the dog feeding signal output terminal WDI _ out serves as a second input terminal of the selection module 20, and a common node of the first diode VD1 and the second diode VD2 serves as a first output terminal of the selection module 20.
The operating principle of the selection module 20 shown in fig. 1 and 2 is: when the system is powered on or reset and reinitialized, due to the characteristics of the watchdog 50, the reset signal output terminal reset _ out of the watchdog 50 outputs a low-level reset signal of 140-280 ms, the processor 10 is initialized to complete the reset operation, and the dog feeding signal output terminal WDI _ out of the processor 10 has no signal output in the initialization process of the processor 10. When the reset signal output terminal reset _ out of the watchdog 50 outputs a low-level reset signal, the first diode VD1 is in a forward conducting state, and whether the dog feeding signal output terminal WDI _ out outputs a high-level dog feeding signal or not, the anode of the first diode VD1 is clamped to a low level of the voltage drop of the first diode VD1 by the first diode VD1, so that the common node of the first diode VD1 and the second diode VD2, which is the first output terminal of the selection module 20, outputs a low-level unlock signal to the self-locking module 30. When the initialization of the processor 10 is completed, the reset signal input terminal reset _ in of the processor 10 is at a high level, the first diode VD1 is turned off in the reverse direction and does not respond to a high level reset signal, and at the same time, the feed dog signal output terminal WDI _ Out of the processor 10 outputs a high level feed dog signal, and the second diode VD2 is turned on in the forward direction, so that the common node of the first diode VD1 and the second diode VD2, which are the first output terminal Out _1 of the selection block 20, outputs a high level lock signal to the self-locking block 30, and when the feed dog signal output terminal WDI _ Out of the processor 10 is at a low level, the second diode VD2 is turned off in the reverse direction and the common node of the first diode VD1 and the second diode VD2, which are the first output terminal Out _1 of the selection block 20, outputs a high level lock signal, that is not responding to a low level feed dog signal, thereby realizing that the selection block 20 outputs a low level unlock signal to the self-locking block 30 when inputting a low level reset signal, the high level of the up-lock signal is output to the self-locking module 30 when the high level of the dog feeding signal is input.
As shown In fig. 1, In the embodiment of the present invention, the self-locking module 30 is configured to output an enable control signal from the second output terminal Out _2 and lock the second output terminal Out _2 In a locked state of the output enable control signal after receiving a lock signal output from the first output terminal Out _1 at the third input terminal In _3, maintain the locked state of the second output terminal Out _2 after receiving a high-impedance signal output from the first output terminal Out _1 at the third input terminal In _3, and output an enable control release signal from the second output terminal Out _2 and release the locked state of the second output terminal Out _2 after receiving an unlock signal output from the first output terminal Out _1 at the third input terminal In _ 3.
As shown in fig. 2, in an example, the self-locking module 30 includes a first transistor VT1, a second transistor VT2, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5, an emitter of the first transistor VT1 is connected to the power VCC through a second resistor R2, a collector of the first transistor VT1 is connected to the ground through a third resistor R3, a collector of the second transistor VT2 is connected to the power VCC through a fifth resistor R5, an emitter of the second transistor VT2 is connected to the ground, a base of the second transistor VT2 is connected to a collector of the first transistor VT1 through a fourth resistor R4, a base of the first transistor VT1 is connected to a collector of the second transistor VT2, a common node of the collector of the first transistor 1 and the third resistor R3 is a third input terminal of the self-locking module 30, a common node of the collector of the second transistor VT2 and the second resistor VT R2 is a second output terminal 30, the first transistor VT1 is a PNP transistor, and the second transistor VT2 is an NPN transistor.
The working principle of the self-locking module 30 shown in fig. 1 and 2 is: the first transistor VT1 in the self-locking module 30 is a PNP transistor, the second transistor VT2 is an NPN transistor, when receiving the high-level locking signal output by the selection module 20, the second transistor VT2 is turned on, the collector of the second transistor VT2 is pulled low, that is, the enable pin OE of the tri-state output control chip U1 is low, at this time, since the base of the first transistor VT1 is connected to the collector of the second transistor VT2, the first transistor VT1 is turned on, after the first transistor VT1 is turned on, the node where the first transistor VT1 is connected to the third resistor R3 and the fourth resistor R4 is pulled high, so that the second transistor VT2 is maintained in a conducting state, and when the selection module 20 outputs the high-level locking signal, the first transistor VT1 and the second transistor VT2 in the self-locking module 30 are maintained in a conducting and locked state, thereby achieving the self-locking function, namely, the locking state of the locking signal of which the second output terminal Out _2 outputs a high level is maintained. After receiving the low-level unlocking signal output by the selection module 20, the second transistor VT2 is turned off because the low-level unlocking signal is output to the first transistor VT1, the third resistor R3 and the public node of the fourth resistor R4, and the collector of the second transistor VT2 is pulled up to the power VCC through the fifth resistor R5, that is, the collector of the second transistor VT2 is at a high level, and the enable pin OE of the tri-state output control chip connected to the collector of the second transistor VT2 becomes a high level, at this time, the base of the first transistor VT1 becomes high in level, the first transistor VT1 is turned off, and the whole self-locking module 30 is unlocked.
The tri-state output control module 40 comprises a tri-state output control chip U1, the tri-state output control chip U1 is provided with an enable pin OE, a dog feeding signal input pin a and a dog feeding signal output pin Y, the enable pin OE is an enable input terminal In _4 of the tri-state output control module 40, the dog feeding signal input pin a is a signal input terminal In _5 of the tri-state output control module 40, and the dog feeding signal output pin Y is a third output terminal of the tri-state output control module 40.
The watchdog 50 includes a watchdog chip U2, and the watchdog chip U2 is provided with a feed dog signal input terminal WDI _ in and a reset signal output terminal reset _ out.
The working principle of the tri-state output control module 40 is: the enable pin OE is an enable end of the tri-state output control chip U1, the enable pin OE is active when a low level signal, even when the enable pin OE is low, the dog feeding signal output pin Y of the tri-state output control chip U1 directly outputs a dog feeding signal input by the dog feeding signal input pin a to realize the feeding of the watchdog 50, when the enable pin OE is high, the dog feeding signal output pin Y of the tri-state output control chip U1 outputs a high resistance signal, i.e., no output state, the monitoring function of the watchdog 50 is disabled, thereby realizing the disabling, enabling or feeding of the watchdog 50 function by controlling the level of the enable pin OE of the tri-state output control chip U1 to control the output state of the dog feeding signal output pin Y.
When the watchdog 50 is powered on, a low-level reset signal of 140-280 ms is output, the function of the watchdog 50 can be enabled or disabled through the state of the feeding dog signal input terminal WDI _ in, that is, when the feeding dog signal input terminal WDI _ in is in a high-resistance state, the function of the watchdog 50 is disabled, when the feeding dog signal input terminal WDI _ in is in a high-level state, the function of the watchdog 50 is enabled, when the watchdog 50 is normally in a monitoring state, the feeding dog signal needs to be received from the feeding dog signal input terminal WDI _ in within a predetermined time, and when the feeding dog signal is not received for a time exceeding a predetermined time, the watchdog 50 outputs a reset signal from the reset signal output terminal reset _ out to reset the processor 10.
The watchdog control circuit of the embodiment of the invention comprises a processor, a selection module, a self-locking module, a tri-state output control module and a watchdog, and realizes that when the watchdog function needs to be forbidden during program burning, debugging or power-on starting, the watchdog outputs a reset signal, then outputs an unlocking signal to a self-locking module through the selection module, outputs an enable control release signal from the self-locking module to enable the tri-state output control module to be in a high-impedance state so as to forbid the watchdog function, the watchdog stops outputting the reset signal, the processor does not receive the reset signal of the watchdog during program burning, debugging and starting, after the processor outputs a dog feeding signal after program burning, debugging or power-on starting, the selection module outputs a locking signal to the self-locking module, the self-locking module outputs an enable control signal to the tri-state output control module, and the tri-state output control module outputs the dog feeding signal to the watchdog, the watchdog works normally after the program is started. On one hand, the watchdog function is forbidden without manual intervention during program burning and debugging, so that the program burning and debugging efficiency is improved, on the other hand, the program is not required to be changed to optimize the starting efficiency and configure the watchdog signal output port to forbid and enable the watchdog, so that the normal starting of the program is ensured, and the reliability of the watchdog control circuit is improved.
The embodiment of the invention also provides electronic equipment, which comprises the watchdog control circuit in the embodiment of the invention, wherein the electronic equipment can be electronic equipment in an elevator system, such as a main control board, a motor control board, a control board for detecting the door closing in place and the like of an elevator in the elevator equipment.
Fig. 3 is a flowchart of a watchdog control method according to an embodiment of the present invention. The watchdog control method shown in fig. 3 may be applied to an electronic device provided in an embodiment of the present invention, where a watchdog control circuit in the electronic device includes a processor, a selection module, an auto-lock module, a tri-state output control module, and a watchdog, and the watchdog control method may include the following steps:
s301, when the processor is powered on or triggers reset, the watchdog is controlled to output a reset signal.
As shown in fig. 1, when a program is burned and debugged, or a system is powered on or reset, a watchdog monitoring function of the watchdog needs to be disabled, and the watchdog may be controlled to output a low-level reset signal of 140-280 ms, that is, the watchdog generally outputs the low-level reset signal when powered on.
And S302, when the reset signal is input into the selection module, controlling the selection module to output an unlocking signal.
As shown in fig. 1, one input terminal of the selection module 20 is connected to the reset signal input terminal reset _ in of the processor 10, so that the reset signal is input into the selection module 20, so that the selection module outputs a low-level unlocking signal to the self-locking module 30, and specifically, the low-level unlocking signal to the self-locking module 30 can be realized by the circuit principle of the selection module 20, and the detailed details are shown in the circuit principle diagram of the selection module 20 shown in fig. 2 and the description of the operation principle of the selection module 20 in the embodiment of the watchdog control circuit described above, and will not be further described herein.
And S303, controlling the self-locking module to output an enabling control release signal when the unlocking signal is input into the self-locking module.
As shown in the schematic circuit diagram of the self-mode-locking block 30 in fig. 2, when the unlocking signal of low level is input to the self-mode-locking block, the enable control release signal is output from the self-mode-locking block 30 to the enable pin OE of the tri-state output control block 40, and the detailed principle refers to the description of the operation principle of the selection block 20 in the above embodiment of the watchdog control circuit, and will not be described in detail here.
S304, when the enable control release signal is input into the tri-state output control module, controlling the tri-state output control module to output a high-impedance state signal to stop the watchdog monitoring function.
Referring to the schematic circuit diagram of the tri-state output control module 40 shown in fig. 2, when the enable control release signal is input to the enable pin OE of the tri-state output control module 40, the tri-state output control module 40 outputs a high-impedance signal, and the detailed principle refers to the description of the working principle of the tri-state output control module 40 in the above embodiment of the watchdog control circuit, and will not be described in detail here.
S305, stopping the watchdog monitoring function when the tri-state output control module outputs a high-impedance state signal.
As shown in fig. 2, since the tri-state output control module 40 is in a high impedance state, the tri-state output control module 40 outputs a high impedance state signal, the dog feeding signal input terminal WDI _ in of the watchdog 50 has no input, and the watchdog function is disabled, the watchdog function is disabled when the processor is started by burning, debugging and power-on reset, so that the processor can be normally started.
After the processor is normally started, the watchdog control method of the embodiment of the invention further comprises the following steps: when the processor is powered on or reset is finished, the control processor outputs a dog feeding signal and controls the reset input end of the processor to be at a high level, when the dog feeding signal is input into the selection module, the selection module is controlled to output a locking signal, when the locking signal is input into the self-locking module, the self-locking module is controlled to output an enabling control signal, when the enabling control signal is input into the tri-state output control module, the tri-state output control module is controlled to output the received dog feeding signal, and when the tri-state output control module outputs the dog feeding signal, the watchdog is controlled to output a reset signal when the watchdog does not receive the dog feeding signal within a preset time length, so that the watchdog function is started to be started to monitor the processor after the processor starts to output the dog feeding signal.
The watchdog control circuit comprises a processor, a selection module, a self-locking module, a tri-state output control module and a watchdog, and realizes that when the watchdog function needs to be forbidden during program burning, debugging or power-on starting, the watchdog outputs an unlocking signal to the self-locking module through the selection module after outputting a reset signal, the self-locking module outputs an enable control release signal to enable the tri-state output control module to be in a high-resistance state to forbid the watchdog function, the watchdog stops outputting the reset signal, the processor does not receive the reset signal of the watchdog during program burning, debugging and starting, and after the processor outputs a feed dog signal after program burning, debugging or power-on starting, the selection module outputs a locking signal to the self-locking module, the self-locking module outputs an enable control signal to the tri-state output control module, the tri-state output control module outputs a dog feeding signal to the watchdog, and the watchdog works normally after the program is started. On one hand, the watchdog function is forbidden without manual intervention during program burning and debugging, so that the program burning and debugging efficiency is improved, and on the other hand, the program does not need to be changed to optimize the starting efficiency, so that the program can be normally started.
In the description herein, the terms "first" and "second" are used merely for descriptive purposes and are not intended to have any special meaning.
In the description herein, references to the description of "an embodiment," "an example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single technical solution, and such description is for clarity only, and those skilled in the art should take the description as a whole, and the technical solutions in the embodiments may be appropriately combined to form other embodiments that may be understood by those skilled in the art.
The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive effort, which would fall within the scope of the present invention.
Claims (11)
1. A watchdog control circuit is characterized by comprising a processor, a selection module, a self-locking module, a tri-state output control module and a watchdog, wherein the processor is provided with a dog feeding signal output end and a reset signal input end, the watchdog is provided with a dog feeding signal input end and a reset signal output end, the input end of the selection module is respectively connected with the dog feeding signal output end and the reset signal input end, the output end of the selection module is connected with the input end of the self-locking module, the signal input end of the tri-state output control module is connected with the dog feeding signal output end, the enable input end of the tri-state output control module is connected with the output end of the self-locking module, and the output end of the tri-state output control module is connected with the dog feeding signal input end,
the selection module is used for outputting an unlocking signal to the self-locking module when a reset signal is input and outputting a locking signal to the self-locking module when a dog feeding signal is input when the processor is powered on or triggers reset;
the self-locking module is used for outputting an enabling control signal when the locking signal is input and outputting an enabling control releasing signal when the unlocking signal is input;
the tri-state output control module is used for outputting a dog feeding signal input from the dog feeding signal output end when the enable control signal is input, and outputting a high-resistance state signal to stop the watchdog monitoring function when the enable control release signal is input;
the watchdog is used for stopping the watchdog monitoring function when the tri-state output control module outputs a high-resistance state signal, and outputting a reset signal from the reset signal output end when no dog feeding signal is input at the dog feeding signal input end within a preset time length.
2. The watchdog control circuit of claim 1,
the selection module is provided with a first input end, a second input end and a first output end, and the first input end and the second input end are respectively connected with the dog feeding signal output end and the reset signal input end;
the self-locking module is provided with a third input end and a second output end, and the third input end is connected with the first output end;
the tri-state output control module is also provided with a third output end, the enabling input end is connected with the second output end, the signal input end is connected with the dog feeding signal output end, and the third output end is connected with the dog feeding signal input end.
3. The watchdog control circuit of claim 2, wherein the selection module is configured to output a high level lock signal from the first output terminal when a high level dog feeding signal is input to the first input terminal, output a high impedance signal from the first output terminal when a low level dog feeding signal is input to the first input terminal, and,
and when the second input end inputs a high-level reset signal, a high-impedance state signal is output from the first output end.
4. The watchdog control circuit according to claim 2 or 3, wherein the selection module includes a first diode, a second diode, and a first resistor connected in series, wherein a cathode of the first diode is connected to the reset signal input terminal, a cathode of the second diode is connected to an anode of the first diode, an anode of the second diode is connected to the watchdog signal output terminal through the first resistor, a cathode of the first diode serves as the first input terminal, an end of the first resistor connected to the watchdog signal output terminal serves as the second input terminal, and a common node of the first diode and the second diode serves as the first output terminal.
5. The watchdog control circuit of claim 2, wherein the self-locking module is configured to output an enable control signal from the second output terminal and lock the second output terminal in a locked state of the output enable control signal after the third input terminal receives the lock signal output by the first output terminal, maintain the locked state of the second output terminal after the third input terminal receives the high impedance signal output by the first output terminal, and,
and after the third input end receives the unlocking signal output by the first output end, outputting an enable control release signal from the second output end and releasing the locking state of the second output end.
6. The watchdog control circuit of claim 2 or 5, wherein the self-locking module comprises a first transistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor;
the emitting electrode of the first triode passes through the second resistor is connected with the power supply, the collecting electrode of the first triode passes through the third resistor ground, the collecting electrode of the second triode passes through the fifth resistor and is connected with the power supply, the emitting electrode of the second triode is grounded, the base electrode of the second triode passes through the fourth resistor and is connected with the collecting electrode of the first triode, the base electrode of the first triode and the collecting electrode of the second triode are connected, the collecting electrode of the first triode and the common node of the third resistor serve as the third input end, and the collecting electrode of the second triode and the common node of the second resistor serve as the second output end.
7. The watchdog control circuit of claim 2, wherein the tri-state output control module comprises a tri-state output control chip provided with an enable pin as the enable input, a dog feeding signal input pin as the signal input, and a dog feeding signal output pin as the third output.
8. The watchdog control circuit of claim 2, wherein the watchdog comprises a watchdog chip provided with a feed dog signal input and a reset signal output.
9. An electronic device, characterized in that the electronic device comprises a watchdog control circuit according to any one of claims 1 to 8.
10. A watchdog control method applied to the electronic device of claim 9, comprising:
when the processor is powered on or triggers reset, the watchdog is controlled to output a reset signal;
when the reset signal is input into a selection module, controlling the selection module to output an unlocking signal;
when the unlocking signal is input into the self-locking module, controlling the self-locking module to output an enabling control release signal;
when the enable control release signal is input into the tri-state output control module, controlling the tri-state output control module to output a high-impedance state signal to stop the watchdog monitoring function;
and stopping the watchdog monitoring function when the tri-state output control module outputs a high-impedance state signal.
11. The watchdog control method of claim 10, further comprising:
when the processor is powered on or reset, controlling the processor to output a dog feeding signal and controlling a reset input end of the processor to be at a high level;
when the dog feeding signal is input into the selection module, controlling the selection module to output a locking signal;
when the locking signal is input into the self-locking module, controlling the self-locking module to output an enabling control signal;
when the enable control signal is input into the tri-state output control module, controlling the tri-state output control module to output the received dog feeding signal;
and outputting a dog feeding signal by the three-state output control module, and controlling the watchdog to output a reset signal when the watchdog does not receive the dog feeding signal within a preset time length.
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