CN211180610U - Fault information latch circuit - Google Patents
Fault information latch circuit Download PDFInfo
- Publication number
- CN211180610U CN211180610U CN202020097984.0U CN202020097984U CN211180610U CN 211180610 U CN211180610 U CN 211180610U CN 202020097984 U CN202020097984 U CN 202020097984U CN 211180610 U CN211180610 U CN 211180610U
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- triode
- resistor
- diode
- resistance
- fault information
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Abstract
The programmable logic device or the complex logic gate circuit is used for latching transient fault signals, and the cost is high. To this not enough, provide the utility model who is named as a fault information latch circuit, belong to electron technical field. The utility model discloses a circuit includes triode Q1 and Q2, resistance R1 ~ R4, diode D1 and electric capacity C1, triode Q1's projecting pole ground connection, the base connects triode Q2's collecting electrode, resistance R2's one end, resistance R3's one end and electric capacity C1's one end, another termination input voltage Vin of resistance R2, resistance R3 and electric capacity C1's the other end all ground connection; the base of the triode Q2 is connected with the collector of the triode Q1, one end of the resistor R4 and the output voltage Verror, the emitter is connected with the anode of the diode D1 and one end of the resistor R1, the cathode of the diode D1 is connected with the reset voltage Vreset, and the other ends of the resistor R1 and the resistor R4 are both connected with + 5V. Utility model's circuit is succinct, and the reliability is high, and is with low costs.
Description
Technical Field
The utility model relates to a fault information latch circuit belongs to electron technical field.
Background
In some automatic control systems, a single chip microcomputer needs to monitor multiple paths of external fault signals, and when an external interrupt port of the single chip microcomputer is not enough, part of external fault information can only be accessed to a common I/O port of the single chip microcomputer. Because the external fault signal is a transient signal in a short time and is monitored by a common I/O port of the singlechip, the level of the common I/O port can be read only by adopting a program scanning mode, and the external fault signal can be leaked. The common method for solving the problem is to latch transient fault signals by using a programmable logic device or to realize the transient fault signals by using a complex logic gate circuit, so that the circuit is complex and the cost is high.
SUMMERY OF THE UTILITY MODEL
In order to solve the problem, the utility model provides a fault information latch circuit, the circuit comprises triode, resistance, diode and electric capacity, and the circuit is succinct, and the reliability is high, and with low costs.
The utility model discloses the concrete technical scheme who takes as follows:
a fault information latch circuit comprises triodes Q1 and Q2, resistors R1-R4, a diode D1 and a capacitor C1, wherein an emitter of a triode Q1 is grounded, a base is connected with a collector of the triode Q2, one end of the resistor R2, one end of a resistor R3 and one end of the capacitor C1, the other end of the resistor R2 is connected with an input voltage Vin, and the other ends of the resistor R3 and the capacitor C1 are grounded; the base electrode of the triode Q2 is connected with the collector electrode of the triode Q1, one end of the resistor R4 and the output voltage Verror, the emitter electrode is connected with the anode of the diode D1 and one end of the resistor R1, the cathode of the diode D1 is connected with the reset voltage Vreset, and the other ends of the resistor R1 and the resistor R4 are both connected with + 5V; the triode Q1 is a low-power NPN tube, and the triode Q2 is a low-power PNP tube.
The utility model has the advantages that: the fault information latch circuit is composed of discrete elements, and is simple, high in reliability and low in cost.
Drawings
Fig. 1 is a circuit diagram of the present invention.
Detailed Description
The present invention will be further explained with reference to the accompanying drawings.
As shown in fig. 1, a fault information latch circuit includes transistors Q1 and Q2, resistors R1 to R4, a diode D1 and a capacitor C1, wherein an emitter of a transistor Q1 is grounded, a base is connected to a collector of the transistor Q2, one end of the resistor R2, one end of a resistor R3 and one end of the capacitor C1, the other end of the resistor R2 is connected to an input voltage Vin, and the other ends of the resistor R3 and the capacitor C1 are both grounded; the base electrode of the triode Q2 is connected with the collector electrode of the triode Q1, one end of the resistor R4 and the output voltage Verror, the emitter electrode is connected with the anode of the diode D1 and one end of the resistor R1, the cathode of the diode D1 is connected with the reset voltage Vreset, and the other ends of the resistor R1 and the resistor R4 are both connected with + 5V; the triode Q1 is a low-power NPN tube, and the triode Q2 is a low-power PNP tube.
The Vin signal is a voltage signal transmitted by the monitored object, and is a low level when the monitored object is normal, and is a transient high level when the monitored object has a fault; the Verror signal is sent to a common I/O port of the singlechip, and is at a high level when the monitored object is normal, and is at a low level when the monitored object has a fault; the Vreset signal is a reset signal sent by the unit machine, is high level at ordinary times, and when the latch circuit needs to be reset, the singlechip sends a low level of 100 milliseconds, so that the reset can be completed.
When the fault information latch circuit is just powered on, if the monitored object is normal, the Vin signal is at a low level, the base electrode of the triode Q1 cannot obtain trigger voltage, the triode Q1 is cut off, the triode Q2 is also cut off, and the Verror signal sent to the single chip microcomputer is at a high level, which indicates that the monitored object is normal.
When the monitored object has a fault, the Vin signal sent by the monitored object is in a transient high level, the base electrode of the triode Q1 is triggered, the triode Q1 is enabled to be conducted, the collector voltage of the triode Q2 begins to drop, the conduction of the triode Q2 is triggered, the collector current of the triode Q2 is injected into the base electrode of the triode Q1, the conduction of the triode Q1 is triggered to be stronger, so that strong positive feedback is formed, the triode Q1 and the triode Q2 are enabled to be rapidly conducted in a saturated mode, even if the Vin signal is restored to be in a low level, the triode Q1 and the triode Q2 are still kept in the saturated mode, the Verror signal is output to be in a low level, and fault.
When the single chip microcomputer finishes reading the fault information, the single chip microcomputer provides a reset signal, the Vreset signal is inverted to be a low level of 100 milliseconds, the diode D1 is conducted, the voltage of the emitting electrode of the triode Q2 is pulled down to about 0.7V, the triode Q2 is cut off, the triode Q1 is cut off, the Verror signal restores to a high level, the fault information latch circuit finishes resetting, and the next fault information is waited to arrive.
Claims (1)
1. A fault information latch circuit is characterized in that: the circuit comprises triodes Q1 and Q2, resistors R1-R4, a diode D1 and a capacitor C1, wherein an emitter of the triode Q1 is grounded, a base of the triode Q3583 is connected with a collector of the triode Q2, one end of the resistor R2, one end of the resistor R3 and one end of the capacitor C1, the other end of the resistor R2 is connected with an input voltage Vin, and the other ends of the resistor R3 and the capacitor C1 are grounded; the base electrode of the triode Q2 is connected with the collector electrode of the triode Q1, one end of the resistor R4 and the output voltage Verror, the emitter electrode is connected with the anode of the diode D1 and one end of the resistor R1, the cathode of the diode D1 is connected with the reset voltage Vreset, and the other ends of the resistor R1 and the resistor R4 are both connected with + 5V; the triode Q1 is a low-power NPN tube, and the triode Q2 is a low-power PNP tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020097984.0U CN211180610U (en) | 2020-01-16 | 2020-01-16 | Fault information latch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020097984.0U CN211180610U (en) | 2020-01-16 | 2020-01-16 | Fault information latch circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211180610U true CN211180610U (en) | 2020-08-04 |
Family
ID=71798673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020097984.0U Expired - Fee Related CN211180610U (en) | 2020-01-16 | 2020-01-16 | Fault information latch circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211180610U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112636726A (en) * | 2020-12-22 | 2021-04-09 | 中国电子科技集团公司第十八研究所 | Latch reset circuit for spaceflight |
-
2020
- 2020-01-16 CN CN202020097984.0U patent/CN211180610U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112636726A (en) * | 2020-12-22 | 2021-04-09 | 中国电子科技集团公司第十八研究所 | Latch reset circuit for spaceflight |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20200804 Termination date: 20210116 |