CN113093594B - Interlocking circuit realized by using output characteristic of IO port of single chip microcomputer - Google Patents
Interlocking circuit realized by using output characteristic of IO port of single chip microcomputer Download PDFInfo
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- CN113093594B CN113093594B CN202110311706.XA CN202110311706A CN113093594B CN 113093594 B CN113093594 B CN 113093594B CN 202110311706 A CN202110311706 A CN 202110311706A CN 113093594 B CN113093594 B CN 113093594B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
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Abstract
The invention discloses an interlocking circuit realized by utilizing the output characteristic of an IO port of a singlechip, which comprises a main control MCU and a simulation PWM chip, wherein the main control MCU is connected with a first resistor R1 through an IO1 pin, one end of the first resistor R1 is connected with an MOS (metal oxide semiconductor) tube, an IO2 pin of the main control MCU is connected with a second resistor R2, and one ends of the first resistor R1 and the second resistor R2 are respectively connected with the grid electrode of the MOS tube; the drain electrode of the MOS tube is connected with a third resistor R3, one end of the third resistor R3 is connected with a positive 5V power supply, the positive 5V power supply supplies power to the main control MCU, the drain electrode of the MOS tube is connected with a fourth resistor R4, and one end of the fourth resistor R4 is connected with a 4 th pin of the analog PWM chip; by reducing the output voltage conducted by the interlocking circuit, the output voltage is less than 0.05v, and the circuit generates a stable PWM control signal by reducing the voltage drop, so that the analog PWM circuit can achieve the maximum duty ratio output in the normal working state, and the expandability of the application occasion of the interlocking circuit is improved.
Description
Technical Field
The invention relates to the field of interlocking circuits, in particular to an interlocking circuit realized by utilizing the output characteristic of an IO port of a single chip microcomputer.
Background
The interlock circuit is used for controlling the coil loop of the other coil loop by using an auxiliary contact of one loop among a plurality of loops to carry out state keeping or function limitation.
The general subject of interlock circuitry is often control of other circuits. In circuit control, when a second output high level signal is applied, a first output low level signal and a control circuit work output effective state change; when the output states of the two applied signals are the same, the state of the circuit control output is in an invalid state no matter the two signals are in a low level or high level state, so that the control circuit realizes the interlocking function.
The existing circuit respectively controls two triodes through two IO of an MCU, wherein one triode is PNP type and the other triode is NPN type, although the output of the power-on locking analog PWM circuit is realized, because the two triodes are conducted simultaneously, about 0.7v of conduction voltage drop can be generated on the PNP tube, the limit value of the maximum duty ratio of the analog PWM circuit is limited, and the application occasion of the interlocking circuit is further limited.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides the interlocking circuit realized by utilizing the output characteristic of the IO port of the single chip microcomputer, the output voltage of the pull-down low level conducted by the interlocking circuit is reduced, the output voltage is less than 0.05v, the circuit generates a stable PWM control signal by reducing the voltage drop, further, the analog PWM circuit can achieve the maximum duty ratio output under the normal working state, and the expandability of the application occasion of the interlocking circuit is improved.
In order to solve the technical problems, the invention provides the following technical scheme: an interlocking circuit realized by using the output characteristic of an IO port of a singlechip comprises a master control MCU and a simulation PWM chip, wherein the master control MCU is connected with a first resistor R1 through an IO1 pin, one end of the first resistor R1 is connected with an MOS (metal oxide semiconductor) transistor, an IO2 pin of the master control MCU is connected with a second resistor R2, and one ends of the first resistor R1 and the second resistor R2 are respectively connected with a grid electrode of the MOS transistor;
the drain electrode of the MOS tube is connected with a third resistor R3, one end of the third resistor R3 is connected with a positive 5V power supply, the positive 5V power supply supplies power to the main control MCU, the drain electrode of the MOS tube is connected with a fourth resistor R4, and one end of the fourth resistor R4 is connected with a 4 th pin of the analog PWM chip;
the 8 th pin of simulation PWM chip is connected with the VCC power, the 8 th pin of simulation PWM chip is connected with electric capacity C, electric capacity C's other end ground connection, the 9 th pin of simulation PWM chip is connected with the triode, the 10 th pin of simulation PWM chip and the base of triode interconnect, the 10 th pin of simulation PWM chip is connected with the diode, the negative pole of diode and the projecting pole of triode interconnect, the base of triode is connected with fifth resistance R5.
As a preferred technical solution of the present invention, the first resistor R1 is a protection resistor, and is used for slowing down the switching rate of the MOS transistor.
As a preferred technical solution of the present invention, the second resistor R2 is a bleeder resistor, and is used for preventing the MOS transistor from being broken down and providing a bias voltage for the MOS transistor.
As a preferred technical solution of the present invention, the model of the analog PWM chip is WL 0302.
As a preferred technical solution of the present invention, the main control MCU, the first resistor R1 and the second resistor R2 form a path, and the resistances of the first resistor R1 and the second resistor R2 are 1K Ω and 100K Ω, respectively.
As a preferred technical solution of the present invention, the IO2 pin of the main control MCU and the source of the MOS transistor are connected to each other.
As a preferable embodiment of the present invention, the third resistor R3 is a pull-up resistor, and the resistance of the third resistor R3 is 10K Ω.
As a preferred technical solution of the present invention, the 8 th pin of the analog PWM chip is short-circuited with the 11 th pin and the 12 th pin of the analog PWM chip, respectively, and the 13 th pin of the analog PWM chip is grounded.
As a preferred technical solution of the present invention, a collector of the triode is grounded, and an emitter of the triode is provided with a modulation signal output terminal.
As a preferred embodiment of the present invention, the other end of the fifth resistor R5 is grounded, and the resistance of the fifth resistor R5 is 1K Ω.
Compared with the prior art, the invention can achieve the following beneficial effects:
1. according to the invention, the first resistor R1 and the second resistor R2 for protecting the MOS tube are respectively integrated to the grid electrode of the same MOS tube, the output voltage of the pull-down low level conducted by the interlocking circuit can be reduced, the output voltage is less than 0.05v, the circuit generates a stable PWM control signal by reducing the voltage drop, further, the analog PWM circuit can achieve the maximum duty ratio output under the normal working state, and the expandability of the application occasion of the interlocking circuit is improved;
2. according to the invention, the output of the analog PWM circuit is ensured to be in a closed state, and the MOS tube and the triode are prevented from being triggered by mistake in the power-on process, so that the MOS tube and the triode are prevented from being damaged, the service life of a circuit element is prolonged, and the use cost is saved;
3. the analog PWM circuit is controlled and controlled by controlling the output level of I0, when the IO1 pin of the main control MCU outputs high level and the IO2 pin outputs low level, the circuit outputs PWM _ OUT signal, so that the external IGBT power tube works, the external motor is controlled to normally run, the interlocking function of power-on control output is further realized, if the output level of the IO1 pin of the main control MCU and the output level of the IO2 pin are both high level or low level, the PWM output signal is in a closed state, and the effective control of the output signal of the PWM circuit is realized.
Drawings
Fig. 1 is a circuit diagram of the complete structure of the present invention.
Wherein: 1. a main control MCU; 2. simulating a PWM chip; 3. a first resistor R1; 4. an MOS tube; 5. a second resistor R2; 6. a third resistor R3; 7. a fourth resistor R4; 8. a capacitor C; 9. a triode; 10. a diode; 11. and a fifth resistor R5.
Detailed Description
The present invention will be further described with reference to specific embodiments for the purpose of facilitating an understanding of technical means, characteristics of creation, objectives and functions realized by the present invention, but the following embodiments are only preferred embodiments of the present invention, and are not intended to be exhaustive. Based on the embodiments in the implementation, other embodiments obtained by those skilled in the art without any creative efforts belong to the protection scope of the present invention. The experimental methods in the following examples are conventional methods unless otherwise specified, and materials, reagents and the like used in the following examples are commercially available unless otherwise specified.
Example (b):
as shown in fig. 1, an interlock circuit implemented by using an IO port output characteristic of a single chip microcomputer includes a main control MCU1 and a simulation PWM chip 2, a 8 th pin of the simulation PWM chip 2 is respectively short-circuited with a 11 th pin and a 12 th pin of the simulation PWM chip 2, a 13 th pin of the simulation PWM chip 2 is grounded, the model of the simulation PWM chip 2 is WL0302, the main control MCU1 is connected with a first resistor R13 through an IO1 pin, one end of the first resistor R13 is connected with a MOS transistor 4, an IO2 pin of the main control MCU1 is connected with a source of the MOS transistor 4, the first resistor R13 is a protection resistor for slowing down a switching rate of the MOS transistor 4, an IO2 pin of the main control MCU1 is connected with a second resistor R25, the second resistor R25 is a bleeder resistor for preventing the MOS transistor 4 from being broken down, and simultaneously providing a bias voltage for the MOS transistor 4, one ends of the first resistor R13 and the second resistor R25 are respectively connected with a gate of the main control MCU1, the first resistor R13 and the second resistor R25, the resistance values of the first resistor R13 and the second resistor R25 are 1K omega and 100K omega respectively; the drain of the MOS transistor 4 is connected with a third resistor R36, one end of the third resistor R36 is connected with a positive 5V power supply, the positive 5V power supply supplies power to the main control MCU1, the third resistor R36 is a pull-up resistor, the resistance of the third resistor R36 is 10K Ω, wherein the third resistor R36 is used for reducing the current passing through the third resistor R36, further, the voltage at the two ends of the third resistor R36 is reduced, the drain of the MOS transistor 4 is connected with a fourth resistor R47, and one end of the fourth resistor R47 is connected with the 4 th pin of the analog PWM chip 2; the 8 th pin of simulation PWM chip 2 is connected with the VCC power, the 8 th pin of simulation PWM chip 2 is connected with electric capacity C8, electric capacity C8's other end ground connection, the 9 th pin of simulation PWM chip 2 is connected with triode 9, triode 9's collecting electrode ground connection, triode 9's projecting pole is provided with the modulated signal output end, the 10 th pin of simulation PWM chip 2 and triode 9's base interconnect, the 10 th pin of simulation PWM chip 2 is connected with diode 10, diode 10's negative pole and triode 9's projecting pole interconnect, triode 9's base is connected with fifth resistance R511, fifth resistance R511's other end ground connection, fifth resistance R511's resistance is 1K omega.
The working principle of the invention is as follows: when the power supply device is used, the main control MCU1 is not initialized at the power-on moment, the output levels of the IO1 pin and the IO2 pin are both in a high-resistance state, at the moment, the voltage of each pin of the main control MCU1 is in the same electrical state, and if the output levels of the IO1 pin and the IO2 pin are both in a low-resistance state, the voltage of each pin of the main control MCU1 is also in the same electrical state at the moment, so that a PWM _ EN signal cannot be pulled down, further, the PWM output signal is in a closed state, and further, the effective control on the output signal of a PWM circuit is realized, therefore, when the output levels of the IO1 pin and the IO2 pin are equal, the power supply moment of the external IGBT power tube is in a cut-off state, and the phenomenon that the current passing through the interior of the external IGBT power tube is overlarge due to false triggering can be avoided, so that the external IGBT power tube is prevented from being damaged;
therefore, when the IO1 pin of the main control MCU1 outputs a high level and the IO2 pin outputs a low level, the MOS transistor 4 is turned on, and the current passing through the pull-up resistor is reduced to turn on the MOS transistor 4, so that the actual output voltage of the PWM _ EN signal is less than 0.05V, which allows the PWM duty cycle output by the PWM circuit in the normal enable state to reach the maximum value and allows the effective voltage value output by the circuit to reach the maximum value, thereby improving the scalability of the interlock circuit in use.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and the preferred embodiments of the present invention are described in the above embodiments and the description, and are not intended to limit the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (9)
1. The utility model provides an utilize interlock circuit that singlechip IO mouth output characteristic realized, includes main control MCU (1) and simulation PWM chip (2), its characterized in that: the main control MCU (1) is connected with one end of a first resistor R1(3) through an IO1 pin, an IO2 pin of the main control MCU (1) is connected with one end of a second resistor R2(5), and the other end of the first resistor R1(3) and the other end of the second resistor R2(5) are connected and then connected with a grid electrode of the MOS transistor (4); the source electrode of the MOS tube (4) is connected with an IO2 pin of the master control MCU (1); the drain electrode of the MOS tube (4) is connected with one end of a third resistor R3(6), the other end of the third resistor R3(6) is connected with a positive 5V power supply, the positive 5V power supply supplies power to the main control MCU (1), the drain electrode of the MOS tube (4) is connected with one end of a fourth resistor R4(7), and the other end of the fourth resistor R4(7) is connected with a 4 th pin of the analog PWM chip (2);
a VCC power supply is connected to an 8 th pin of the analog PWM chip (2), the 8 th pin of the analog PWM chip (2) is connected with one end of a capacitor C (8), the other end of the capacitor C (8) is grounded, a 9 th pin of the analog PWM chip (2) is connected with a base electrode of a triode (9), a 10 th pin of the analog PWM chip (2) is connected with the base electrode of the triode (9), a 10 th pin of the analog PWM chip (2) is connected with an anode of a diode (10), a cathode of the diode (10) is connected with an emitting electrode of the triode (9), a base electrode of the triode (9) is connected with one end of a fifth resistor R5(11), and the other end of the fifth resistor R5(11) is connected with a collector electrode of the triode and then grounded; the 4 th pin of the analog PWM chip (2) is a DTC pin, the 8 th pin is a C1 pin, the 9 th pin is an E1 pin, and the 10 th pin is an E2 pin.
2. The interlock circuit realized by the output characteristic of the IO port of the single chip microcomputer according to claim 1, is characterized in that: the first resistor R1(3) is a protection resistor and is used for slowing down the switching rate of the MOS transistor (4).
3. The interlock circuit realized by the output characteristic of the IO port of the single chip microcomputer according to claim 1, is characterized in that: the second resistor R2(5) is a bleeder resistor for preventing the MOS transistor (4) from being broken down and providing bias voltage for the MOS transistor (4).
4. The interlock circuit realized by the output characteristic of the IO port of the single chip microcomputer according to claim 1, is characterized in that: the model of the analog PWM chip (2) is TL 494.
5. The interlock circuit realized by the output characteristic of the IO port of the single chip microcomputer according to claim 1, is characterized in that: the master control MCU (1), the first resistor R1(3) and the second resistor R2(5) form a channel, and the resistance values of the first resistor R1(3) and the second resistor R2(5) are 1K omega and 100K omega respectively.
6. The interlock circuit realized by the output characteristic of the IO port of the single chip microcomputer according to claim 1, is characterized in that: the third resistor R3(6) is a pull-up resistor, and the resistance value of the third resistor R3(6) is 10K omega.
7. The interlock circuit realized by the output characteristic of the IO port of the single chip microcomputer according to claim 1, is characterized in that: the 8 th pin of the analog PWM chip (2) is respectively in short circuit with the 11 th pin and the 12 th pin of the analog PWM chip (2), and the 13 th pin of the analog PWM chip (2) is grounded; the 11 th pin of the analog PWM chip (2) is a pin C2, the 12 th pin is a pin VCC, and the 13 th pin is a pin CONT.
8. The interlock circuit realized by the output characteristic of the IO port of the single chip microcomputer according to claim 1, is characterized in that: and an emitting electrode of the triode (9) is provided with a modulation signal output end.
9. The interlock circuit realized by the output characteristic of the IO port of the single chip microcomputer according to claim 1, is characterized in that: the resistance value of the fifth resistor R5(11) is 1K omega.
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| CN202110311706.XA CN113093594B (en) | 2021-03-24 | 2021-03-24 | Interlocking circuit realized by using output characteristic of IO port of single chip microcomputer |
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| CN202110311706.XA CN113093594B (en) | 2021-03-24 | 2021-03-24 | Interlocking circuit realized by using output characteristic of IO port of single chip microcomputer |
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| CN113093594B true CN113093594B (en) | 2022-03-04 |
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| CN209948949U (en) * | 2019-06-21 | 2020-01-14 | 珠海格力电器股份有限公司 | PWM shaping interlocking circuit for preventing short circuit of switching device |
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