CN211554886U - Singlechip circuit convenient to disconnect and reset - Google Patents
Singlechip circuit convenient to disconnect and reset Download PDFInfo
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- CN211554886U CN211554886U CN202020326677.5U CN202020326677U CN211554886U CN 211554886 U CN211554886 U CN 211554886U CN 202020326677 U CN202020326677 U CN 202020326677U CN 211554886 U CN211554886 U CN 211554886U
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Abstract
The utility model discloses a singlechip circuit convenient for disconnection and reset, which comprises a singlechip, a reset chip and an ISP download interface, and is also provided with a reset switch circuit, wherein the reset switch circuit comprises a first switch circuit and a second switch circuit, the first switch circuit is arranged between the reset chip and the singlechip, and the first switch circuit is connected with the ISP download interface through the second switch circuit; when the first pin of the ISP downloading interface is connected with a high level, the second switch circuit is switched on, and the first switch circuit is switched off; when the first pin of the ISP downloading interface is disconnected with a high level, the second switch circuit is cut off, and the first switch circuit is conducted. The utility model discloses an add two triodes in the circuit, can burn when writing at the procedure, prevent to reset chip control reset signal and reset, compare with prior art, it is more convenient to use, does not need control hardware to come control circuit.
Description
Technical Field
The utility model belongs to the technical field of the singlechip, especially, relate to a singlechip circuit who conveniently breaks off and resets.
Background
In the single chip system, it has program ISP download interface and external reset chip circuit. When programming, it may happen that the reset circuit is not controlled in time to cause reset. This often causes program download exceptions when downloading the program. In order to solve this problem, the reset signal line is usually disconnected during downloading, and the reset signal line is shorted after the program is downloaded.
As shown in fig. 1, the conventional single chip microcomputer system includes a single chip microcomputer, a reset chip and an ISP download interface, the reset chip has a triode, an emitter of the triode is grounded, a collector of the triode is connected to the single chip microcomputer through a switch, and the ISP download interface is connected to the single chip microcomputer. When programming, the automatic reset can be prevented only by disconnecting the switch, the use is inconvenient, and the switch is easy to damage or have poor contact by frequently plugging and unplugging the switch.
SUMMERY OF THE UTILITY MODEL
In order to solve the defects of the prior art, the utility model provides a singlechip circuit that conveniently breaks off and resets.
In order to achieve the purpose, the utility model provides a technical scheme does:
a kind of one-chip computer circuit which is easy to cut off and reset, including one-chip computer, reset chip and ISP downloads the interface, it also has reset switch circuit, the said reset switch circuit includes the first switch circuit and second switch circuit, the first switch circuit is set up between chip and one-chip computer of resetting, the first switch circuit downloads the interface through the second switch circuit connection ISP; when the first pin of the ISP downloading interface is connected with a high level, the second switch circuit is switched on, and the first switch circuit is switched off; when the first pin of the ISP downloading interface is disconnected with a high level, the second switch circuit is cut off, and the first switch circuit is conducted.
Preferably, the first switch circuit comprises a transistor Q1, a resistor R4, a resistor R5 and a resistor R6, and the second switch circuit comprises a transistor Q1, a resistor R1, a resistor R2 and a resistor R3;
the first pin of the ISP download interface is connected with the base electrode of a triode Q1 through a resistor R1, the second pin of the ISP download interface is connected with the first pin of the singlechip, and the first pin of the singlechip is connected with a power supply VCC through a resistor R6;
a triode Q3 is arranged in the reset chip, an emitting electrode of a triode Q3 is grounded, a collector electrode of a triode Q3 is connected with an emitting electrode of a triode Q1, the emitting electrode of the triode Q1 is connected with a base electrode of a triode Q1 through a resistor R5, the collector electrode of the triode Q1 is connected with a first pin of the single chip microcomputer, and the base electrode of the triode Q1 is connected with the collector electrode of a triode Q2 through a resistor R4; the collector of the transistor Q2 is connected to the power supply VCC through a resistor R3, the emitter of the transistor Q2 is grounded, and the base is connected to the emitter through a resistor R2.
Preferably, the third pin of the ISP download interface is connected to the second pin of the single chip.
Preferably, the fourth pin of the ISP download interface is connected to the third pin of the single chip.
The utility model discloses a singlechip circuit during operation, ISP download interface can connect an outside ware of writing with a fire (downloader), should write with a high level in the ware certainly to make ISP download interface's first pin insert the high level.
The resistor R1 of the utility model is a base current-limiting resistor of a triode Q2, which prevents the BE node of Q2 from being burnt out by overcurrent. R2 is BE node shunt resistance, guarantee when external disturbance, reliably close Q2. The resistor R4 is a base current limiting resistor of the triode Q1, the BE node of the Q1 is prevented from being burnt out due to overcurrent, and the resistor R5 is a BE node shunt resistor, so that the Q1 is reliably closed when external interference occurs. VCC connected to R6 is the pull-up resistance of the reset circuit. VCC connected to R3 is the bias circuit for Q2, Q1.
Adopt the technical scheme provided by the utility model, compare with prior art, have following beneficial effect:
the utility model discloses an add two triodes in the circuit, can burn when writing at the procedure, prevent to reset chip control reset signal and reset, compare with prior art, it is more convenient to use, does not need control hardware to come control circuit.
Drawings
FIG. 1 is a schematic diagram of a prior art circuit;
fig. 2 is a schematic circuit diagram of the present invention.
Detailed Description
For further understanding of the present invention, the present invention will be described in detail with reference to the following examples, which are provided for illustration of the present invention but are not intended to limit the scope of the present invention.
As shown in fig. 2, the present embodiment relates to a single chip microcomputer circuit facilitating disconnection and reset, which includes a single chip microcomputer, a reset chip, an ISP download interface, and a reset switch circuit, where the reset switch circuit includes a first switch circuit and a second switch circuit, the first switch circuit is disposed between the reset chip and the single chip microcomputer, and the first switch circuit is connected to the ISP download interface through the second switch circuit; when the first pin of the ISP downloading interface is connected with a high level, the second switch circuit is switched on, and the first switch circuit is switched off; when the first pin of the ISP downloading interface is disconnected with a high level, the second switch circuit is cut off, and the first switch circuit is conducted.
The first switch circuit comprises a triode Q1, a resistor R4, a resistor R5 and a resistor R6, and the second switch circuit comprises a triode Q1, a resistor R1, a resistor R2 and a resistor R3;
the first pin of the ISP download interface is connected with the base electrode of a triode Q1 through a resistor R1, the second pin of the ISP download interface is connected with the first pin of the singlechip, and the first pin of the singlechip is connected with a power supply VCC through a resistor R6;
a triode Q3 is arranged in the reset chip, an emitting electrode of a triode Q3 is grounded, a collector electrode of a triode Q3 is connected with an emitting electrode of a triode Q1, the emitting electrode of the triode Q1 is connected with a base electrode of a triode Q1 through a resistor R5, the collector electrode of the triode Q1 is connected with a first pin of the single chip microcomputer, and the base electrode of the triode Q1 is connected with the collector electrode of a triode Q2 through a resistor R4; the collector of the transistor Q2 is connected to the power supply VCC through a resistor R3, the emitter of the transistor Q2 is grounded, and the base is connected to the emitter through a resistor R2.
And a third pin of the ISP downloading interface is connected with a second pin of the singlechip. And a fourth pin of the ISP downloading interface is connected with a third pin of the singlechip.
The utility model discloses a theory of operation is:
when the programming device downloading program is not inserted into the ISP downloading interface, the reset chip can detect the single chip microcomputer once every 100ms, the single chip microcomputer cannot be reset when the normal operation of the single chip microcomputer is detected, and a reset signal can be sent to reset when the single chip microcomputer is detected to be abnormal.
When the programming device downloading program is inserted into the ISP downloading interface, the high level of the programming device enables the first pin of the ISP downloading interface to BE connected with the high level, the BE section of Q2 is conducted, and the CE section is started; the BE section of the Q1 is inverted, so that the Q1 is cut off, the reset chip is disconnected with the single chip microcomputer, and a reset signal cannot BE sent out.
After the programming device is downloaded, the programming device is pulled out, the BE node of Q2 is vacant, and the CE node is cut off; the BE node of Q1 is opened, so Q1 switches on, and the chip that resets is connected with the singlechip again, and the singlechip is controlled by the chip that resets.
The present invention and its embodiments have been described above schematically, without limitation, and what is shown in the drawings is merely an embodiment of the present invention, and the actual structure is not limited thereto. Therefore, those skilled in the art should understand that they can easily and effectively implement the present invention without departing from the spirit and scope of the present invention.
Claims (4)
1. A kind of one-chip computer circuit which is easy to cut off and reset, including one-chip computer, reset chip and ISP downloads the interface, characterized by that, it also has reset switch circuit, the said reset switch circuit includes the first switch circuit and second switch circuit, the first switch circuit is set up between chip and one-chip computer of resetting, the first switch circuit downloads the interface through the second switch circuit connection ISP; when the first pin of the ISP downloading interface is connected with a high level, the second switch circuit is switched on, and the first switch circuit is switched off; when the first pin of the ISP downloading interface is disconnected with a high level, the second switch circuit is cut off, and the first switch circuit is conducted.
2. The single chip microcomputer circuit for facilitating the disconnection reset of claim 1, wherein the first switch circuit comprises a transistor Q1, a resistor R4, a resistor R5 and a resistor R6, and the second switch circuit comprises a transistor Q1, a resistor R1, a resistor R2 and a resistor R3;
the first pin of the ISP download interface is connected with the base electrode of a triode Q1 through a resistor R1, the second pin of the ISP download interface is connected with the first pin of the singlechip, and the first pin of the singlechip is connected with a power supply VCC through a resistor R6;
a triode Q3 is arranged in the reset chip, an emitting electrode of a triode Q3 is grounded, a collector electrode of a triode Q3 is connected with an emitting electrode of a triode Q1, the emitting electrode of the triode Q1 is connected with a base electrode of a triode Q1 through a resistor R5, the collector electrode of the triode Q1 is connected with a first pin of the single chip microcomputer, and the base electrode of the triode Q1 is connected with the collector electrode of a triode Q2 through a resistor R4; the collector of the transistor Q2 is connected to the power supply VCC through a resistor R3, the emitter of the transistor Q2 is grounded, and the base is connected to the emitter through a resistor R2.
3. The single chip microcomputer circuit facilitating disconnection and reset of claim 2, wherein a third pin of the ISP download interface is connected to a second pin of the single chip microcomputer.
4. The single chip microcomputer circuit facilitating disconnection and reset of claim 2, wherein a fourth pin of the ISP download interface is connected to a third pin of the single chip microcomputer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020326677.5U CN211554886U (en) | 2020-03-16 | 2020-03-16 | Singlechip circuit convenient to disconnect and reset |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020326677.5U CN211554886U (en) | 2020-03-16 | 2020-03-16 | Singlechip circuit convenient to disconnect and reset |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211554886U true CN211554886U (en) | 2020-09-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020326677.5U Active CN211554886U (en) | 2020-03-16 | 2020-03-16 | Singlechip circuit convenient to disconnect and reset |
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| Country | Link |
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| CN (1) | CN211554886U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112486060A (en) * | 2020-11-20 | 2021-03-12 | 深圳市沃特沃德股份有限公司 | Reset circuit, circuit board and electronic product of singlechip |
-
2020
- 2020-03-16 CN CN202020326677.5U patent/CN211554886U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112486060A (en) * | 2020-11-20 | 2021-03-12 | 深圳市沃特沃德股份有限公司 | Reset circuit, circuit board and electronic product of singlechip |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: A single chip microcomputer circuit convenient for disconnection and reset Effective date of registration: 20211207 Granted publication date: 20200922 Pledgee: Hangzhou High-tech Financing Guarantee Co.,Ltd. Pledgor: HANGZHOU GUHENG ENERGY SCIENCE & TECHNOLOGY Co.,Ltd. Registration number: Y2021330002497 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20221213 Granted publication date: 20200922 Pledgee: Hangzhou High-tech Financing Guarantee Co.,Ltd. Pledgor: HANGZHOU GUHENG ENERGY SCIENCE & TECHNOLOGY Co.,Ltd. Registration number: Y2021330002497 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: A Convenient Circuit for Disconnecting and Resetting Single Chip Computers Effective date of registration: 20230327 Granted publication date: 20200922 Pledgee: Hangzhou High-tech Financing Guarantee Co.,Ltd. Pledgor: HANGZHOU GUHENG ENERGY SCIENCE & TECHNOLOGY Co.,Ltd. Registration number: Y2023330000605 |