CN113791927B - Watchdog control circuit, electronic device, and watchdog control method - Google Patents
Watchdog control circuit, electronic device, and watchdog control method Download PDFInfo
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- CN113791927B CN113791927B CN202111106926.5A CN202111106926A CN113791927B CN 113791927 B CN113791927 B CN 113791927B CN 202111106926 A CN202111106926 A CN 202111106926A CN 113791927 B CN113791927 B CN 113791927B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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Abstract
The embodiment of the invention discloses a watchdog control circuit, electronic equipment and a watchdog control method, wherein the watchdog control circuit comprises a processor, a selection module, a self-locking module, a three-state output control module and a watchdog, wherein the selection module outputs an unlocking signal to the self-locking module when a reset signal is input when the processor is electrified or reset begins; the self-locking module is used for outputting an enabling control release signal when an unlocking signal is input; the tri-state output control module is used for being in a high-resistance state when an enabling control release signal is input; the watchdog is used for stopping outputting the reset signal when the tri-state output control module is in a high-resistance state. The method has the advantages that when the program is burnt, debugged or powered on and started, the unlocking signal is output to the self-locking module through the selection module, the self-locking module outputs the enabling control releasing signal to enable the tri-state output control module to be in a high-resistance state so as to disable the watchdog, manual intervention is not needed to disable the watchdog, and the program is changed so as to optimize the starting efficiency, so that the program can be started normally.
Description
Technical Field
The embodiment of the invention relates to the technical field of electronic circuit monitoring, in particular to a watchdog control circuit, electronic equipment and a watchdog control method.
Background
In order to ensure the safe and reliable operation of the electronic equipment in the use process of the electronic equipment, a hardware watchdog is generally added to monitor the operation process of the electronic equipment so as to reset the electronic equipment by triggering the watchdog to output a reset signal after an abnormality occurs in the operation process of the electronic equipment.
In practical application, the program debugging, burning and starting loading time in the electronic equipment is too long, and the electronic equipment system cannot work normally due to the monitoring function of the watchdog. On the one hand, in order to solve the problem that the watchdog cannot work normally in program debugging and programming, a jumper wire or a dial switch is required to be added on a reset signal output by the watchdog, a reset signal loop is disconnected when the program is debugged or programmed, a watchdog circuit cannot work normally, and after the program is programmed or debugged, the reset signal loop is closed again, so that the watchdog circuit works normally; on the other hand, for the overlong program starting and loading time, firstly, the program is optimized to improve starting efficiency, and secondly, the output state of the dog feeding GPIO port is configured to determine the opening or closing of the function of the watchdog.
In summary, the control of the watchdog in the prior art during the program debugging, burning and starting stage has the following problems:
1) The addition of jumper or dial switch requires manual intervention;
2) Optimizing the starting efficiency of the program is complex, and the program needs to be changed;
3) After the output state of the configured watchdog GPIO port is in program failure or pin damage, the risk of failure exists in the watchdog function, and the reliability is low.
Disclosure of Invention
The aim of the embodiment of the invention is that: the invention provides a watchdog control circuit, electronic equipment and a watchdog control method, which are used for solving the problems that the control of the existing watchdog in the program debugging, burning and starting stages needs manual intervention, the program efficiency is optimized and complicated and the reliability is low, and the embodiment of the invention adopts the following technical scheme:
in a first aspect, a watchdog control circuit is provided, including a processor, a selection module, a self-locking module, a tri-state output control module and a watchdog, the processor is provided with a feeding dog signal output end and a reset signal input end, the watchdog is provided with a feeding dog signal input end and a reset signal output end, the input end of the selection module is respectively connected with the feeding dog signal output end and the reset signal input end, the output end of the selection module is connected with the input end of the self-locking module, the signal input end of the tri-state output control module is connected with the feeding dog signal output end, the enabling input end of the tri-state output control module is connected with the output end of the self-locking module, the output end of the tri-state output control module is connected with the feeding dog signal input end,
the selection module is used for outputting an unlocking signal to the self-locking module when a reset signal is input when the processor is electrified or triggered to reset, and outputting a locking signal to the self-locking module when a feeding dog signal is input;
the self-locking module is used for outputting an enabling control signal when the locking signal is input and outputting an enabling control release signal when the unlocking signal is input;
the tri-state output control module is used for outputting a dog feeding signal input from the dog feeding signal output end when the enabling control signal is input, and outputting a high-impedance signal to stop a watchdog monitoring function when the enabling control release signal is input;
the watchdog is used for stopping the watchdog monitoring function when the tri-state output control module outputs a high-resistance signal, and outputting a reset signal from the reset signal output end when the dog feeding signal input end does not have the dog feeding signal input within a preset time.
Optionally, the selection module is provided with a first input end, a second input end and a first output end, and the first input end and the second input end are respectively connected with the feeding dog signal output end and the reset signal input end;
the self-locking module is provided with a third input end and a second output end, and the third input end is connected with the first output end;
the tri-state output control module is provided with a third output end, the enabling input end is connected with the second output end, the signal input end is connected with the dog feeding signal output end, and the third output end is connected with the dog feeding signal input end.
Optionally, the selecting module is configured to output a high-level lock signal from the first output terminal when the high-level feeding signal is input to the first input terminal, output a high-impedance signal from the first output terminal when the low-level feeding signal is input to the first input terminal,
and when the second input end inputs the high-level reset signal, the first output end outputs a high-resistance state signal.
Optionally, the selection module includes first diode, second diode, first resistance that establish ties in proper order, wherein, the negative pole of first diode with reset signal input is connected, the negative pole of second diode with the positive pole of first diode is connected, the positive pole of second diode passes through first resistance with feed dog signal output part is connected, the negative pole of first diode is as first input, first resistance with feed dog signal output part is connected one end and is as second input, first diode with the public node of second diode is as first output.
Optionally, the self-locking module is configured to output an enable control signal from the second output terminal after the third input terminal receives the locking signal output by the first output terminal, lock the second output terminal in a locked state of the output enable control signal, maintain the locked state of the second output terminal after the third input terminal receives the high-impedance signal output by the first output terminal,
and after the third input end receives the unlocking signal output by the first output end, outputting an enabling control release signal from the second output end and releasing the locking state of the second output end.
Optionally, the self-locking module includes a first triode, a second resistor, a third resistor, a fourth resistor and a fifth resistor;
the emitter of the first triode is connected with a power supply through the second resistor, the collector of the first triode is grounded through the third resistor, the collector of the second triode is connected with the power supply through the fifth resistor, the emitter of the second triode is grounded, the base of the second triode is connected with the collector of the first triode through the fourth resistor, the base of the first triode is connected with the collector of the second triode, the common node of the collector of the first triode and the third resistor is used as the third input end, and the common node of the collector of the second triode and the second resistor is used as the second output end.
Optionally, the tri-state output control module includes a tri-state output control chip, where the tri-state output control chip is provided with an enable pin, a dog feeding signal input pin and a dog feeding signal output pin, the enable pin is used as the enable input end, the dog feeding signal input pin is used as the signal input end, and the dog feeding signal output pin is used as the third output end.
Optionally, the watchdog comprises a watchdog chip, and the watchdog chip is provided with a feeding dog signal input end and a reset signal output end.
In a second aspect, there is provided an electronic device comprising the watchdog control circuit of any of the first aspects.
In a third aspect, a watchdog control method is provided, which is applied to the electronic device in the second aspect, and includes:
when the processor is powered on or triggers reset, controlling the watchdog to output a reset signal;
when the reset signal is input into the selection module, controlling the selection module to output an unlocking signal;
when the unlocking signal is input into the self-locking module, controlling the self-locking module to output an enabling control release signal;
when the enabling control release signal is input into the tri-state output control module, controlling the tri-state output control module to output a high-resistance state signal so as to stop the watchdog monitoring function;
and stopping the watchdog monitoring function when the tri-state output control module outputs a high-resistance state signal.
Optionally, the method further comprises:
when the processor is powered on or reset is finished, controlling the processor to output a dog feeding signal and controlling a reset input end of the processor to be in a high level;
when the feeding signal is input into the selection module, controlling the selection module to output a locking signal;
when the locking signal is input into the self-locking module, controlling the self-locking module to output an enabling control signal;
when the enabling control signal is input into the three-state output control module, controlling the three-state output control module to output the received dog feeding signal;
and outputting a feeding dog signal at the tri-state output control module, and controlling the watchdog to output a reset signal when the feeding dog signal is not received within a preset time period.
The watchdog control circuit comprises a processor, a selection module, a self-locking module, a three-state output control module and a watchdog, wherein when the program is burnt, debugged or powered on to start the watchdog function, the watchdog outputs a reset signal to the self-locking module through the selection module, the self-locking module outputs an enabling control release signal to enable the three-state output control module to be in a high-impedance state so as to disable the watchdog function, the watchdog stops outputting the reset signal, the processor does not receive the reset signal of the watchdog when the program is burnt, debugged or powered on, the processor outputs a lock signal to the self-locking module after the program is burnt, debugged or powered on to start the watchdog, the self-locking module outputs an enabling control signal to the three-state output control module, the three-state output control module outputs a watchdog signal to the watchdog, and the watchdog works normally after the program is started. On one hand, manual intervention is not needed to disable the watchdog function during program burning and debugging, so that the program burning and debugging efficiency is improved, and on the other hand, the program is not needed to be changed to optimize starting efficiency and configure a watchdog feeding signal output port to disable and enable the watchdog, so that normal starting of the program is ensured, and the reliability of a watchdog control circuit is improved.
Drawings
The invention is described in further detail below with reference to the drawings and examples.
Fig. 1 is a circuit block diagram of a watchdog control circuit according to an embodiment of the present invention.
Fig. 2 is a schematic circuit diagram of a watchdog control circuit according to an embodiment of the present invention.
Fig. 3 is a flowchart of a watchdog control method according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems solved by the present invention, the technical solutions adopted and the technical effects achieved more clear, the technical solutions of the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
In the description of the present invention, unless explicitly stated and limited otherwise, the terms "connected," "connected," and "fixed" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Fig. 1 is a circuit block diagram of a watchdog control circuit according to an embodiment of the present invention, and as shown in fig. 1, the watchdog control circuit according to an embodiment of the present invention includes a processor 10, a selection module 20, a self-locking module 30, a tri-state output control module 40, and a watchdog 50.
The processor 10 may be an integrated circuit with data processing capability running one or more applications, the processor 10 is provided with a watchdog signal output wdi_out for outputting a watchdog signal to watchdog 50 and a reset signal input reset_in, and the watchdog signal output wdi_out may be a high level signal. The watchdog 50 may be a hardware watchdog, and the watchdog 50 is provided with a watchdog signal input wdi_in and a reset signal output reset_out, and the reset signal output reset_out may be a low level signal.
As shown in fig. 1, in the embodiment of the present invention, the input end of the selection module 20 is connected to the dog feeding signal output end wdi_out and the reset signal input end reset_in, the output end of the selection module 20 is connected to the input end of the self-locking module 30, the input end of the tri-state output control module 40 is connected to the output end of the self-locking module 30 and the dog feeding signal output end wdi_out, and the output end of the tri-state output control module 40 is connected to the dog feeding signal input end wdi_in.
Specifically, as shown In fig. 1, the selection module 20 is provided with a first input terminal in_1, a second input terminal in_2, and a first output terminal out_1, the first input terminal in_1 and the second input terminal in_2 are respectively connected with the feeding signal output terminal wdi_out and the reset signal input terminal reset_in, the self-locking module 30 is provided with a third input terminal in_3 and a second output terminal out_2, the third input terminal in_3 is connected with the first output terminal out_1, the tri-state output control module 40 is provided with an enable input terminal, a signal input terminal and a third output terminal, the enable input terminal in_4 is connected with the second output terminal out_2, the signal input terminal in_5 is connected with the feeding signal output terminal wdi_out, and the third output terminal out_3 is connected with the feeding signal input terminal wdi_in.
Wherein the selection module 20 is configured to output an unlock signal to the latching module 30 when a reset signal (i.e., a reset signal is output when the watchdog 50 is powered up due to characteristics of the watchdog 50) is input when the processor 10 is powered up or triggers reset, and output a lock signal to the latching module 30 when a watchdog-in signal is input, the latching module 30 is configured to output an enable control signal when the lock signal is input, and output an enable control release signal when the unlock signal is input, the tri-state output control module 40 is configured to output a watchdog-in signal input from the watchdog-in signal output terminal wdi_out when the enable control signal is input, and output a high-impedance signal to stop a watchdog monitoring function when the enable control release signal is input, and the watchdog 50 is configured to stop a watchdog monitoring function when the tri-state output control module 40 outputs a high-impedance signal, and output a reset signal from the reset signal output terminal reset_out when the watchdog-in no-in signal is input within a preset period.
In order to make the principle of the watchdog control circuit according to the embodiments of the present invention more clearly understood by those skilled in the art, the following describes the operation principle of the watchdog control circuit with reference to the circuit schematic diagrams of fig. 1 and 2.
As shown In fig. 1, in the embodiment of the present invention, the selection module 20 is configured to output a high-level lock signal from the first output terminal out_1 when the in_1 high-level feeding signal is input to the first input terminal, output a high-impedance signal from the first output terminal out_1 when the in_1 low-level feeding signal is input to the first input terminal, and output a low-impedance signal from the first output terminal out_1 when the in_2 low-level reset signal is input to the second input terminal in_2, and output a high-impedance signal from the first output terminal out_1 when the in_1 high-level reset signal is input to the second input terminal in_2.
As shown in fig. 2, in one possible example, the selection module 20 includes a first diode VD1, a second diode VD2, and a first resistor R1 sequentially connected in series, where a cathode of the first diode VD1 is connected to the reset signal input terminal reset_in, a cathode of the second diode VD2 is connected to an anode of the first diode VD1, an anode of the second diode VD2 is connected to the dog feeding signal output terminal wdi_out through the first resistor R1, a cathode of the first diode VD1 is used as a first input terminal of the selection module 20, an end of the first resistor R1 connected to the dog feeding signal output terminal wdi_out is used as a second input terminal of the selection module 20, and a common node of the first diode VD1 and the second diode VD2 is used as a first output terminal of the selection module 20.
The selection module 20 shown in fig. 1 and 2 operates on the following principle: when the system is powered on or reset and reinitialized, the reset signal output end reset_out of the watchdog 50 outputs a low-level reset signal of 140-280 ms due to the characteristics of the watchdog 50, the processor 10 is initialized to complete the reset operation, and the dog feeding signal output end WDI_out of the processor 10 has no signal output in the process of initializing the processor 10. When the reset signal output terminal reset_out of the watchdog 50 outputs a reset signal of a low level, the first diode VD1 is in a forward conducting state, and no matter whether the watchdog signal output terminal wdi_out outputs a high level watchdog signal, the anode of the first diode VD1 is clamped by the first diode VD1 to a low level of a voltage drop of the first diode VD1, so that a common node of the first diode VD1 and the second diode VD2, which is the first output terminal of the selection module 20, outputs an unlock signal of a low level to the self locking module 30. When the initialization of the processor 10 is completed, the reset signal input terminal reset_in of the processor 10 is at a high level, the first diode VD1 is turned off reversely, and does not respond to the high level reset signal, meanwhile, the dog feeding signal output terminal wdi_out of the processor 10 outputs a high level dog feeding signal, and the second diode VD2 is turned on positively, so that the common node of the first diode VD1 and the second diode VD2 as the first output terminal out_1 of the selection module 20 outputs a high level locking signal to the self-locking module 30, and when the dog feeding signal output terminal wdi_out of the processor 10 is at a low level, the second diode VD2 is turned off reversely, and the common node of the first diode VD1 and the second diode VD2 as the first output terminal out_1 of the selection module 20 outputs a high resistance signal, that is, does not respond to the low level dog feeding signal, thereby realizing that the selection module 20 outputs a low level unlocking signal to the self-locking module 30 when the low level reset signal is input, and the high level locking signal is output to the self-locking module 30.
As shown In fig. 1, in the embodiment of the present invention, the self-locking module 30 is configured to output an enable control signal from the second output terminal out_2 after the third input terminal in_3 receives the lock signal output by the first output terminal out_1, lock the second output terminal out_2 In a locked state of the output enable control signal, maintain the locked state of the second output terminal out_2 after the third input terminal in_3 receives the high-impedance state signal output by the first output terminal out_1, and output an enable control release signal from the second output terminal out_2 and release the locked state of the second output terminal out_2 after the third input terminal in_3 receives the unlock signal output by the first output terminal out_1.
As shown in fig. 2, in one example, the self-locking module 30 includes a first triode VT1, a second triode VT2, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5, an emitter of the first triode VT1 is connected to the power VCC through the second resistor R2, a collector of the first triode VT1 is grounded through the third resistor R3, a collector of the second triode VT2 is connected to the power VCC through the fifth resistor R5, an emitter of the second triode VT2 is grounded, a base of the second triode VT2 is connected to a collector of the first triode VT1 through the fourth resistor R4, a base of the first triode VT1 is connected to a collector of the second triode VT2, a common node between the collector of the first triode VT1 and the third resistor R3 is a third input end of the self-locking module 30, a common node between the collector of the second triode VT2 and the second resistor R2 is a second output end of the self-locking module 30, wherein the first triode VT1 is a PNP type triode, and the collector of the second triode VT2 is a NPN type.
The self-locking module 30 shown in fig. 1 and 2 operates on the following principle: the first triode VT1 in the self-locking module 30 is a PNP type triode, the second triode VT2 is an NPN type triode, after receiving the high-level locking signal output by the selection module 20, the second triode VT2 is turned on, the level of the collector of the second triode VT2 is pulled down, that is, the enable pin OE of the tri-state output control chip U1 is low, at this time, since the base of the first triode VT1 is connected with the collector of the second triode VT2, the first triode VT1 is turned on, after the first triode VT1 is turned on, the level at the node where the first triode VT1 is connected with the third resistor R3 and the fourth resistor R4 is pulled up, so that the second triode VT2 is maintained in a turned-on state, when the high-level locking signal output by the selection module 20 is realized, the first triode VT1 and the second triode VT2 in the self-locking module 30 are maintained in a turned-on locking state, that is, the locking state of the locking signal output by the second output end out_2 is maintained in a high-level locking state. When the low-level unlock signal output by the selection module 20 is received, the low-level unlock signal is output to the first triode VT1, the third resistor R3, the fourth resistor R4, the second triode VT2 is turned off, the collector of the second triode VT2 is pulled up to the power VCC through the fifth resistor R5, that is, the collector of the second triode VT2 is at a high level, the enable pin OE of the tri-state output control chip connected with the collector of the second triode VT2 becomes a high level, at this time, the base of the first triode VT1 is turned off due to the high level, and the whole self-locking module 30 is unlocked.
The tri-state output control module 40 includes a tri-state output control chip U1, where the tri-state output control chip U1 is provided with an enable pin OE, a dog feeding signal input pin a and a dog feeding signal output pin Y, the enable pin OE is an enable input end in_4 of the tri-state output control module 40, the dog feeding signal input pin a is a signal input end in_5 of the tri-state output control module 40, and the dog feeding signal output pin Y is a third output end of the tri-state output control module 40.
The watchdog 50 includes a watchdog chip U2, and the watchdog chip U2 is provided with a watchdog signal input wdi_in and a reset signal output reset_out.
The three-state output control module 40 operates on the principle that: the enabling pin OE is an enabling end of the tri-state output control chip U1, the enabling pin OE is effective when the enabling pin OE is in a low level signal, even if the enabling pin OE is in a low level signal, the dog feeding signal output pin Y of the tri-state output control chip U1 directly outputs the dog feeding signal input by the dog feeding signal input pin A so as to realize the dog feeding of the watchdog 50, and when the enabling pin OE is in a high level signal, the dog feeding signal output pin Y of the tri-state output control chip U1 outputs a high-resistance signal, namely, no output state, the monitoring function of the watchdog 50 is forbidden, so that the output state of the dog feeding signal output pin Y is controlled by controlling the level of the enabling pin OE of the tri-state output control chip U1, and the inhibition, the enabling or the dog feeding of the function of the watchdog 50 is realized.
The watchdog 50 outputs a low-level reset signal of 140-280 ms when powered on, the function of the watchdog 50 can be enabled or disabled through the state of the watchdog feeding signal input end wdi_in, namely, when the watchdog feeding signal input end wdi_in is in a high-impedance state, the function of the watchdog 50 is disabled, when the watchdog feeding signal input end wdi_in is in a high-level state, the function of the watchdog 50 is enabled, when the watchdog 50 is in a monitoring state normally, the watchdog 50 needs to receive the watchdog feeding signal from the watchdog feeding signal input end wdi_in within a stipulated time, and when the watchdog feeding signal is not received for more than a preset time, the watchdog 50 outputs a reset signal from the reset signal output end reset_out to reset the processor 10.
The watchdog control circuit comprises a processor, a selection module, a self-locking module, a three-state output control module and a watchdog, wherein when the program is burnt, debugged or powered on to start the watchdog function, the watchdog outputs a reset signal to the self-locking module through the selection module, the self-locking module outputs an enabling control release signal to enable the three-state output control module to be in a high-impedance state so as to disable the watchdog function, the watchdog stops outputting the reset signal, the processor does not receive the reset signal of the watchdog when the program is burnt, debugged or powered on, the processor outputs a lock signal to the self-locking module after the program is burnt, debugged or powered on to start the watchdog, the self-locking module outputs an enabling control signal to the three-state output control module, the three-state output control module outputs a watchdog signal to the watchdog, and the watchdog works normally after the program is started. On one hand, manual intervention is not needed to disable the watchdog function during program burning and debugging, so that the program burning and debugging efficiency is improved, and on the other hand, the program is not needed to be changed to optimize starting efficiency and configure a watchdog feeding signal output port to disable and enable the watchdog, so that normal starting of the program is ensured, and the reliability of a watchdog control circuit is improved.
The embodiment of the invention also provides electronic equipment which comprises the watchdog control circuit, wherein the electronic equipment can be electronic equipment in an elevator system, such as a main control board, a motor control board, a door closing detection control board and the like of an elevator in the elevator equipment.
Fig. 3 is a flowchart of a watchdog control method according to an embodiment of the present invention. The watchdog control method shown in fig. 3 may be applied to an electronic device provided by the embodiment of the present invention, where the watchdog control circuit includes a processor, a selection module, a self-locking module, a tri-state output control module, and a watchdog, and the watchdog control method may include the following steps:
and S301, when the processor is powered on or reset is triggered, controlling the watchdog to output a reset signal.
As shown in fig. 1, when the program is burned and debugged, or the system is powered on or reset, the watchdog monitoring function of the watchdog needs to be disabled, so that the watchdog can be controlled to output a low-level reset signal of 140-280 ms, namely, the watchdog is generally powered on, namely, the watchdog outputs a low-level reset signal.
S302, when the reset signal is input into the selection module, controlling the selection module to output an unlocking signal.
As shown in fig. 1, one input terminal of the selection module 20 is connected to the reset signal input terminal reset_in of the processor 10, so that a reset signal is input into the selection module 20, so that the selection module outputs a low-level unlock signal to the self-locking module 30, specifically, the low-level unlock signal to the self-locking module 30 may be implemented by the circuit principle of the selection module 20, and the specific details are shown in the circuit schematic diagram of the selection module 20 shown in fig. 2 and the description of the operation principle of the selection module 20 in the above embodiment of the watchdog control circuit will not be described in detail herein.
And S303, when the unlocking signal is input into the self-locking module, controlling the self-locking module to output an enabling control release signal.
As shown in the schematic circuit diagram of the self-locking module 30 in fig. 2, when the low-level unlocking signal is input to the self-locking module, the self-locking module 30 outputs the enable control release signal to the enable pin OE of the tri-state output control module 40, and the detailed principle is referred to the description of the working principle of the selection module 20 in the above embodiment of the watchdog control circuit, and will not be described in detail herein.
And S304, when the enabling control release signal is input into the tri-state output control module, controlling the tri-state output control module to output a high-resistance state signal so as to stop the watchdog monitoring function.
As shown in the schematic circuit diagram of the tri-state output control module 40 in fig. 2, when the enable control release signal is input to the enable pin OE of the tri-state output control module 40, the tri-state output control module 40 outputs a high-impedance signal, and the detailed description of the operation principle of the tri-state output control module 40 is omitted herein.
And S305, stopping the watchdog monitoring function when the tri-state output control module outputs a high-resistance state signal.
As shown in fig. 2, since the tri-state output control module 40 is in a high-impedance state, the tri-state output control module 40 outputs a high-impedance state signal, the watchdog function is disabled because the watchdog signal input end wdi_in of the watchdog 50 is not input, and the watchdog function is disabled when the processor is started by burning, debugging and power-on reset, so that the processor can be started normally.
After the normal start of the processor, the watchdog control method of the embodiment of the invention further comprises the following steps: when the processor is powered on or reset is finished, the control processor outputs a dog feeding signal, the reset input end of the control processor is in a high level, the control selection module outputs a locking signal when the dog feeding signal is input into the selection module, the self-locking module is controlled to output an enabling control signal when the locking signal is input into the self-locking module, the tri-state output control module is controlled to output the received dog feeding signal when the enabling control signal is input into the tri-state output control module, and the tri-state output control module outputs the dog feeding signal to control the watchdog to output a reset signal when the dog feeding signal is not received within a preset time length, so that the watchdog function is started to monitor the processor after the processor starts outputting the dog feeding signal.
The watchdog control circuit method of the embodiment of the invention is applied to the watchdog control circuit of the embodiment of the invention, and the watchdog control circuit comprises a processor, a selection module, a self-locking module, a three-state output control module and a watchdog, so that when the watchdog function is required to be disabled during program burning, debugging or power-on starting, the watchdog outputs a reset signal to the self-locking module through the selection module, the self-locking module outputs an enabling control release signal to enable the three-state output control module to be in a high-impedance state so as to disable the watchdog function, the watchdog stops outputting the reset signal, the processor does not receive the reset signal of the watchdog during program burning, debugging or power-on starting, the processor outputs a locking signal to the self-locking module after the program burning, debugging or power-on starting, the self-locking module outputs an enabling control signal to the self-locking module, the three-state output control module outputs a feeding signal to the watchdog, and the watchdog normally works after the program is started. On one hand, manual intervention is not needed to disable the watchdog function during program burning and debugging, so that the program burning and debugging efficiency is improved, and on the other hand, the program is not needed to be changed to optimize the starting efficiency, so that the program can be started normally.
In the description herein, the terms "first," "second," and "second" are used merely to distinguish between the descriptions and have no special meaning.
In the description herein, reference to the term "one embodiment," "an example," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate technical solution, and this description is provided for clarity only, and those skilled in the art should consider the disclosure as a whole, and the technical solutions in the embodiments may be appropriately combined to form other embodiments that can be understood by those skilled in the art.
The technical principle of the present invention is described above in connection with the specific embodiments. The description is made for the purpose of illustrating the general principles of the invention and should not be taken in any way as limiting the scope of the invention. Other embodiments of the invention will be apparent to those skilled in the art from consideration of this specification without undue burden.
Claims (11)
1. The watchdog control circuit is characterized by comprising a processor, a selection module, a self-locking module, a three-state output control module and a watchdog, wherein the processor is provided with a dog feeding signal output end and a reset signal input end, the watchdog is provided with a dog feeding signal input end and a reset signal output end, the input end of the selection module is respectively connected with the dog feeding signal output end and the reset signal input end, the output end of the selection module is connected with the input end of the self-locking module, the signal input end of the three-state output control module is connected with the dog feeding signal output end, the enabling input end of the three-state output control module is connected with the output end of the self-locking module, the output end of the three-state output control module is connected with the dog feeding signal input end,
the selection module is used for outputting an unlocking signal to the self-locking module when a reset signal is input when the processor is electrified or triggered to reset, and outputting a locking signal to the self-locking module when a feeding dog signal is input;
the self-locking module is used for outputting an enabling control signal when the locking signal is input and outputting an enabling control release signal when the unlocking signal is input;
the tri-state output control module is used for outputting a dog feeding signal input from the dog feeding signal output end when the enabling control signal is input, and outputting a high-impedance signal to stop a watchdog monitoring function when the enabling control release signal is input;
the watchdog is used for stopping the watchdog monitoring function when the tri-state output control module outputs a high-resistance signal, and outputting a reset signal from the reset signal output end when the dog feeding signal input end does not have the dog feeding signal input within a preset time.
2. The watchdog control circuit of claim 1, wherein,
the selection module is provided with a first input end, a second input end and a first output end, and the first input end and the second input end are respectively connected with the feeding signal output end and the reset signal input end;
the self-locking module is provided with a third input end and a second output end, and the third input end is connected with the first output end;
the tri-state output control module is further provided with a third output end, the enabling input end is connected with the second output end, the signal input end is connected with the dog feeding signal output end, and the third output end is connected with the dog feeding signal input end.
3. The watchdog control circuit of claim 2, wherein the selection module is configured to output a high lock signal from the first output terminal when a high level watchdog feeding signal is input to the first input terminal, output a high impedance signal from the first output terminal when a low level watchdog feeding signal is input to the first input terminal,
and when the second input end inputs the high-level reset signal, the first output end outputs a high-resistance state signal.
4. A watchdog control circuit according to claim 2 or 3, wherein the selection module comprises a first diode, a second diode and a first resistor connected in series in sequence, wherein the cathode of the first diode is connected with the reset signal input terminal, the cathode of the second diode is connected with the anode of the first diode, the anode of the second diode is connected with the dog feeding signal output terminal through the first resistor, the cathode of the first diode is used as the first input terminal, the end of the first resistor connected with the dog feeding signal output terminal is used as the second input terminal, and the common node of the first diode and the second diode is used as the first output terminal.
5. The watchdog control circuit of claim 2, wherein the self-locking module is configured to output an enable control signal from the second output terminal after the third input terminal receives the lock signal output from the first output terminal, and lock the second output terminal in a locked state of the output enable control signal, maintain the locked state of the second output terminal after the third input terminal receives the high impedance signal output from the first output terminal,
and after the third input end receives the unlocking signal output by the first output end, outputting an enabling control release signal from the second output end and releasing the locking state of the second output end.
6. The watchdog control circuit of claim 2 or 5, wherein the latching module comprises a first transistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor;
the emitter of the first triode is connected with a power supply through the second resistor, the collector of the first triode is grounded through the third resistor, the collector of the second triode is connected with the power supply through the fifth resistor, the emitter of the second triode is grounded, the base of the second triode is connected with the collector of the first triode through the fourth resistor, the base of the first triode is connected with the collector of the second triode, the common node of the collector of the first triode and the third resistor is used as the third input end, and the common node of the collector of the second triode and the second resistor is used as the second output end.
7. The watchdog control circuit according to claim 2, wherein the tri-state output control module comprises a tri-state output control chip provided with an enable pin, a watchdog signal input pin and a watchdog signal output pin, the enable pin being the enable input, the watchdog signal input pin being the signal input, and the watchdog signal output pin being the third output.
8. The watchdog control circuit of claim 2, wherein the watchdog comprises a watchdog chip provided with a watchdog signal input and a reset signal output.
9. An electronic device comprising the watchdog control circuit of any of claims 1-8.
10. A watchdog control method, characterized by being applied to the electronic device of claim 9, comprising:
when the processor is powered on or triggers reset, controlling the watchdog to output a reset signal;
when the reset signal is input into the selection module, controlling the selection module to output an unlocking signal;
when the unlocking signal is input into the self-locking module, controlling the self-locking module to output an enabling control release signal;
when the enabling control release signal is input into the tri-state output control module, controlling the tri-state output control module to output a high-resistance state signal so as to stop the watchdog monitoring function;
and stopping the watchdog monitoring function when the tri-state output control module outputs a high-resistance state signal.
11. The watchdog control method of claim 10, further comprising:
when the processor is powered on or reset is finished, controlling the processor to output a dog feeding signal and controlling a reset input end of the processor to be in a high level;
when the feeding signal is input into the selection module, controlling the selection module to output a locking signal;
when the locking signal is input into the self-locking module, controlling the self-locking module to output an enabling control signal;
when the enabling control signal is input into the three-state output control module, controlling the three-state output control module to output the received dog feeding signal;
and outputting a feeding dog signal at the tri-state output control module, and controlling the watchdog to output a reset signal when the feeding dog signal is not received within a preset time period.
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