CN220651243U - Watchdog chip control circuit - Google Patents
Watchdog chip control circuit Download PDFInfo
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- CN220651243U CN220651243U CN202322382887.2U CN202322382887U CN220651243U CN 220651243 U CN220651243 U CN 220651243U CN 202322382887 U CN202322382887 U CN 202322382887U CN 220651243 U CN220651243 U CN 220651243U
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- watchdog
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- 230000004048 modification Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
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- 238000011084 recovery Methods 0.000 description 1
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Abstract
The utility model provides a watchdog chip control circuit, which comprises: the device comprises a watchdog chip, a microcontroller, a connector and a logic inverter, wherein the connector is electrically connected with the logic inverter, the logic inverter is electrically connected with the watchdog chip, the watchdog chip is electrically connected with the microcontroller, and the microcontroller is electrically connected with the connector. The watchdog chip control circuit has the characteristics of convenient implementation and low cost, and in practical application, the microcontroller of the connector is not in short circuit for normal starting, and the watchdog chip is in a working state of normal monitoring program operation; when the connector is in short circuit, the microcontroller enters a downloading mode, and the watchdog chip is forbidden to operate, so that the watchdog chip does not reset the microcontroller because the watchdog chip does not receive the feeding pulse of the microcontroller, and the downloading mode of the microcontroller is ensured not to be interrupted by the watchdog chip.
Description
Technical Field
The utility model relates to the technical field of control circuits, in particular to a watchdog chip control circuit.
Background
Along with the increasing complexity of the working environment of the electronic equipment, the functions are more and more powerful, the program structure is more and more complex, the instruction codes are longer and longer, the equipment is out of control due to the influence of the field working environment, the program runs away, and the probability of the dead halt of each functional module is greatly increased. Currently, in order to prevent a program of a microcontroller (MCU, microcontroller Unit) from running into a dead loop and not continuing to work normally, a watchdog function needs to be added, an existing Microcontroller (MCU) is usually provided with an internal watchdog module, a time is set for an application program to enable the internal watchdog device during initialization, then the application program uses a thread to feed a dog, the execution time of the thread is far less than the time set by the watchdog, and after a system (or the application program) is abnormal, the thread for feeding the dog does not work naturally, and at the moment, the watchdog module resets the MCU microcontroller.
However, when the internal watchdog module is used, the internal watchdog module can be used only after being initialized by software, and if the program runs before the initialization and the starting are completed, the watchdog cannot reset the system, so that the function of the watchdog is lost, and the recovery capability of the system is reduced. Therefore, the reliability of the internal watchdog is insufficient, at this time, another more reliable method is to use an external watchdog chip, the external watchdog chip does not need a program to initialize the external watchdog chip, and the external watchdog chip has pins such as power supply, grounding, enabling, WDI (WatchDog Input), WDO (WatchDog Output) and the like, when the WDI pin detects edge jump every time, the watchdog count is reset, if no watchdog feeding pulse on the WDI pin is detected within the set timeout time, the WDO pin is pulled down for a period of time, and the external watchdog chip is immediately in a working state after being powered up, so that the operation scene which does not need to use the watchdog is interrupted. For example, when the program is updated, the micro controller MCU needs to enter a downloading mode, and at the moment, the MCU micro controller does not output a feeding pulse because the system program is not running, the watchdog chip can pull down the WDO pin to cause the system to restart continuously, so that the program downloading cannot be completed, and inconvenience is brought to the work.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present utility model is to provide a watchdog chip control circuit for solving the problem of restart vulnerability of an external watchdog chip circuit in the prior art.
To achieve the above and other related objects, the present utility model provides a watchdog chip control circuit, the circuit comprising: the device comprises a watchdog chip, a microcontroller, a connector and a logic inverter, wherein the connector is electrically connected with the logic inverter, the logic inverter is electrically connected with the watchdog chip, the watchdog chip is electrically connected with the microcontroller, and the microcontroller is electrically connected with the connector.
In an embodiment of the utility model, the connector is a dual pin connector.
In an embodiment of the utility model, a first pin of the connector is electrically connected to the dc power supply through a first resistor, and a second pin of the connector is grounded through a second resistor.
In an embodiment of the present utility model, a first pin of the logic inverter is electrically connected to a second pin of the connector, a second pin of the logic inverter is grounded, and a third pin of the logic inverter is electrically connected to an enable pin of the watchdog chip.
In an embodiment of the present utility model, a watchdog signal input pin of the watchdog chip is electrically connected to an input/output pin of the microcontroller, and a watchdog output pin of the watchdog chip is electrically connected to a reset pin of the microcontroller.
In an embodiment of the utility model, a watchdog output pin of the watchdog chip is connected to a dc power supply through a third resistor.
In an embodiment of the utility model, a power pin of the watchdog chip is electrically connected to the dc power supply, and the power pin of the watchdog chip is grounded through a first capacitor.
In an embodiment of the utility model, a power pin of the microcontroller is electrically connected to the dc power supply, and the power pin of the microcontroller is grounded through a second capacitor.
In an embodiment of the utility model, a BOOT pin of the microcontroller is electrically connected to the second pin of the connector.
In an embodiment of the present utility model, the watchdog chip and the ground pin of the microcontroller are grounded.
As described above, the watchdog chip control circuit has the characteristics of convenient implementation and low cost, and in practical application, the microcontroller of the connector is not in short circuit for normal starting, and the watchdog chip is in a working state of normal monitoring program operation; when the connector is in short circuit, the microcontroller enters a downloading mode, and the watchdog chip is forbidden to operate, so that the watchdog chip does not reset the microcontroller because the watchdog chip does not receive the feeding pulse of the microcontroller, and the downloading mode of the microcontroller is ensured not to be interrupted by the watchdog chip.
Drawings
Fig. 1 is a schematic diagram of a watchdog chip control circuit according to the present utility model.
Description of element reference numerals
U1 watchdog chip
U2 microcontroller
SW1 connector
Q1 logic inverter
First pin of A logic inverter
Second pin of B logic inverter
Third pin of C logic inverter
First pin of TP1 connector
Second pin of TP2 connector
R1 first resistor
R2 second resistor
R3 third resistor
C1 First capacitor
C2 Second capacitor
Detailed Description
Other advantages and effects of the present utility model will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present utility model with reference to specific examples. The utility model may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present utility model. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present utility model by way of illustration, and only the components related to the present utility model are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
Furthermore, it should be further understood that the terms "first," "second," "third," and the like in this specification are used solely to distinguish one from another component, element, step, or the like in the specification, but do not necessarily denote a logical or sequential relationship between individual components, elements, steps, or the like, nor should they be construed as indicating or implying a relative importance or order of such components or steps.
It should be noted that, the problem of reliability deficiency exists in the use of the internal watchdog module, and the problem that the program cannot be downloaded due to continuous restarting of the control system exists in the use of the external watchdog chip, so that special scenes need to be considered when the external watchdog is used, and the application provides a watchdog chip control circuit capable of meeting the special scenes.
Specifically, referring to fig. 1, the present utility model provides a watchdog chip U1 control circuit, including: the device comprises a watchdog chip U1, a microcontroller U2, a connector SW1 and a logic inverter Q1, wherein the connector SW1 is electrically connected with the logic inverter Q1, the logic inverter Q1 is electrically connected with the watchdog chip U1, the watchdog chip U1 is electrically connected with the microcontroller U2, and the microcontroller U2 is electrically connected with the connector SW 1.
It should be noted that, the connector SW1 is a dual-pin connector, wherein the first pin TP1 of the connector is electrically connected to the dc power supply through the first resistor R1, and the second TP2 of the connector is grounded through the second resistor R2, specifically, two pins (TP 1 and TP2 respectively) of the connector are shorted in some situations, so that an effect can be achieved more conveniently, such as a burning fixture used on a production line.
Further, the first pin a of the logic inverter is electrically connected with the second pin TP2 of the connector, the second pin B of the logic inverter is grounded, the third pin C of the logic inverter is electrically connected with the enable pin EN of the watchdog chip U1, the watchdog signal input pin WDI of the watchdog chip U1 is electrically connected with the input/output pin IO0 of the microcontroller U2, the watchdog output pin WDO of the watchdog chip U1 is electrically connected with the RESET pin RESET of the microcontroller U2, the watchdog output pin WDO of the watchdog chip U1 is electrically connected with the dc power supply through the third resistor R3, the power pin of the watchdog chip U1 is electrically connected with the dc power supply, the power pin of the watchdog chip U1 is grounded through the first capacitor C1, the power pin of the microcontroller U2 is electrically connected with the dc power supply, and the power pin of the microcontroller U2 is grounded through the second capacitor C2. Further, the BOOT pin of the microcontroller U2 is electrically connected to the second pin TP2 of the connector, and both the watchdog chip U1 and the ground pin "GND" of the microcontroller U2 are grounded.
Specifically, in an embodiment of the present utility model, it is assumed that the dc power VCC is "3.3V", and of course, according to different schemes, any other reasonable voltage value may be adopted, where the first resistor R1 is "10kΩ", the second resistor R2 is "100 k Ω", R2/r1=10, and of course, any other reasonable resistance ratio may be adopted, where the first resistor R1 and the second resistor R2 only satisfy that the voltage division, the BOOT signal is at a logic high level, so that when two pins of the connector are shorted, the microcontroller is in a download mode, the watchdog chip is in a disabled state, the upper end of the first resistor R1 is connected to the dc power of "3.3V", and the lower end is connected to the first pin TP1 of the connector; the upper end of the second resistor R2 is connected with the second pin TP2 of the connector, the BOOT pin of the microcontroller U2 and the first pin A of the logic inverter, the lower end of the second resistor R2 is grounded, the second pin B of the logic inverter is grounded, the third pin C of the logic inverter is connected with the enabling pin of the watchdog chip U1, wherein in a connection circuit of the second resistor R2 and the logic inverter Q1, the relation between the first pin A (BOOT signal) of the logic inverter and the third pin C (WDT_EN signal) of the logic inverter is as follows: "boot=0v, wdt_en=3.3v; boot=3.3v, wdt_en=0v.
Further, the power supply pin of the watchdog chip U1 is connected to the dc power VCC and the first capacitor C1, the enable pin of the watchdog chip U1 is connected to the third pin C of the logic inverter, the ground pin of the watchdog chip U1 is directly grounded, the watchdog signal input pin of the watchdog chip U1 is connected to the input/output pin of the microcontroller U2, the watchdog output pin of the watchdog chip U1 is connected to the reset pin of the microcontroller U2, wherein the third resistor R3 connected to the power supply is further required to be added to the watchdog output pin of the U1 so as to represent a high level ("3.3V") when the "WDO" outputs a high resistance, so that the watchdog output pin is connected to the reset pin of the U2, and the watchdog output pin outputs a low level (e.g. "0V") when the "WDI" does not have a feeding pulse within a set time, and the output pin of the microcontroller U2 is reset when the enable pin is low level (e.g. "0V") is not stable, and the output of the watchdog output is in a high level (e.3V) when the microcontroller is not in a reset mode. Because when the enabling pin of the watchdog chip U1 is "0V", the watchdog chip U1 is in the disabled state, and the watchdog output pin is in the high-resistance state no matter whether the watchdog feeding signal input pin thereof receives the watchdog feeding pulse, the voltage of the watchdog output pin is about "3.3V" due to the third resistor R3. When the enabling pin of the watchdog chip U1 is 3.3V, the watchdog chip U1 is in a normal working state, and if the watchdog feeding signal input pin receives a watchdog feeding pulse signal within a set time, the watchdog output pin keeps a high-resistance state to be about 3.3V; if the watchdog signal input pin does not receive a watchdog pulse within a set time, the watchdog outputs "0V", and the watchdog output pin of the watchdog chip U1 and the reset pin of the microcontroller U2 are connected together, so that the microcontroller U2 resets the restart procedure because the reset pin becomes "0V".
Further, the BOOT pin of the microcontroller U2 is connected to the second pin TP2 of the connector, and is connected to the upper end of the second resistor R2 and the first pin a of the logic inverter, the power pin of the microcontroller U2 is connected to the dc power VCC, and the ground pin of the microcontroller U2 is directly grounded, where the input/output pin of the microcontroller U2 generates a watchdog feeding pulse signal to the watchdog signal input pin of the watchdog chip U1, when the reset pin of the microcontroller U2 is at a low level (e.g. "0V"), the microcontroller U2 is in a reset state, and cannot work normally, and when the reset pin is at a high level (e.g. "3.3V"), the microcontroller U2 is in a normal working state, and because the watchdog output pin of the watchdog chip U1 is connected to the reset pin of the microcontroller U2, when the watchdog output pin of the watchdog chip U1 outputs a low level (e.g. "0V"), the microcontroller U2 resets and restarts the program.
Further, as shown in table 1, descriptions of the components of the control circuit under different shorting scenarios of the connector are shown.
TABLE 1 connector shorting detail table
It should be noted that, for the situation that the connector SW1 is not shorted, the microcontroller U2 is normally started and the watchdog chip U1 is in a normal working state after power-on, specifically as follows: when SW1 is not shorted, the BOOT pin of the microcontroller U2 and the BOOT signal are pulled down to "0V" (low level) by the second resistor R2, and as shown in table 1, the microcontroller U2 is normally started, and at this time, the watchdog enable pin is "3.3V (high level), and the watchdog chip U1 is in an enabled state (normal operating state).
For the short circuit scenario of the connector SW1, the short circuit can be performed through the jumper cap in specific application, and the short circuit can be performed through other modes, so that the short circuit is not limited in the application, and in addition, the short circuit refers to the short circuit of two pins of the connector SW 1. Wherein, microcontroller U2 can get into download mode and watchdog chip U1 is in the forbidden state after the power on, and watchdog chip U1 can not reset microcontroller U2 because of not receiving the watchdog pulse signal, and microcontroller U2's download mode can not be interrupted, and microcontroller U2 can stable download procedure, specifically as follows: when the connector SW1 is shorted, the BOOT pin of the microcontroller U2 and the BOOT signal are pulled down to "3.3V" (high level) by the first resistor R1 and the second resistor R2, and as shown in table 1, the microcontroller U2 enters the download mode, the watchdog enable pin is "0V" (low level), the watchdog chip U1 is in the disabled state, although the microcontroller U2 enters the download mode without outputting the watchdog feeding pulse to the watchdog signal input pin of the watchdog chip U1, the watchdog output pin of the watchdog chip U1 still maintains the high level (e.g., "3.3V"), the reset pin of the microcontroller U2 connected to the watchdog output pin also maintains the high level (e.g., "3.3V"), the microcontroller U2 is not reset to restart the program, and is stably in the download mode.
In summary, the watchdog chip U1 control circuit has the characteristics of convenient implementation and low cost, and in practical application, the microcontroller of the connector is not in short circuit for normal starting, and the watchdog chip is in a working state of normal monitoring program operation; when the connector is in short circuit, the microcontroller enters a downloading mode, and the watchdog chip is forbidden to operate, so that the watchdog chip does not reset the microcontroller because the watchdog chip does not receive the feeding pulse of the microcontroller, and the downloading mode of the microcontroller is ensured not to be interrupted by the watchdog chip.
The above embodiments are merely illustrative of the principles of the present utility model and its effectiveness, and are not intended to limit the utility model. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the utility model. Accordingly, it is intended that all equivalent modifications and variations of the utility model be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (12)
1. A watchdog chip control circuit, the circuit comprising:
a watchdog chip, a microcontroller, a connector and a logic inverter, wherein,
the connector is electrically connected with the logic inverter, the logic inverter is electrically connected with the watchdog chip, the watchdog chip is electrically connected with the microcontroller, and the microcontroller is electrically connected with the connector.
2. The watchdog chip control circuit of claim 1, wherein the connector is a dual pin connector.
3. The watchdog chip control circuit of claim 2, wherein a first pin of the connector is electrically connected to the dc power supply through a first resistor and a second pin of the connector is grounded through a second resistor.
4. The watchdog chip control circuit of claim 3, wherein a first pin of the logic inverter is electrically connected to a second pin of the connector, the second pin of the logic inverter is grounded, and a third pin of the logic inverter is electrically connected to an enable pin of the watchdog chip.
5. The watchdog chip control circuit of claim 4, wherein a watchdog signal input pin of the watchdog chip is electrically connected to an input/output pin of the microcontroller, and a watchdog output pin of the watchdog chip is electrically connected to a reset pin of the microcontroller.
6. The watchdog chip control circuit of claim 5, wherein a watchdog output pin of the watchdog chip is connected to a dc power supply through a third resistor.
7. The watchdog chip control circuit of claim 5, wherein a power pin of the watchdog chip is electrically connected to the dc power supply, and the power pin of the watchdog chip is grounded via a first capacitor.
8. The watchdog chip control circuit of claim 4, wherein a power pin of the microcontroller is electrically connected to the dc power supply and the power pin of the microcontroller is grounded via a second capacitor.
9. The watchdog chip control circuit of claim 3, wherein a BOOT pin of the microcontroller is electrically connected to a second pin of the connector.
10. The watchdog chip control circuit of claim 1, wherein the watchdog chip and the ground pin of the microcontroller are both grounded.
11. The watchdog chip control circuit of claim 9, wherein the microcontroller is normally enabled when the two pins of the connector are not shorted, the watchdog chip being in an enabled state; when the two pins of the connector are short-circuited, the microcontroller is in a downloading mode, and the watchdog chip is in a forbidden state.
12. The watchdog chip control circuit of claim 11, wherein when the watchdog chip is in an inhibit state, a BOOT signal corresponding to the BOOT pin after the voltage division by the first resistor and the second resistor is at a logic high level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322382887.2U CN220651243U (en) | 2023-09-01 | 2023-09-01 | Watchdog chip control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322382887.2U CN220651243U (en) | 2023-09-01 | 2023-09-01 | Watchdog chip control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220651243U true CN220651243U (en) | 2024-03-22 |
Family
ID=90268851
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322382887.2U Active CN220651243U (en) | 2023-09-01 | 2023-09-01 | Watchdog chip control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220651243U (en) |
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2023
- 2023-09-01 CN CN202322382887.2U patent/CN220651243U/en active Active
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