CN209784946U - controllable reset circuit based on single chip microcomputer - Google Patents
controllable reset circuit based on single chip microcomputer Download PDFInfo
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- CN209784946U CN209784946U CN201920823922.0U CN201920823922U CN209784946U CN 209784946 U CN209784946 U CN 209784946U CN 201920823922 U CN201920823922 U CN 201920823922U CN 209784946 U CN209784946 U CN 209784946U
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Abstract
The utility model discloses a steerable reset circuit based on singlechip, include: the single chip microcomputer module receives a heartbeat signal from the processor, and generates a fault signal when the heartbeat signal is judged to be abnormal; and the reset circuit is connected with the singlechip module and generates a reset signal according to the fault signal so as to restart the processor. The utility model discloses an operating condition who utilizes the heartbeat signal that the singlechip was received to judge the treater in real time resets and restarts in order to send fault signal to the treater, and the software card dies to lead to when having avoided pure software to reset and resets not effective and special watchdog chip not nimble enough regulation of resetting trigger condition's problem, has also solved the unable problem that normally during operation circuit can't reset of single chip module, has improved the successful stability and the flexibility that reset of whole circuit.
Description
Technical Field
The embodiment of the utility model provides a reset circuit field especially relates to a steerable reset circuit based on singlechip.
Background
In electronic devices, especially microcomputer systems, the problem of restarting the whole system program is often encountered, so that reset circuits are currently used to restore the circuits to the initial state.
The main function of the reset circuit is to prevent the electronic system from going into a dead cycle or down due to a special situation. The existing reset circuit has the problems that reset software is blocked or enters dead cycle to cause unsuccessful reset and the reset time of a reset device can not be flexibly adjusted due to self reasons.
SUMMERY OF THE UTILITY MODEL
The utility model aims to avoid the dead problem that leads to not taking effect and the not nimble regulation trigger condition that resets of special watchdog chip of resetting of software card that pure software resets.
In order to achieve the above object, the utility model provides a steerable reset circuit based on singlechip, include:
The singlechip module is used for receiving the heartbeat signal from the processor and generating a fault signal when the heartbeat signal is judged to be abnormal;
And the reset circuit is connected with the singlechip module and generates a reset signal according to the fault signal so as to restart the processor.
Further, the single chip microcomputer module comprises a single chip microcomputer chip, the reset circuit comprises a watchdog chip, and a pin 7 of the watchdog chip is connected to a reset pin 1 of the processor and used for the watchdog chip to send a reset signal to the processor so as to complete resetting.
Further, pin 1 of the watchdog chip is connected to a dc power supply through a resistor R3, and is also connected to a ground terminal through a capacitor C2, and pin 6 of the watchdog chip is connected to the dc power supply through a resistor R6, so as to ensure that a high-level signal is continuously input to pin 6.
Further, pin 2 of the watchdog chip is connected to a direct current power supply, and is connected to pin 3 of the watchdog chip through parallel capacitors C3 and C4, and pin 3 and pin 4 of the watchdog chip are connected to a ground terminal.
Further, pin 1 and pin 2 of the single chip microcomputer chip are respectively connected with a signal output pin of the processor and used for receiving heartbeat signals sent by the processor, and pin 5 and pin 6 of the single chip microcomputer chip are respectively connected with a program input pin of the processor and used for receiving a program for burning the single chip microcomputer chip by the processor so as to establish judgment logic for judging whether the heartbeat signals are normal or not.
Further, pin 5 of the monolithic chip is connected to the dc power supply through a resistor R9, pin 6 of the monolithic chip is connected to pin 9 of the dc power supply monolithic chip through a resistor R8, and is connected to the dc power supply through a reverse light emitting diode D2 and a resistor R7.
Further, pin 1 of the single chip is connected to the dc power supply through a resistor R11, pin 2 of the single chip is connected to the dc power supply through a resistor R12, pin 3, pin 12 and pin 21 of the single chip are connected to the ground, pin 4 of the single chip is connected to the ground through parallel capacitors C5 and C6 and is connected to the dc power supply through a resistor R7, pin 20 of the single chip is connected to the dc power supply through a resistor R10 and is connected to the ground through a capacitor C7, and is connected to pin 1 of the watchdog chip through series resistors R2 and R1.
Further, the method also comprises the following steps: and the switching circuit is electrically connected with a pin 1 of the watchdog chip and used for providing a fault signal when being triggered.
Further, the switch circuit includes a push button switch connected between pin 1 of the watchdog chip and ground.
Further, the switch circuit further comprises a capacitor C1 and an anti-static diode D1, the push button switch is connected to pin 1 of the watchdog chip through a resistor R1, is connected to pin 20 of the single chip microcomputer chip through a resistor R2, is connected to the ground through a capacitor C1 and an anti-static diode D1 which are connected in parallel, and the anode of the anti-static diode D1 is grounded.
The beneficial effects of the utility model reside in that act as the function of traditional watchdog through the singlechip, software card dies to lead to when having avoided pure software to reset resets and does not take effect and the problem of the not nimble regulation trigger condition that resets of special watchdog chip.
drawings
Fig. 1 is a flowchart of a controllable reset circuit based on a single chip in the first embodiment;
Fig. 2 is a circuit diagram of a controllable reset circuit based on a single chip in the second embodiment;
Fig. 3 is a circuit diagram of a controllable reset circuit based on a single chip in the third embodiment.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a flowchart of a controllable reset circuit based on a single chip according to an embodiment of the present invention. As shown in fig. 1, a controllable reset circuit based on a single chip microcomputer includes a single chip microcomputer module 11 and a reset circuit 12.
And the singlechip module 11 receives the heartbeat signal from the processor 13, and generates a fault signal when judging that the heartbeat signal is abnormal.
The reset circuit 12 is connected with the single chip module 11, and the reset circuit 12 generates a reset signal according to the fault signal to restart the processor 13.
Specifically, in this embodiment, the reset circuit 12 may be a watchdog chip that does not enable the automatic reset function, and is connected to the single chip module 11, and after the reset circuit 12 receives the fault signal from the single chip module 11, the reset circuit 12 generates a reset signal according to the fault signal to restart the processor 13.
The first embodiment has the beneficial effect of avoiding the problems that the reset is not effective due to dead software blocking when pure software is reset and the special watchdog chip is not flexible enough to adjust the reset triggering condition.
Example two
fig. 2 is a circuit diagram of a controllable reset circuit based on a single chip microcomputer according to a second embodiment of the present invention. As shown in fig. 2, a controllable reset circuit based on a single chip microcomputer includes a single chip microcomputer module and a reset circuit.
In this embodiment, the single chip module includes a single chip 21, and the reset circuit includes a watchdog chip 22.
The watchdog chip 22 of the present embodiment includes pins 1 to 4 and pins 6 to 8.
Pin 1 of the watchdog chip 22 is connected to an external dc power supply D3V3 through a resistor R3, and is connected to ground through a capacitor C2.
Pin 2 of the watchdog chip 22 is connected to a dc power supply D3V3, and is connected to pin 3 of the watchdog chip 22 through parallel capacitors C3 and C4, and pin 3 and pin 4 of the watchdog chip 22 are connected to ground. Specifically, the dc power supply D3V3 of this embodiment may be a 600 ma dc power supply, the adopted resistor may be a chip resistor, and the capacitor may be a chip capacitor.
Pin 6 of the watchdog chip 22 is connected to the dc power supply D3V3 through a resistor R6, pin 7 of the watchdog chip 22 is connected to the dc power supply D3V3 through a resistor R5, and pin 8 of the watchdog chip 22 is connected to the dc power supply D3V3 through a resistor R4.
The one-chip microcomputer chip 21 of the present embodiment includes at least pins 1 to 6, pin 9, pin 12, pin 20, and pin 21.
Pin 1 of the one-chip 21 is connected to a dc power supply D3V3 through a resistor R11.
Pin 2 of the one-chip 21 is connected to a dc power supply D3V3 through a resistor R12.
Pin 3, pin 12, and pin 21 of the one-chip 21 are connected to a ground terminal.
Pin 4 of the one-chip 21 is connected to ground through parallel capacitors C5 and C6, and is connected to a dc power supply D3V3 through a resistor R7.
Pin 5 of the one-chip 21 is connected to a dc power supply D3V3 through a resistor R9.
Pin 6 of the one-chip 21 is connected to a dc power supply D3V3 through a resistor R8.
the pin 9 of the single chip 21 is connected to the dc power supply D3V3 through the reverse led D2 and the resistor R7.
Pin 20 of the one-chip 21 is connected to dc power supply D3V3 through resistor R10, to ground through capacitor C7, and to pin 1 of the watchdog chip 22 through series connected resistors R2 and R1.
in this embodiment, pin 7 of the watchdog chip 22 is connected to the reset pin 1 of the processor 23 for the watchdog chip 22 to send a reset signal to the processor 23 to complete the reset.
In this embodiment, the reset circuit is connected to the single chip module, and the reset circuit generates a reset signal according to the fault signal to restart the processor. Specifically, when the pin 2 of the monolithic chip 21 of the monolithic module does not detect a heartbeat signal or a heartbeat signal is abnormal, an MR _ RESET _ IN signal (fault signal) is sent to the RESET circuit through the pin 20 of the monolithic chip 21, at this time, the pin 1 of the watchdog chip 22 of the RESET circuit is pulled low, the trigger pin 7 is pulled low, and thus, the pin 1 of the processor 23 is used for resetting the processor 23, so that the whole circuit is RESET and restarted. The heartbeat signal of this embodiment may be a square wave pulse signal with a preset pulse width and duration, the model of the single chip microcomputer chip may be U717, and the model of the watchdog chip may be U715.
When pin 2 of the one-chip microcomputer 21 normally receives the heartbeat signal from the processor 23, and the failure signal is not generated when the heartbeat signal is judged to be normal. Specifically, when a high-level signal is continuously input to pin 6 of the watchdog chip 22, it is ensured that the automatic reset function of the watchdog chip 22 cannot be triggered, and at this time, the watchdog chip 22 only plays a role in driving the reset signal.
Pin 1 and pin 2 of the single chip microcomputer chip 21 of this embodiment are connected to signal output pin 2 and pin 3 of the processor 23, respectively, and are configured to receive a heartbeat signal sent by the processor 23, and pin 5 and pin 6 are connected to program input pin 4 and pin 5 of the processor 23, respectively, and are configured to receive a program for burning the single chip microcomputer chip 21 by the processor 23, so as to establish a judgment logic for judging whether the heartbeat signal is normal.
Compared with the prior art, the beneficial effects of this embodiment are that through the operating condition who utilizes the heartbeat signal that singlechip received to judge the treater in real time in order to send the fault signal to reset the restart to the treater, avoided pure software to reset when dead software card leads to reset not effective and special watchdog chip not nimble enough the regulation reset trigger condition's problem.
EXAMPLE III
Fig. 3 is a circuit diagram of another controllable reset circuit based on a single chip according to the third embodiment of the present invention. As shown in fig. 3, a controllable reset circuit based on a single chip microcomputer includes a single chip microcomputer module and a reset circuit.
In this embodiment, the single chip microcomputer module includes a single chip microcomputer chip 31, and the reset circuit includes a watchdog chip 32.
The watchdog chip 32 of the present embodiment includes pins 1 to 4 and pins 6 to 8.
Pin 1 of the watchdog chip 32 is connected to an external dc power supply D3V3 through a resistor R3, and is connected to ground through a capacitor C2.
Pin 2 of the watchdog chip 32 is connected to a dc power supply D3V3, and is connected to pin 3 of the watchdog chip 32 through parallel capacitors C3 and C4, and pin 3 and pin 4 of the watchdog chip 32 are connected to ground. Specifically, the dc power supply D3V3 of this embodiment may be a 600 ma dc power supply, the adopted resistor may be a chip resistor, and the capacitor may be a chip capacitor.
Pin 6 of the watchdog chip 32 is connected to the dc power supply D3V3 through a resistor R6, pin 7 of the watchdog chip 32 is connected to the dc power supply D3V3 through a resistor R5, and pin 8 of the watchdog chip 32 is connected to the dc power supply D3V3 through a resistor R4.
The one-chip 31 of the present embodiment includes at least pins 1 to 6, pin 9, pin 12, pin 20, and pin 21.
Pin 1 of the one-chip microcomputer chip 31 is connected to a direct-current power supply D3V3 through a resistor R11.
Pin 2 of the one-chip microcomputer chip 31 is connected to a direct-current power supply D3V3 through a resistor R12.
Pin 3, pin 12 and pin 21 of the single chip microcomputer chip 31 are connected to the ground terminal.
Pin 4 of the microchip 31 is connected to ground through parallel capacitors C5 and C6, and is also connected to a dc power supply D3V3 through a resistor R7.
Pin 5 of the one-chip microcomputer chip 31 is connected to a direct current power supply D3V3 through a resistor R9.
Pin 6 of the one-chip microcomputer chip 31 is connected to a direct-current power supply D3V3 through a resistor R8.
The pin 9 of the singlechip chip 31 is connected to a direct current power supply D3V3 through a reverse light emitting diode D2 and a resistor R7.
The pin 20 of the single chip 31 is connected to a direct current power supply D3V3 through a resistor R10, is connected to a ground terminal through a capacitor C7, and is connected to the pin 1 of the watchdog chip 32 through series-connected resistors R2 and R1.
The controllable reset circuit based on the single chip microcomputer in the embodiment further comprises: and the switching circuit is electrically connected with the pin 1 of the watchdog chip 32 and is used for providing a fault signal when being triggered.
The switch circuit may include a push button switch S1 connected between pin 1 of the watchdog chip 32 and ground. Specifically, when the single chip microcomputer module is damaged or cannot normally work completely, the effect of successfully resetting the whole circuit can be achieved by controlling the button switch S1 of the switch circuit.
The switch circuit further comprises a capacitor C1 and an anti-static diode D1, the push-button switch S1 is connected to pin 1 of the watchdog chip 32 through a resistor R1, is connected to pin 20 of the singlechip chip 31 through a resistor R2, and is connected to the ground through a capacitor C1 and an anti-static diode D1 which are connected in parallel. The anode of the electrostatic prevention diode D1 of the present embodiment is grounded. The anti-static diode of the embodiment can prevent the problem of circuit breakdown caused by the fact that a human body touches the key switch when the human body is charged with static electricity, and specific numerical values of the capacitor and the resistor in the switch circuit can be adjusted according to the specific circuit.
In this embodiment, pin 7 of the watchdog chip 32 is connected to the reset pin 1 of the processor 33 for the watchdog chip 32 to send a reset signal to the processor 33 to complete the reset.
In this embodiment, the reset circuit is connected to the single chip module, and the reset circuit generates a reset signal according to the fault signal to restart the processor. Specifically, when the pin 2 of the single chip microcomputer chip 31 of the single chip microcomputer module does not detect a heartbeat signal or the heartbeat signal is abnormal, an MR _ RESET _ IN signal (fault signal) is sent to the RESET circuit through the pin 20 of the single chip microcomputer chip 31, at this time, the pin 1 of the watchdog chip 32 of the RESET circuit is pulled down, the trigger pin 7 is pulled down, and therefore the processor 33 is RESET through the pin 1 of the processor 33, and the whole circuit is RESET and restarted. The heartbeat signal of this embodiment may be a square wave pulse signal with a preset pulse width and duration, the model of the single chip microcomputer chip may be U717, and the model of the watchdog chip may be U715.
When pin 2 of the single chip 31 normally receives the heartbeat signal from the processor 33, and a fault signal is not generated when the heartbeat signal is judged to be normal. Specifically, when the pin 6 of the watchdog chip 32 continuously inputs a high-level signal, it is ensured that the automatic reset function of the watchdog chip 32 cannot be triggered, and at this time, the watchdog chip 32 only plays a role in driving the reset signal.
Pin 1 and pin 2 of the single chip microcomputer chip 31 of this embodiment are connected to signal output pin 2 and pin 3 of the processor 33, respectively, and are configured to receive a heartbeat signal sent by the processor 33, and pin 5 and pin 6 are connected to program input pin 4 and pin 5 of the processor 33, respectively, and are configured to receive a program for burning the single chip microcomputer chip 31 by the processor 33, so as to establish a judgment logic for judging whether the heartbeat signal is normal.
Compared with the prior art, the beneficial effects of this embodiment are that through the operating condition that utilizes the heartbeat signal that singlechip received to judge the treater in real time in order to send the fault signal to reset and restart the treater, avoided pure software card dead when resetting and lead to resetting not effective and the problem of the not nimble regulation trigger condition that resets of special watchdog chip, also solved the unable problem that resets of circuit when singlechip module can't normally work, improved the successful stability and the flexibility of whole circuit reset.
It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments illustrated herein, but is capable of various obvious modifications, rearrangements and substitutions without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.
Claims (10)
1. A controllable reset circuit based on a single chip microcomputer is characterized by comprising:
The single chip microcomputer module receives a heartbeat signal from the processor, and generates a fault signal when the heartbeat signal is judged to be abnormal;
And the reset circuit is connected with the singlechip module and generates a reset signal according to the fault signal so as to restart the processor.
2. The controllable reset circuit based on the single chip microcomputer according to claim 1, wherein the single chip microcomputer module comprises a single chip microcomputer chip, the reset circuit comprises a watchdog chip, and a pin 7 of the watchdog chip is connected to a reset pin 1 of the processor, so that the watchdog chip sends the reset signal to the processor to complete the reset.
3. The controllable reset circuit based on the single chip microcomputer of claim 2, wherein pin 1 of the watchdog chip is connected to a dc power supply through a resistor R3, and is connected to a ground terminal through a capacitor C2, and pin 6 of the watchdog chip is connected to the dc power supply through a resistor R6, for ensuring that a high level signal is continuously input to pin 6.
4. The controllable reset circuit based on the single chip microcomputer of claim 3, wherein pin 2 of the watchdog chip is connected to the DC power supply and is connected to pin 3 of the watchdog chip through parallel capacitors C3 and C4, and pin 3 and pin 4 of the watchdog chip are connected to ground.
5. The controllable reset circuit based on the single chip microcomputer according to claim 2, wherein pin 1 and pin 2 of the single chip microcomputer chip are respectively connected to a signal output pin of the processor for receiving the heartbeat signal sent by the processor, and pin 5 and pin 6 of the single chip microcomputer chip are respectively connected to a program input pin of the processor for receiving a program for burning the single chip microcomputer chip by the processor, so as to establish a judgment logic for judging whether the heartbeat signal is normal.
6. The MCU-based controllable reset circuit according to claim 4, wherein pin 5 of the MCU chip is connected to the DC power supply through a resistor R9, pin 6 of the MCU chip is connected to the DC power supply through a resistor R8, and pin 9 of the MCU chip is connected to the DC power supply through a reverse LED D2 and a resistor R7.
7. The controllable reset circuit based on single chip microcomputer according to claim 6, wherein pin 1 of the single chip microcomputer chip is connected to the dc power supply through a resistor R11, pin 2 of the single chip microcomputer chip is connected to the dc power supply through a resistor R12, pin 3, pin 12 and pin 21 of the single chip microcomputer chip are connected to ground, pin 4 of the single chip microcomputer chip is connected to ground through parallel capacitors C5 and C6 and is connected to the dc power supply through a resistor R7, pin 20 of the single chip microcomputer chip is connected to the dc power supply through a resistor R10 and is connected to ground through a capacitor C7 and is connected to pin 1 of the watchdog chip through series resistors R2 and R1.
8. The controllable reset circuit based on the single chip microcomputer according to claim 2, further comprising: and the switch circuit is electrically connected with a pin 1 of the watchdog chip and used for providing a fault signal when being triggered.
9. the MCU-based controllable reset circuit according to claim 8, wherein the switch circuit comprises a push button switch connected between pin 1 of the watchdog chip and ground.
10. The controllable reset circuit based on a single chip microcomputer according to claim 9, wherein the switch circuit further comprises a capacitor C1 and an anti-static diode D1, the push button switch is connected to pin 1 of the watchdog chip through a resistor R1, is connected to pin 20 of the single chip microcomputer chip through a resistor R2, is connected to a ground terminal through a parallel capacitor C1 and an anti-static diode D1, and the anode of the anti-static diode D1 is grounded.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920823922.0U CN209784946U (en) | 2019-06-03 | 2019-06-03 | controllable reset circuit based on single chip microcomputer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920823922.0U CN209784946U (en) | 2019-06-03 | 2019-06-03 | controllable reset circuit based on single chip microcomputer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111679929A (en) * | 2020-06-03 | 2020-09-18 | 北京经纬恒润科技有限公司 | Control method applied to multi-core heterogeneous system |
| CN113325779A (en) * | 2021-06-07 | 2021-08-31 | 沈阳铁路信号有限责任公司 | Reset signal safety output circuit and implementation method |
-
2019
- 2019-06-03 CN CN201920823922.0U patent/CN209784946U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111679929A (en) * | 2020-06-03 | 2020-09-18 | 北京经纬恒润科技有限公司 | Control method applied to multi-core heterogeneous system |
| CN113325779A (en) * | 2021-06-07 | 2021-08-31 | 沈阳铁路信号有限责任公司 | Reset signal safety output circuit and implementation method |
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