CN114610514A - Watchdog control circuit and equipment - Google Patents
Watchdog control circuit and equipment Download PDFInfo
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- CN114610514A CN114610514A CN202210126288.1A CN202210126288A CN114610514A CN 114610514 A CN114610514 A CN 114610514A CN 202210126288 A CN202210126288 A CN 202210126288A CN 114610514 A CN114610514 A CN 114610514A
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- watchdog
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
Abstract
The application discloses watchdog control circuit and equipment. The watchdog control circuit includes: the watchdog circuit, the control circuit and the processing chip; the watchdog circuit comprises a watchdog chip, the control circuit is connected with the watchdog, the control circuit comprises a control chip, and the processing chip is connected with the control circuit. When the equipment is started, the processing chip is used for sending a first enabling signal to the control circuit to control the control chip to keep a closed state, and the control chip controls the watchdog chip to keep the closed state according to the first enabling signal; after the equipment is started, the processing chip is used for sending a second enabling signal to the control circuit to control the control chip to be opened, and the control chip controls the watchdog chip to be opened according to the second enabling signal so that the watchdog circuit is in a working state. The watchdog control circuit in this application makes the watchdog open and lock as required and enable the state for the equipment that has complex system also can normally start, improve the stability of equipment operation.
Description
Technical Field
The application relates to the technical field of electronics, in particular to a watchdog control circuit and equipment.
Background
In the related art, in a device provided with a watchdog circuit, a watchdog chip is turned on upon power-on, and a processing chip must issue a watchdog feeding signal within a predetermined time, otherwise the watchdog chip may restart the device. When the kernel file of the device system is large, the kernel needs to be decompressed for a longer time, and the time may exceed the preset time, so that the watchdog outputs a reset signal to restart the device, and the device cannot be normally started.
Disclosure of Invention
The embodiment of the application provides a watchdog control circuit and equipment.
The watchdog control circuit of the embodiment of the application comprises: the watchdog circuit, the control circuit and the processing chip; the watchdog circuit comprises a watchdog chip, the control circuit is connected with the watchdog circuit, the control circuit comprises a control chip, and the processing chip is connected with the control circuit. In addition, when the device is in a starting process, the processing chip is used for sending a first enabling signal to the control circuit to control the control chip to keep a closed state, and the control chip controls the watchdog chip to keep the closed state according to the first enabling signal; after the device is started, the processing chip is used for sending a second enabling signal to the control circuit to control the control chip to be opened, and the control chip controls the watchdog chip to be opened according to the second enabling signal to enable the watchdog circuit to be in a working state.
In the watchdog control circuit of the embodiment of the application, the control circuit connected with the watchdog is controlled to be closed through the processing chip, so that the control chip keeps a closed state, and further the watchdog circuit is ensured to be in a closed state, and therefore the watchdog chip does not work in the process that the equipment is started. And after the equipment is started, the processing chip controls the control circuit to be opened so as to start the control chip, and the watchdog chip is started to enable the watchdog circuit to be in a working state. Therefore, the situation that when the system kernel file of the equipment is large, the kernel needs to be decompressed for a longer time, the watchdog circuit outputs a reset signal to restart the equipment, and the equipment cannot be started normally due to circulation.
In some embodiments, the control circuit includes a locking module for locking the watchdog circuit in an operational state.
In some embodiments, the latch module includes a first transistor, a second transistor, and a third transistor, wherein a base of the first transistor is connected to a collector of the second transistor through a first resistor, an emitter of the first transistor is connected to a power source, a collector of the first transistor is connected to ground through a second resistor, a base of the second transistor is connected between the collector of the first transistor and the first resistor through a third resistor, an emitter of the second transistor is connected to ground, a base of the third transistor is connected to the processing chip, an emitter of the third transistor is connected to ground, and a collector of the third transistor is connected to a collector of the second transistor.
In some embodiments, the control circuit includes a fourth resistor having one end connected to the collector of the third transistor and the other end connected to the power supply.
In some embodiments, the control circuit includes a fifth resistor having one end connected to the power supply and the other end connected to the RST pin of the watchdog chip.
In some embodiments, the control circuit includes a first capacitor and a sixth resistor, a first end of the first capacitor is connected to the RST pin of the watchdog chip, a second end of the first capacitor is connected to ground, a first end of the sixth resistor is connected to the base of the third transistor, and a second end of the sixth resistor is connected to ground.
In some embodiments, the Z pin of the control chip is coupled to the WDI pin of the watchdog chip.
In some embodiments, a Y pin of the control chip is electrically connected to the processing chip, the Y pin of the control chip is configured to receive a dog feeding signal of the processing chip, and the control chip is configured to output the dog feeding signal to a watchdog circuit.
In some embodiments, the control circuit includes a locking module, the locking module is configured to lock the watchdog circuit in an operating state, in a case that the watchdog circuit does not receive a dog feeding signal, a RST pin of the watchdog chip outputs a reset signal to reset the processing chip, the reset signal enables the locking module to unlock the watchdog circuit, and the watchdog chip and the control chip are switched from an on state to an off state according to the reset signal.
The application provides a device, the device includes the watchdog control circuit in any one of the above-mentioned embodiments, the watchdog control circuit is used for monitoring the running state of the device.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The above and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a block diagram of a watchdog control circuit in an embodiment of the present application;
FIG. 2 is a schematic circuit diagram of a watchdog control circuit in an embodiment of the present application;
fig. 3 is a schematic plan view of an apparatus in an embodiment of the present application.
Description of the main element symbols:
the device comprises a first transistor Q1, a second transistor Q2, a third transistor Q3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a watchdog control circuit 1000, a watchdog circuit 100, a watchdog chip 11, a control circuit 200, a control chip 21, a lock module 22, a processing chip 300 and a device 2000.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are illustrative and are only for the purpose of explaining the present application and are not to be construed as limiting the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Referring to fig. 1-3, a watchdog control circuit 1000 is provided according to an embodiment of the present disclosure. The watchdog control circuit 1000 includes: a watchdog circuit 100, a control circuit 200 and a processing chip 300; the watchdog circuit 100 includes a watchdog chip 11, the control circuit 200 is connected to the watchdog circuit 100, the control circuit 200 includes a control chip 21, and the processing chip 300 is connected to the control circuit 200.
When the device 2000 is in a starting process, the processing chip 300 is configured to send a first enable signal to the control circuit 200 to control the control chip 21 to keep in a closed state, and the control chip 21 controls the watchdog chip 11 to keep in the closed state according to the first enable signal; after the device 2000 is started, the processing chip 300 is configured to send a second enable signal to the control circuit 200 to control and control the chip 21 to be turned on, and the control chip 21 controls the watchdog chip 11 to be turned on according to the second enable signal to enable the watchdog circuit 100 to be in an operating state.
In the watchdog control circuit 1000 according to the embodiment of the present application, the processing chip 300 controls the control circuit 200 connected to the watchdog to close, so that the control chip 21 keeps a closed state, and further it is ensured that the watchdog circuit 100 is in a closed state, and the watchdog chip 11 does not work during the process of starting the device 2000. Until the device 2000 is started, the processing chip 300 controls the control circuit 200 to open to turn on the control chip 21, and at this time, the watchdog chip 11 is turned on to make the watchdog circuit 100 in an operating state. Thus, it can be avoided that the watchdog circuit 100 outputs a reset signal to restart the device 2000 due to the fact that a longer time is required to decompress the kernel when the system kernel file of the device 2000 is larger, and the device 2000 cannot be normally started due to the circulation.
Specifically, the watchdog circuit 100 is a means for monitoring the operation status of the system, and the monitoring of the operation status of the system can be realized by combining software and hardware. The software running stably in the device 2000 performs a dog feeding operation after executing a specific instruction, and if the watchdog does not receive a dog feeding signal from the software within a certain period, it determines that the system has a fault and enters an interrupt handler or forces the system to reset.
However, in some devices 2000 provided with the watchdog circuit 100, the watchdog chip 11 is powered on, which necessitates the processing chip 300 to issue a watchdog feeding signal within a predetermined time, otherwise the watchdog chip 11 may restart the device 2000. When the system kernel file of the device 2000 is large, a longer time is required for decompressing the kernel, and the time may exceed a predetermined time, so that the watchdog outputs a reset signal to restart the device 2000, and the device 2000 cannot be normally started
In contrast, the present application provides a watchdog control circuit 1000, which enables the watchdog circuit 100 to be turned on and locked in an enabled state as needed, so that the device 2000 with a complex system can also be started normally, and the stability of the operation of the device 2000 is improved.
The device 2000 may be an electronic device 2000 such as a notebook computer, a desktop computer, a tablet computer, or some large-scale industrial device 2000, a breeding device 2000, or the like, as long as the watchdog control circuit 1000 provided in the present application is applied. The watchdog circuit 100 may include a watchdog chip 11, the model of the watchdog chip 11 may be the SGM706, and the timing time is 1.6 s; the control circuit 200 may be connected to the watchdog circuit 100, the control circuit 200 may include a control chip 21, the model of the control chip 21 may be 74LVC1G66GV, and the control chip 21 may control the watchdog chip 11 to be turned on and off.
The processing chip 300 may be connected to the control circuit 200, so that, when the device 2000 includes a complex core, and the device 2000 needs to be started, during a starting process of the device 2000, the processing chip 300 may send a first enable signal to the control circuit 200, where the first enable signal may be a low-level signal, and under an effect of the first enable signal, the control chip 21 keeps a closed state, so that the control chip 21 cannot control the watchdog chip 11 to be opened, and the watchdog circuit 100 does not work during the starting process of the device 2000.
Thus, even if the start time of the device 2000 exceeds the timing time of the watchdog chip 11, the watchdog chip 11 does not send out the reset signal to reset the device 2000 because the watchdog chip 11 is not in the working state.
After the device 2000 is started, the processing chip 300 may be configured to send a second enable signal to the control circuit 200, where the second enable signal may be a high-level signal. Under the action of the second enable signal, the control chip 21 is turned on, so that the control chip 21 can control the watchdog chip 11 to be turned on, and thus after the device 2000 is started, the watchdog circuit 100 starts to work to monitor the running state of the device 2000 in real time.
Referring to fig. 1 and 2, in some embodiments, the control circuit 200 may include a locking module 22, and the locking module 22 may be configured to lock the watchdog circuit 100 in an operating state. Thus, the locking module 22 locks the watchdog circuit 100 in the operating state, so that the watchdog chip 11 is locked in the open state, and the watchdog chip 11 is prevented from being closed in the normal operating process of the device 2000, which results in the failure of monitoring the operation of the device 2000.
Specifically, the locking module 22 may be formed by matching and connecting a plurality of triodes and a plurality of resistors, and the locking module 22 is used to lock the device 2000 in an open state and cannot be closed once the device 2000 is started, so as to avoid that the device 2000 loses monitoring due to abnormal software shutdown of the watchdog circuit 100.
Referring to fig. 2, in some embodiments, the lock module 22 may include a first transistor Q1, a second transistor Q2, and a third transistor Q3. The base of the first transistor Q1 is connected with the collector of the second transistor Q2 through a first resistor R1, the emitter of the first transistor Q1 is connected with a power supply VCC, and the collector of the first transistor Q1 is grounded through a second resistor R2; the base of the second transistor Q2 is connected between the collector of the first transistor Q1 and the first resistor R1 through a third resistor R3, the emitter of the second transistor Q2 is grounded, the base of the third transistor Q3 is connected to the processing chip 300, the emitter of the third transistor Q3 is grounded, and the collector of the third transistor Q3 is connected to the collector of the second transistor Q2.
Specifically, the first transistor Q1 may be a PNP transistor, and the second transistor Q2 and the third transistor Q3 may be NPN transistors. The first transistor Q1, the second transistor Q2, and the third transistor Q3 may each be model S8550. The locking module 22 in the present application may be constructed by a first transistor Q1, a second transistor Q2, and a third transistor Q3 according to the principle of triode self-locking.
In the present embodiment, when the processing chip 300 sends the first enable signal to the control circuit 200, the first transistor Q1 and the second transistor Q2 are turned off by default, and the collector of the second transistor Q2 and the collector of the third transistor Q3 are maintained at a high level. Since the No. 4 pin of the control chip 21 is connected with the pull-down resistor, the No. 4 pin is at a low level, and the watchdog circuit 100 is in an off state. When the processing chip 300 sends the second enable signal to the control circuit 200, that is, outputs a high level, the collector of the second transistor Q2 is changed from a high level to a low level, since the collector of the second transistor Q2 is connected to the base of the first transistor Q1 through the first resistor R1, the base of the first transistor Q1 is pulled low, and in the case that the first transistor Q1 is a PNP-type triode, the emitter of the first transistor Q1 is connected to the power source VCC, and the base of the first transistor Q1 is a low level, so the first transistor Q1 is turned on.
Meanwhile, the collector of the third transistor Q3 is kept at a high level, since the first transistor Q1 is turned on, that is, the watchdog is turned on when the WDT _ SW signal in fig. 2 is at a high level, the base of the second transistor Q2 is pulled to a high level, the emitter of the second transistor Q2 is grounded to a low level, and when the second transistor Q2 is an NPN type triode, the second transistor Q2 is turned on.
Further, since the second transistor Q2 is turned on, the collector of the second transistor Q2 is at a low level, the base of the first transistor Q1 is at a low level, and the first transistor Q1 is turned on; and the base of the second transistor Q2 is high due to the conduction of the first transistor Q1, so that the second transistor Q2 is turned on. That is, the watchdog circuit 100 is state-locked, and the states of the first transistor Q1 and the second transistor Q2 are not changed any more no matter how the enable signal is changed. In this way, the watchdog circuit 100 is prevented from being turned off during normal operation of the device 2000, resulting in failure to monitor the operation of the device 2000.
Referring to fig. 2, in some embodiments, the control circuit 200 may include a fourth resistor R4, one end of the fourth resistor R4 may be connected to the collector of the third transistor Q3, and the other end may be connected to the power source VCC. As such, the fourth resistor R4 may cause the collector of the second transistor Q2 and the collector of the third transistor Q3 to be maintained at a high level so that the first transistor Q1 is maintained in an off state in a case where the second transistor Q2 and the third transistor Q3 are not turned on.
Specifically, the fourth resistor R4 may be a patch resistor, which may be 10K in size. It can be understood that during the start-up process of the device 2000, the watchdog control circuit 1000 needs to keep the off state, that is, the first transistor Q1, the second transistor Q2 and the third transistor Q3 should be in the off state, the first transistor Q1 in this embodiment is a PNP type triode, the second transistor Q2 and the third transistor Q3 are NPN type triodes, and when the processing chip 300 sends the first enable signal to the control circuit 200, since the first enable signal is at low level, the base of the third transistor Q3 is at low level, the third transistor Q3 is in the off state, the base of the second transistor Q2 is also at low level, and the second transistor Q2 is also in the off state.
At this time, the fourth resistor R4 is used as a pull-up resistor, and when the second transistor Q2 and the third transistor Q3 are not turned on, the collector of the second transistor Q2 and the collector of the third transistor Q3 are both kept at a high level by the presence of the fourth resistor R4, so that when the collector of the second transistor Q2 is at a high level, the level of the base of the first transistor Q1 is pulled up, the first transistor Q1 is kept in an off state, and the watchdog circuit 100 is in an off state.
Referring to fig. 2, in some embodiments, the control circuit 200 includes a fifth resistor R5, one end of the fifth resistor R5 is connected to the power source VCC, and the other end is connected to the RST pin of the watchdog chip 11.
Thus, the fifth resistor R5 can keep the RST pin of the watchdog chip 11 at a high level when the RST pin of the watchdog chip 11 does not output a low level, thereby preventing the processing chip 300 from being reset in a normal operating state.
Specifically, it can be understood that the signal output from the RST pin of the watchdog chip 11 (pin No. 7 of the watchdog chip 11) is typically an active low reset control signal, which means that it is desirable that the RST pin of the watchdog chip 11 is kept at a high level and is in an inactive state except for a reset. Then a fifth resistor R5 may be external to the RST pin of the watchdog chip 11 and the fifth resistor R5 may be a pull-up resistor.
One end of the fifth resistor R5 is connected to the VCC power supply, and the other end of the fifth resistor R5 is connected to the RST pin, so that the RST pin of the watchdog chip 11 is kept at a high level when the RST pin of the watchdog chip 11 does not output a low level, thereby preventing the processing chip 300 from being reset in a normal operating state.
Referring to fig. 2, in some embodiments, the control circuit 200 may include a first capacitor C1 and a sixth resistor R6, a first end of the first capacitor C1 may be connected to the RST pin of the watchdog chip 11, a second end of the first capacitor C1 may be grounded, a first end of the sixth resistor R6 may be connected to the base of the third transistor Q3, and a second end of the sixth resistor R6 may be grounded.
In this way, when the processing chip 300 sends the first enable signal to the control circuit 200, the sixth resistor R6 may keep the base of the third transistor Q3 at a low level, that is, the third transistor Q3 may be turned off, and the first capacitor C1 may play a role in resisting interference, so that the operation of the control circuit 200 is more stable.
Specifically, as can be seen from the figure, a first end of the sixth resistor R6 is connected to the base of the third transistor Q3, and a second end of the sixth resistor R6 is grounded, that is, the sixth resistor R6 may be a pull-down resistor. It can be understood that the processing chip 300 does not output a signal before the system is completely started, and the third transistor Q3 may be turned on by mistake due to the existence of a leakage current, so that the watchdog chip 11 is turned on.
Then, when the control circuit 200 is in use, it is desirable that the control circuit 200 should be in an inactive state after being powered on, so as to avoid that the leakage current makes the third transistor Q3 be turned on erroneously and the watchdog chip 11 be turned on erroneously when the processing chip 300 sends the first enable signal to the control circuit 200, that is, WDT _ EN has no signal output. In this way, a sixth resistor R6 may be provided, and in the case that the processing chip 300 has no signal output, the sixth resistor R6 may keep the base of the third transistor Q3 at a low level, that is, the third transistor Q3 is in a turned-off state.
In addition, the RST pin of the watchdog chip 11 may be an asynchronous reset pin, i.e., the RST output low level may reset the processing chip 300.
Referring to fig. 2, in some embodiments, the Z pin of the control chip 21 may be connected to the WDI pin of the watchdog chip 11. As such, the input of the watchdog chip 11 may be input through the Z pin of the control chip 21, such that the control watchdog chip 11 outputs or does not output the reset signal.
Specifically, in the application of the watchdog control circuit 1000, the WDI pin of the watchdog chip 11 (pin 6 of the watchdog chip 11) may be connected to the Z pin of the control chip 21 (pin 2 of the control chip 21), and the input of the watchdog chip 11 is generally referred to as a dog feed. After receiving the dog feeding input, the watchdog chip 11 may zero itself; in the case where the feeding dog input is not received, the watchdog chip 11 gives a reset signal to the processing chip 300 to reset it when time out, thereby preventing a dead halt.
Referring to fig. 2, in some embodiments, the Y pin of the control chip 21 may be electrically connected to the processing chip 300, the Y pin of the control chip 21 may be used for receiving a dog feeding signal of the processing chip 300, and the control chip 21 may be used for outputting the dog feeding signal to the watchdog circuit 100.
In this way, under the condition that the control chip 21 and the watchdog chip 11 are kept in the on state, and the device 2000 is in the normal working state, the watchdog circuit 100 can output the received watchdog feeding signal sent by the processing chip 300 according to the control chip 21, so that the watchdog is cleared, and the device 2000 is prevented from being restarted under the condition that no abnormality occurs to the device 2000.
Specifically, in the application of the watchdog control circuit 1000, the WDI pin of the watchdog chip 11 may be connected to the Z pin of the control chip 21, and the Y pin of the control chip 21 (pin No. 1 of the control chip 21) may be electrically connected to the processing chip 300. Then the input to the watchdog chip 11 may be input by the Z pin of the control chip 21 and the input to the watchdog chip 11 is generally referred to as a feed dog. After receiving the dog feeding input, the watchdog chip 11 may clear itself; in the case where the feeding dog input is not received, the watchdog chip 11 gives a reset signal to the processing chip 300 to reset it when time out, thereby preventing a dead halt.
Therefore, it can be understood that, in a state where the processing chip 300 normally works, the feeding signal may be output at regular intervals, and the feeding signal may be received by the control chip 21 through the Y pin and then input to the WDI pin of the watchdog chip 11 through the Z pin, so that the watchdog chip 11 may receive the feeding signal and clear itself. A restart is avoided which still occurs in a state in which the processor chip is operating normally.
Referring to fig. 2, in some embodiments, the control circuit 200 includes a locking module 22, where the locking module 22 is configured to lock the watchdog circuit 100 in an operating state, and when the watchdog circuit 100 does not receive the dog feeding signal, the RST pin of the watchdog chip 11 outputs a reset signal to reset the processing chip 300, the reset signal enables the locking module 22 to unlock the watchdog circuit 100, and the watchdog chip 11 and the control chip 21 are switched from an active state to a closed state according to the reset signal.
Thus, the watchdog circuit 100 is locked in the working state, and the working state of the device 2000 can be continuously monitored; the RST pin of the watchdog chip 11 outputs a reset signal to reset the processing chip 300, so that the device 2000 is prevented from crashing when the device 2000 is abnormal, meanwhile, the reset signal enables the locking module 22 to unlock the watchdog circuit 100, the watchdog chip 11 and the control chip 21 are switched from the starting state to the closing state according to the reset signal, and the phenomenon that the RST pin of the watchdog chip 11 is triggered by too long starting time of the device 2000 to output the reset signal again, so that the device 2000 cannot be restarted normally all the time is avoided.
Specifically, after the device 2000 starts to be started, the processing chip 300 sends out a first enable signal, and under the action of the first enable signal, the watchdog chip 11 and the control chip 21 are in a closed state. After the device 2000 is started, the processing chip 300 sends out a second enable signal, and the watchdog chip 11 and the control chip 21 are in an open state under the action of the second enable signal. At this time, under the action of the locking module 22 in the control circuit 200, the watchdog circuit 100 is locked in the operating state, and the operating state of the device 2000 is continuously monitored.
Under the monitoring of the watchdog circuit 100, when a program runaway or the like occurs in the device 2000, in order to prevent the device 2000 from crashing, the RST pin of the watchdog chip 11 outputs a reset signal to reset the processing chip 300, and the device 2000 is restarted. At this time, the reset signal enables the latch module 22 to unlock the watchdog circuit 100, and when the latch module 22 includes the first transistor Q1 and the second transistor Q2, the second transistor Q2 is in an off state under the effect of the reset signal, and then the first transistor Q1 is turned off, so that the watchdog chip 11 and the control chip 21 are switched from an on state to an off state according to the reset signal, thereby preventing the RST pin of the watchdog chip 11 from outputting the reset signal again due to the fact that the device 2000 cannot be normally restarted all the time when the device 2000 is activated for an excessively long time.
Referring to fig. 2, in some embodiments, the watchdog chip 11 is further externally connected to a manual enable circuit J1, and after the manual enable circuit J1 is short-circuited, the function of the watchdog chip is turned off, and no reset signal is output, so that it is more convenient to debug the device 2000.
Referring to fig. 3, an embodiment of the present application provides an apparatus 2000, where the apparatus 2000 includes the watchdog control circuit 1000 in any one of the above embodiments, and the watchdog control circuit 1000 is configured to monitor an operation state of the apparatus 2000.
Specifically, the device 2000 may be an electronic device such as a notebook computer, a desktop computer, a tablet computer, a feeder, a feeding monitoring device, or some large-scale industrial devices, breeding devices, or the like, as long as the watchdog control circuit 1000 provided in the present application is applied. Thus, the watchdog circuit 100 can be turned on after the device 2000 is started, so that the watchdog chip 11 is turned on, and the situation that the device 2000 cannot be normally started all the time because the watchdog circuit 100 sends a reset signal to restart the device 2000 due to the fact that the starting time is overtime under the condition that the system of the device 2000 is too complex is avoided. And, the watchdog circuit 100 may be locked after being turned on, so that the watchdog circuit 100 may constantly monitor the operation state of the device 2000, and once the device 2000 is halted, the watchdog control circuit 1000 may restart the device 2000.
In the description herein, references to the description of the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: numerous changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the application, the scope of which is defined by the claims and their equivalents.
Claims (10)
1. A watchdog control circuit, comprising:
the watchdog circuit comprises a watchdog chip;
the control circuit is connected with the watchdog circuit and comprises a control chip;
the processing chip is connected with the control circuit;
when the device is started, the processing chip is used for sending a first enabling signal to the control circuit to control the control chip to keep a closed state, and the control chip controls the watchdog chip to keep the closed state according to the first enabling signal; after the device is started, the processing chip is used for sending a second enabling signal to the control circuit to control the control chip to be opened, and the control chip controls the watchdog chip to be opened according to the second enabling signal to enable the watchdog circuit to be in a working state.
2. The watchdog control circuit of claim 1, wherein the control circuit comprises a locking module to lock the watchdog circuit in an operational state.
3. The watchdog control circuit of claim 2, wherein the locking module comprises a first transistor, a second transistor, and a third transistor, wherein a base of the first transistor is coupled to a collector of the second transistor through a first resistor, an emitter of the first transistor is coupled to a power source, a collector of the first transistor is coupled to ground through a second resistor, a base of the second transistor is coupled between the collector of the first transistor and the first resistor through a third resistor, an emitter of the second transistor is coupled to ground, a base of the third transistor is coupled to the processing die, an emitter of the third transistor is coupled to ground, and a collector of the third transistor is coupled to a collector of the second transistor.
4. The watchdog control circuit of claim 3, wherein the control circuit comprises a fourth resistor having one end coupled to a collector of the third transistor and another end coupled to the power source.
5. The watchdog control circuit of claim 3, wherein the control circuit comprises a fifth resistor having one end connected to the power supply and another end connected to a RST pin of the watchdog chip.
6. The watchdog control circuit of claim 3, wherein the control circuit comprises a first capacitor and a sixth resistor, a first terminal of the first capacitor is connected to the RST pin of the watchdog chip, a second terminal of the first capacitor is connected to ground, a first terminal of the sixth resistor is connected to the base of the third transistor, and a second terminal of the sixth resistor is connected to ground.
7. The watchdog control circuit of claim 1, wherein a Z pin of the control chip is coupled with a WDI pin of the watchdog chip.
8. The watchdog control circuit of claim 1, wherein a Y pin of the control chip is electrically connected to the processing chip, the Y pin of the control chip is configured to receive a dog feeding signal of the processing chip, and the control chip is configured to output the dog feeding signal to the watchdog circuit.
9. The watchdog control circuit according to claim 1, wherein the control circuit comprises a locking module, the locking module is configured to lock the watchdog circuit in an operating state, in a case that the watchdog circuit does not receive a watchdog feeding signal, the RST pin of the watchdog chip outputs a reset signal to reset the processing chip, the reset signal enables the locking module to unlock the watchdog circuit, and the watchdog chip and the control chip are switched from an active state to a closed state according to the reset signal.
10. An apparatus comprising a watchdog control circuit according to any one of claims 1 to 9, the watchdog control circuit being configured to monitor an operational state of the apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210126288.1A CN114610514A (en) | 2022-02-10 | 2022-02-10 | Watchdog control circuit and equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210126288.1A CN114610514A (en) | 2022-02-10 | 2022-02-10 | Watchdog control circuit and equipment |
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| CN114610514A true CN114610514A (en) | 2022-06-10 |
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| CN202210126288.1A Pending CN114610514A (en) | 2022-02-10 | 2022-02-10 | Watchdog control circuit and equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117093403A (en) * | 2023-10-16 | 2023-11-21 | 北京茵沃汽车科技有限公司 | Watchdog control circuit, control method thereof and electronic equipment |
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- 2022-02-10 CN CN202210126288.1A patent/CN114610514A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117093403A (en) * | 2023-10-16 | 2023-11-21 | 北京茵沃汽车科技有限公司 | Watchdog control circuit, control method thereof and electronic equipment |
| CN117093403B (en) * | 2023-10-16 | 2024-01-26 | 北京茵沃汽车科技有限公司 | Watchdog control circuit, control method thereof and electronic equipment |
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