CN213634462U

CN213634462U - Watchdog circuit

Info

Publication number: CN213634462U
Application number: CN202022471526.1U
Authority: CN
Inventors: 王静; 陈建业
Original assignee: Beijing Hanzhixing Technology Co ltd
Current assignee: Beijing Hanzhixing Technology Co ltd
Priority date: 2020-10-30
Filing date: 2020-10-30
Publication date: 2021-07-06
Anticipated expiration: 2030-10-30

Abstract

The utility model discloses a watchdog circuit, which comprises an MCU (microprogrammed control unit) and a peripheral circuit connected with the MCU, wherein a pin 2, a pin 3, a pin 8 and a pin 12 of the MCU are used as signal input pins, a pin 1 and a pin 4 of the MCU are used as signal output pins, and the pin 4 of the MCU is connected with the first peripheral circuit; a second peripheral circuit is connected between the pin 15 and the pin 9 of the MCU; a pin 10 of the MCU is connected with a third peripheral circuit; and a pin 11 of the MCU micro-control unit is connected with a fourth peripheral circuit. The utility model discloses a whether the MCU control hardware is opened successfully with the relevant foot position state of start to intervene when judging the start is unsuccessful and handle and let the system restart until successful, improved the successful degree of reliability of system start.

Description

Watchdog circuit

Technical Field

The utility model relates to a circuit structure, concretely relates to watchdog circuit.

Background

In some specific technical fields, it is necessary to monitor the boot process of a system, such as a CPU, so as to intervene in processing in time when the system is abnormally booted. Although there are many devices and apparatuses capable of monitoring the system startup process in the prior art, most of them have complex internal circuit structures, and are not highly reliable in the monitoring system startup process, and are prone to have startup state judgment errors. And, when the abnormal starting of the system is monitored, the active intervention processing can not be carried out so as to ensure the successful starting of the system.

SUMMERY OF THE UTILITY MODEL

The utility model discloses use control hardware start process, improve the successful reliability of system's start as the purpose, provide a watchdog circuit.

To achieve the purpose, the utility model adopts the following technical proposal:

the watchdog circuit comprises an MCU (microprogrammed control unit) and a peripheral circuit connected with the MCU, wherein a pin (2), a pin (3), a pin (8) and a pin (12) of the MCU are used as signal input pins of the MCU, a pin (1) and a pin (4) of the MCU are used as signal output pins of the MCU, the pin (4) of the MCU is connected with a first peripheral circuit, and a pin (5), a pin (6) and a pin (7) of the MCU are suspended;

a second peripheral circuit is connected between a pin (15) and a pin (9) of the MCU, a pin (16) of the MCU is in short circuit with the pin (15), and a pin (13) and a pin (14) of the MCU are grounded;

a pin (10) of the MCU is connected with a third peripheral circuit; and a pin (11) of the MCU is connected with a fourth peripheral circuit.

As a preferable solution of the present invention, the peripheral circuit includes the first peripheral circuit, the second peripheral circuit, the third peripheral circuit and the fourth peripheral circuit, the first peripheral circuit includes a logic device U8, a capacitor C51 and a resistor R58, and a pin (4) of the MCU micro control unit is connected to a pin (2) of the logic device U8; a pin (1) of the logic device U8 is suspended, a pin (3) is grounded, a pin (4) is connected with an external auxiliary power supply after being connected with the resistor R58, and a pin (5) is connected with the external auxiliary power supply and is grounded after being connected with the capacitor C51.

As a preferred scheme of the present invention, the second peripheral circuit includes a capacitor C88, a capacitor C95 and a resistor R38, one end of the capacitor C88 is grounded, and the other end is connected to a pin (15) of the MCU micro-control unit; one end of the capacitor C95 is grounded, and the other end of the capacitor C95 is connected with a pin (9) of the MCU; one end of the resistor R38 is connected with a pin (15) of the MCU, and the other end of the resistor R38 is connected with a pin (9) of the MCU; and a pin (15) of the MCU is externally connected with an auxiliary power supply.

As an optimized scheme of the utility model, third peripheral circuit includes connecting piece JP8, connecting piece JP 8's pin (1) external auxiliary power supply, pin (2) are connected pin (10), pin (3) of the little the control unit of MCU pin (9), pin (4) ground connection.

As a preferable scheme of the present invention, the fourth peripheral circuit includes a connection part JP9 and a resistor R48, and a pin (1) of the connection part JP9 is connected to the resistor R48 and then externally connected to an auxiliary power supply; pin (2) of the connector JP9 is connected with pin (11) of the MCU micro control unit, and pin (3) of the connector JP9 is grounded.

As a preferred scheme of the present invention, the model of the MCU micro control unit is MSP430G2231IRSA 16R.

As a preferred embodiment of the present invention, the model number of the logic device U8 is SN74LVC1G07 DBVR.

As a preferred scheme of the utility model, auxiliary power supply's supply voltage is 3V.

The utility model discloses a whether the MCU control hardware is opened successfully with the relevant foot position state of start to intervene when judging the start is unsuccessful and handle and let the system restart until successful, improved the successful degree of reliability of system start.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be obtained from these drawings without inventive effort.

Fig. 1 is a schematic circuit diagram of a watchdog circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram of signals input to the MCU or output from the MCU after the system is normally powered on and successfully powered on;

FIG. 3 is a timing diagram of signals input to or output from the MCU when the system is not successfully powered on.

Detailed Description

The technical solution of the present invention is further explained by the following embodiments with reference to the accompanying drawings.

Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; for a better understanding of the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.

The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not indicated or implied that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are used only for illustrative purposes and are not to be construed as limiting the present patent, and the specific meaning of the terms will be understood by those skilled in the art according to the specific circumstances.

In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being either a fixed connection, a detachable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

As shown in fig. 1, the utility model discloses a watchdog circuit that embodiment provided, including MCU microcontrol unit 100 (preferred model is MSP430G2231IRSA 16R) and the peripheral circuit of connecting MCU microcontrol unit 100, MCU microcontrol unit's pin 2, pin 3, pin 8 and pin 12 are as MCU microcontrol unit's signal input pin, MCU microcontrol unit's pin 1 and pin 4 are as MCU microcontrol unit's signal output pin, MCU microcontrol unit's pin 4 connects first peripheral circuit, MCU microcontrol unit's pin 5, pin 6 and pin 7 are unsettled;

a second peripheral circuit is connected between a pin 15 and a pin 9 of the MCU, a pin 16 of the MCU is in short circuit with the pin 15, and a pin 13 and a pin 14 of the MCU are grounded;

a pin 10 of the MCU is connected with a third peripheral circuit; and a pin 11 of the MCU micro-control unit is connected with a fourth peripheral circuit.

As shown in fig. 1, the peripheral circuits include a first peripheral circuit, a second peripheral circuit, a third peripheral circuit and a fourth peripheral circuit, the first peripheral circuit includes a logic device U8 (preferably model number SN74LVC1G07 DBVR), a capacitor C51 and a resistor R58, and pin 4 of the MCU micro-control unit is connected to pin 2 of the logic device U8; pin 1 of the logic device U8 is floating, pin 3 is grounded, pin 4 is connected to the resistor R58 and then externally connected to the auxiliary power supply, and pin 5 is connected to the capacitor C51 and then grounded.

As shown in fig. 1, the second peripheral circuit includes a capacitor C88, a capacitor C95 and a resistor R38, one end of the capacitor C88 is grounded, and the other end is connected to a pin 15 of the MCU; one end of the capacitor C95 is grounded, and the other end of the capacitor C95 is connected with a pin 9 of the MCU; one end of the resistor R38 is connected with a pin 15 of the MCU, and the other end is connected with a pin 9 of the MCU; and a pin 15 of the MCU micro-control unit is externally connected with an auxiliary power supply.

As shown in fig. 1, the third peripheral circuit includes a connector JP8, pin 1 of the connector JP8 is externally connected with an auxiliary power supply, pin 2 is connected with pin 10 of the MCU, pin 3 is connected with pin 9 of the MCU, and pin 4 is grounded.

As shown in fig. 1, the fourth peripheral circuit includes a connector JP9 and a resistor R48, and a pin 1 of the connector JP9 is connected to the resistor R48 and then externally connected to an auxiliary power supply; pin 2 of the connector JP9 is connected to pin 11 of the MCU, and pin 3 of the connector JP9 is grounded. The device connected to connection JP9 is used to provide mode selection for hardware boot process monitoring.

In the above technical solution, the supply voltage of the auxiliary power supply is preferably 3V.

It is following right the utility model provides a watchdog circuit control hardware start process's principle is briefly expounded:

ATXBT #, SLP _ S4#, SLP _ S3#, PLTRST _3p3# in fig. 1 are input signals respectively input into the MCU through

pins

12, 2, 8 and 3 of the MCU, wherein ATXTB # is a signal for a user to press a key, and the 3 sets of signals SLP _ S4#, SLP _ S3#, PLTRST _3p3# are provided from the CPU to the MCU for determining the current power-on state of the CPU according to the 3 sets of signals, so as to intervene in the process in time according to the determined power-on state. The operation principle of the watchdog circuit is described below with a timing chart:

fig. 2 shows a timing chart of signals input to or output from the MCU after the CPU is normally powered on and successfully powered on. As can be seen from FIG. 2, when PLTRST _3P3# changes from low level to high level, it indicates that the CPU is successfully powered on.

Fig. 3 shows a timing chart of signals input to or output from the MCU when the CPU is not successfully powered on. As shown in fig. 3, when the signal PLTRST _3P3# input to the MCU is still at the high level about 1 second after the signal COREPWROK output by the MCU goes high, the signal PWRBTN _ OUT # output by the MCU will be at the low level for more than 5 seconds to force the system to shut down, when the signal SLP _ S4# input to the MCU goes high, it indicates that the system has shut down, and then the signal PWRBTN _ OUT # goes high for a short period of time before sending a power-on signal until the system is successfully powered on.

It should be understood that the above-described embodiments are merely illustrative of the preferred embodiments of the present invention and the technical principles thereof. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, these modifications are within the scope of the present invention as long as they do not depart from the spirit of the present invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.

Claims

1. A watchdog circuit is characterized by comprising an MCU (microprogrammed control Unit) and a peripheral circuit connected with the MCU, wherein a pin 2, a pin 3, a pin 8 and a pin 12 of the MCU are used as signal input pins of the MCU, a pin 1 and a pin 4 of the MCU are used as signal output pins of the MCU, a pin 4 of the MCU is connected with a first peripheral circuit, and a pin 5, a pin 6 and a pin 7 of the MCU are suspended;

a pin 10 of the MCU is connected with a third peripheral circuit; and a pin 11 of the MCU micro control unit is connected with a fourth peripheral circuit.

2. The watchdog circuit of claim 1, wherein the peripheral circuits include the first peripheral circuit, the second peripheral circuit, the third peripheral circuit, and the fourth peripheral circuit, the first peripheral circuit includes a logic device U8, a capacitor C51, and a resistor R58, pin 4 of the MCU micro-control unit is connected to pin 2 of the logic device U8; pin 1 of the logic device U8 is suspended, pin 3 is grounded, pin 4 is connected with an external auxiliary power supply after being connected with the resistor R58, and pin 5 is connected with the external auxiliary power supply and is grounded after being connected with the capacitor C51.

3. A watchdog circuit according to claim 1, wherein the second peripheral circuit comprises a capacitor C88, a capacitor C95 and a resistor R38, one end of the capacitor C88 is connected to ground, and the other end is connected to pin 15 of the MCU; one end of the capacitor C95 is grounded, and the other end of the capacitor C95 is connected with a pin 9 of the MCU; one end of the resistor R38 is connected with a pin 15 of the MCU, and the other end of the resistor R38 is connected with a pin 9 of the MCU; and a pin 15 of the MCU micro control unit is externally connected with an auxiliary power supply.

4. The watchdog circuit of claim 1, wherein the third peripheral circuit comprises a connector JP8, pin 1 of the connector JP8 is externally connected to an auxiliary power supply, pin 2 is connected to pin 10 of the MCU, pin 3 is connected to pin 9 of the MCU, and pin 4 is grounded.

5. The watchdog circuit of claim 1, wherein the fourth peripheral circuit comprises a connector JP9 and a resistor R48, and pin 1 of the connector JP9 is connected to the resistor R48 and then externally connected to an auxiliary power supply; pin 2 of the connector JP9 is connected to pin 11 of the MCU, and pin 3 of the connector JP9 is grounded.

6. The watchdog circuit of claim 1, wherein the MCU microcontrol unit is model MSP430G2231IRSA 16R.

7. The watchdog circuit of claim 2, wherein the logic device U8 is model SN74LVC1G07 DBVR.

8. A watchdog circuit according to any one of claims 2-5, wherein the auxiliary power supply has a supply voltage of 3V.