TW202238382A - Mainboard, external device of mainboard, and booting method of mainboard - Google Patents

Abstract

A mainboard is provided. The mainboard includes a controller, a first switch element and a basic input/output system. The first switch element is configured to pull a first pin of the controller to a first voltage level when it is turned on. The controller detects whether the first pin is at the first voltage level to enter a boot failure rescue mode. In the boot failure rescue mode, the controller causes the basic input/output system to reduce the signal transmission rate corresponding to a signal channel to perform the boot action.

Description

Main board, external device of main board and method for starting the main board

The present invention relates to a motherboard, and in particular to a solution for eliminating the failure of the motherboard to start normally.

The Basic Input/Output System (BIOS) is the firmware used by the computer to perform hardware initialization and provide runtime services for the operating system during the power-on phase of the computer. The setting value of the BIOS program and the detection value of hardware parameters are stored in a random access memory (Random Access Memory, RAM) commonly known as CMOS.

When starting the computer through the BIOS program, the information in the CMOS needs to be loaded. Generally speaking, if the BIOS parameter settings are wrong or overclocking fails, you can start the system by clearing the CMOS settings and loading the system defaults. Alternatively, the system can be booted by manually pressing a specific key on the motherboard to forcibly enter the BIOS interface and load the system default values. However, in the case of high-speed devices (such as graphics cards, storage devices, etc.) or compatibility issues with the signal transmission rate of the bus, even if the default value is loaded and the system is in the default state, it will still fail to boot. situation. This inability to power on will result in poor user experience and increase product return rates.

Therefore, it is necessary to propose a technical solution to solve the aforementioned problem of not being able to boot.

The invention provides a mainboard, an external device of the mainboard, and a booting method of the mainboard, so as to solve the situation that the mainboard cannot be started due to the compatibility of signal transmission rates between internal devices of the mainboard.

The motherboard of the present invention includes a controller, a first switch element and a basic input and output system. The first switch element is used for pulling the first pin of the controller to a first voltage level when turned on. The controller detects whether the first pin is at the first voltage level to enter the boot failure rescue mode. In the boot failure rescue mode, the controller makes the basic input and output system lower the signal transmission rate corresponding to a signal channel to execute the boot action.

The external device of the main board of the present invention is used for external connection to the aforementioned main board. The external device includes a second switch element. The second switch element is coupled to the first switch element, and is used for pulling the first pin to a first voltage level through the first switch element when turned on.

The booting method of the main board of the present invention includes: the controller of the main board detects whether the first pin of the main board is at the first voltage level to enter the boot failure rescue mode; and in the boot failure rescue mode, the controller makes the basic The I/O system lowers the signal transmission rate corresponding to a signal channel to perform a power-on action.

Based on the above, the present invention lowers the signal transmission rate corresponding to a signal channel by performing the power-on failure rescue mode. In this way, it is possible to eliminate the situation that the system cannot be turned on due to the compatibility problem of the signal transmission rate.

FIG. 1 is a schematic structural diagram of a motherboard according to a first embodiment of the present invention. Please refer to FIG. 1 , the motherboard 100 is composed of components such as a controller 120 , a Basic Input/Output System (BIOS) 130 , and a first switch element 140 carried by a substrate 110 . In this embodiment, the controller 120 may be a central processing unit (Central Processing Unit, CPU). The controller 120 has a first pin (pin) 121 . The first pin 121 may be a general-purpose input/output (GPIO) pin of the CPU chip, but the present invention is not limited thereto.

The first switch element 140 may be any suitable switch element or connector, such as a pin header. The first switch element 140 can be disposed anywhere on the substrate 110 and one end of the first switch element 140 is coupled to the first pin 121 . In an embodiment, the other terminal of the first switching element 140 may be coupled to a reference voltage terminal. When the first switch element 140 is turned on (for example, by shorting the pins of the pin header), the first pin 121 of the controller 120 is pulled up to a voltage level corresponding to the aforementioned reference voltage terminal. When the controller 120 detects that its first pin 121 is at a high voltage level, it enters into a boot failure rescue mode. In practical application, when the user finds that the boot cannot be started normally, the first switch element 140 of the motherboard 100 can be manually turned on to enter the boot failure rescue mode.

The BIOS 130 is a firmware that performs hardware initialization and provides runtime services for the operating system when the host is powered on (ie, booting). The BIOS 130 is stored in a memory device (ROM chip or flash memory chip). In the boot failure rescue mode, the controller 120 enables the BIOS 130 to adjust a signal transmission rate corresponding to a signal channel to perform a boot action. In this embodiment, the signal channel is, for example, a signal channel conforming to the PCIe (short for PCI Express) standard. Currently, high-speed devices in the host (such as display cards, storage devices, etc.) and at least part of the bus (such as extension cables inside the host) all conform to the PCIe specification. In terms of implementation details, the storage circuit of the BIOS 130 may pre-store the first storage information corresponding to the first preset rate. When entering the boot failure rescue mode, the BIOS 130 can perform signal transmission at a first preset rate according to the first stored information.

The first preset rate may be a signal transmission rate that can ensure successful booting and is obtained after an actual test before the product is shipped. In an embodiment, the first predetermined rate may be a signal transmission rate conforming to PCIe version 3.0. However, the present invention is not limited thereto. In other embodiments, the first preset rate may also be a signal transmission rate corresponding to other PCIe versions, such as PCIe version 4.0, PCIe version 5.0 or PCIe version 2.0. Generally speaking, the first preset rate usually corresponds to an older PCIe version.

Instead of directly reducing the signal transmission rate to the first preset rate, in another embodiment, the BIOS 130 can also reduce the signal transmission rate in stages in the boot failure rescue mode. For example, in the boot failure rescue mode, the BIOS 130 may first reduce the current signal transmission rate from corresponding to PCIe 4.0 version to corresponding to PCIe 3.0 version. Moreover, when it is confirmed that the booting operation still fails at the signal transmission rate corresponding to PCIe 3.0 version, the BIOS 130 may further reduce the signal transmission rate from corresponding to PCIe 3.0 version to corresponding to PCIe 2.0 version. To put it simply, when it is confirmed that the system still cannot be turned on, the BIOS 130 may sequentially reduce the signal transmission rate.

By reducing the current signal transmission rate (either directly to the first preset rate or sequentially reducing the signal transmission rate), there is a high probability that the signal transmission rate caused by high-speed devices (such as graphics cards, storage devices, etc.) or buses can be ruled out. Inability to boot due to compatibility issues. Therefore, the user can boot normally by executing the boot failure rescue mode. In addition, compared to the existing method of clearing the CMOS settings (the boot codes stored in the BIOS 130 will all be restored to the system default values), the present invention can maintain the current CMOS setting values (that is, previously generated and stored by a user setting) a boot code in BIOS 130). In this way, the user can make individual changes to the setting values in the previous setting values that may cause the failure to boot through the BIOS interface after the normal boot, without readjusting all the setting values.

The booting action includes executing at least one booting test program by the controller 120 . Moreover, the controller 120 judges whether the execution of the booting action is successful by reading at least one response signal generated corresponding to the at least one booting test program within a preset time interval after the at least one booting test program is executed. Specifically, the timing mechanism of a watch dog timer set in the BIOS 130 can be used to check whether the response signal generated by the corresponding power-on test program is valid and sent back within a preset time interval. If the judgment result is yes, it means that the booting action is successful. On the contrary, if the determination result is negative, it means that the booting operation fails.

FIG. 2 is a schematic structural diagram of a motherboard according to a second embodiment of the present invention. The second embodiment shown in FIG. 2 is an extension of the first embodiment shown in FIG. 1 . The function and coupling relationship of the motherboard 100, the substrate 110, the controller 120, the first pin 121, the BIOS 130, and the first switching element 140 shown in FIG. description and will not be repeated here. Please refer to FIG. 2 , the difference between the second embodiment and the first embodiment is that an external device 200 is added in the second embodiment. The external device 200 may be a controller. The second switch element 210 in the external device 200 is coupled to the first switch element 140 by wire. The second switch element 210 can be turned on by operating the external device 200 . Similarly, the second switching element 210 may be any suitable form of switching element or connector. When the second switch element 210 is turned on, the first switch element 140 is jointly turned on, so as to pull the first pin 121 to a first voltage level (eg, a high voltage level) and enter the boot failure rescue mode.

Under the framework of the first embodiment, the user needs to open the case to turn on the first switch element 140 . However, under the framework of the second embodiment, the user can enter the boot failure rescue mode only by operating the external device 200 . FIG. 3 is a schematic diagram showing the appearance of the external device of the second embodiment. Please refer to FIG. 3 , the external device 300 includes a key set 310 and a screen 320 . In this embodiment, the user can respectively perform frequency reduction and frequency increase operations through the buttons 311 and 312 . In addition, the user can perform shutdown and startup operations respectively through the button 313 and the button 314 . Through the button 315, the restart operation can be performed under the overclocking setting value. The operation of clearing the CMOS settings can be performed through the key 316 . The function of the button 317 is the focus of the second embodiment. Through the button 317, the second switch element 317 can be turned on to enter the boot failure rescue mode.

The screen 320 of the external device 300 is used to display various codes. For example, when "00" is displayed, it means that the motherboard cannot detect CPU or CPU abnormality. When the code "D6" is displayed, it means that the display card output is abnormal. When the code "55" is displayed, it means that the BIOS cannot detect the memory or the memory is abnormal. In a usage scenario, when the code “D6” appears, the user can press the button 317 to enter the “boot failure rescue mode”. In this way, the failure to boot due to incompatible signal rates of high-speed devices (such as display cards, DRAMs) or cables can be eliminated by executing the boot failure rescue mode. After booting normally, the user can individually adjust the setting values that may affect the normal operation of the system through the BIOS interface.

FIG. 4 is a flow chart showing the steps of the booting method of the motherboard of the present invention. It should be noted that the booting method of the motherboard shown in FIG. 4 can be applied to the first embodiment shown in FIG. 1 and the second embodiment shown in FIG. 2 at the same time. Please refer to FIG. 1, FIG. 2 and FIG. 4 at the same time. In step S410, the controller 120 detects whether the first pin 121 of the controller 120 is at the first voltage level (such as a high voltage level) to enter the power-on failure rescue. model. In step S420 , in the boot failure rescue mode, the controller 120 causes the BIOS 130 to reduce the signal transmission rate corresponding to a signal channel to perform a boot action.

To sum up, the present invention provides a solution for the failure to boot. By detecting the voltage level of the first pin of the controller to enter the boot failure rescue mode. Moreover, under this mode, the BIOS is made to adjust the signal transmission rate, so as to eliminate the situation that the computer cannot be turned on due to the compatibility problem of the signal transmission rate. In this way, user experience can be improved and product returns caused by failure to boot can be reduced.

100: Motherboard 110: Substrate 120: Controller 121: The first pin 130: Basic Input Output System 140: the first switching element 200: external device 210: second switching element 300: external device 310: button group 311~317: button 320: screen S410, S420: steps

FIG. 1 is a schematic structural diagram of a motherboard according to a first embodiment of the present invention. FIG. 2 is a schematic structural diagram of a motherboard according to a second embodiment of the present invention. FIG. 3 is a schematic diagram showing the appearance of the external device of the second embodiment. FIG. 4 is a flow chart showing the steps of the booting method of the motherboard of the present invention.

S410, S420: steps

Claims (15)

A motherboard, comprising: a controller with a first pin; a first switch element, used to pull the first pin to a first voltage level when turned on; and A basic input and output system (Basic Input/Output System, BIOS), Wherein, the controller detects whether the first pin is at the first voltage level to enter a power-on failure rescue mode, Wherein, in the boot failure rescue mode, the controller causes the BIOS to lower a signal transmission rate corresponding to a signal channel to perform a boot action. The motherboard as claimed in claim 1, wherein the BIOS is further configured to reduce the signal transmission rate to a first preset rate in the boot failure rescue mode. The motherboard as claimed in item 2, wherein the basic input output system is further used to further reduce the signal transmission rate to a second preset rate to execute the booting action again when the booting action fails, wherein The second preset rate is less than the first preset rate. The motherboard according to claim 1, wherein in the boot failure rescue mode, the BIOS retains a boot code generated through a user setting. The motherboard as described in claim 1, wherein the controller is also used to execute at least one boot test program, and read the corresponding at least one boot test program in a preset time interval after the at least one boot test program is executed At least one response signal generated by the testing program is used to determine whether the booting action is executed successfully. The motherboard according to claim 1, wherein the first pin is a general-purpose input/output (GPIO) pin of the controller. An external device for a motherboard, used for external connection to the motherboard as described in claim 1, wherein the external device includes: A second switch element, coupled to the first switch element, is used for pulling the first pin to the first voltage level through the first switch element when turned on. A booting method of a mainboard, wherein the mainboard includes a controller and a basic input output system, and the booting method includes: The controller detects whether a first pin of the controller is at the first voltage level to enter a power-on failure rescue mode; and In the boot failure rescue mode, the controller causes the BIOS to lower a signal transmission rate corresponding to a signal channel to perform a boot action. The booting method of the main board as described in claim item 8, wherein the step of making the basic input and output system adjust the signal transmission rate by the controller further includes: making the BIOS reduce the signal transmission rate to a first preset rate. The booting method of the motherboard as described in request item 9, also includes: When the controller confirms that the boot action fails, the basic input output system further reduces the signal transmission rate to a second preset rate to execute the boot action again, Wherein, the second preset rate is smaller than the first preset rate. The method for booting a motherboard as described in claim 8, wherein in the boot failure rescue mode, the BIOS retains a boot code generated by a user setting. The booting method of the motherboard as described in request item 8, also includes: The controller executes at least one power-on test program, and within a preset time interval after the at least one power-on test program is executed, by reading at least one response signal generated corresponding to the at least one power-on test program, it is determined whether to restart Whether the boot action is executed successfully. The booting method of the motherboard as claimed in claim 8, wherein the first pin is a general-purpose input and output pin of the controller. The booting method of the main board as claimed in claim 8, wherein the main board further includes a first switch element for pulling the first pin to the first voltage level when turned on. The booting method of the motherboard as described in claim 14, wherein the motherboard is also coupled to an external device, and the external device includes a second switch element, which is used to pass the first switch element to the first switch element when it is turned on. The pin is pulled to the first voltage level.

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