CN117093403B - Watchdog control circuit, control method thereof and electronic equipment - Google Patents
Watchdog control circuit, control method thereof and electronic equipment Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0736—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function
- G06F11/0739—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function in a data processing system embedded in automotive or aircraft systems
Abstract
The application provides a watchdog control circuit, a control method thereof and electronic equipment, and relates to the technical field of electronic circuits. The watchdog control circuit includes: the delay circuit comprises an output end; a logic gate circuit including an enable pin and an output; the watchdog chip is respectively connected with the logic gate circuit and the system chip; the output end of the delay circuit is connected with an enabling pin of the logic gate circuit, the output end of the logic gate circuit is connected with an enabling pin of the first power supply module, and the first power supply module is connected with the system chip; the delay circuit is configured to provide a first electrical signal to the logic gate circuit after the power management integrated circuit is in a secure state; the logic gate circuit is configured to output a blocking signal under control of the first electrical signal so as to isolate the output signal of the watchdog chip from the first power supply module by the blocking signal, such that the first power supply module is not affected by the output signal of the watchdog chip during the isolation.
Description
Technical Field
The application relates to the technical field of electronic circuits, in particular to a watchdog control circuit, a control method thereof and electronic equipment.
Background
During the starting process or operation of the whole system, if the whole system is subjected to strong electromagnetic interference or power supply load rejection, the MCU (Microprogrammed Control Unit, microcontroller) may work abnormally, so that the whole system cannot work. To address this problem, a watchdog module is typically integrated in the power management integrated circuit.
The power management integrated circuit generally has a residual voltage detection function and a low voltage detection function, and when a plurality of low voltage conditions or residual voltage conditions occur continuously, the power management integrated circuit can enter a safe mode, and at the moment, the power management integrated circuit can not output power to the main chip, and the built-in watchdog chip cannot be used. To disable the power management integrated circuit, the entire system is typically powered down and restarted. When the power is turned off and restarted, the watchdog chip is generally added to power off and restart the primary power supply, however, the power-on reset time of the watchdog chip cannot be completely decoupled from the starting time of the whole system.
Disclosure of Invention
The present application has been made in order to solve the above technical problems. The embodiment of the application provides a watchdog control circuit, a control method thereof and electronic equipment.
In a first aspect, an embodiment of the present application provides a watchdog control circuit, including: the delay circuit comprises an output end; a logic gate circuit including an enable pin and an output; the watchdog chip is respectively connected with the logic gate circuit and the system chip; the output end of the delay circuit is connected with an enabling pin of the logic gate circuit, the output end of the logic gate circuit is connected with an enabling pin of the first power supply module, and the first power supply module is connected with the system chip; the delay circuit is configured to provide a first electrical signal to the logic gate circuit after the power management integrated circuit is in a secure state; the logic gate circuit is configured to output a blocking signal under control of the first electrical signal so as to isolate the output signal of the watchdog chip from the first power supply module by the blocking signal, such that the first power supply module is not affected by the output signal of the watchdog chip during the isolation.
With reference to the first aspect, in certain implementations of the first aspect, the watchdog chip is configured to control the first power module to stop supplying power after the power management integrated circuit is in a secure state.
With reference to the first aspect, in certain implementations of the first aspect, the watchdog chip is further configured to perform a power-on reset procedure after controlling the first power module to stop supplying power, wherein a duration of the first electrical signal is greater than or equal to a duration of the watchdog chip performing the power-on reset procedure.
With reference to the first aspect, in certain implementations of the first aspect, the watchdog chip outputs a low-level signal when performing a power-on reset procedure.
With reference to the first aspect, in certain implementations of the first aspect, the delay circuit is further configured to provide the logic gate with the second electrical signal after the first electrical signal output ends; wherein the logic gate circuit is further configured to maintain the high-low level output state after receiving the second electrical signal, and the watchdog chip is further configured to control an operation state of the system chip through the logic gate circuit.
With reference to the first aspect, in certain implementations of the first aspect, the watchdog chip is further configured to control an operational state of the system chip by a logic gate circuit, including: the watchdog chip is further configured to provide a high-level signal to the logic gate circuit after the power-on reset is finished, so that the logic gate circuit inputs the high-level signal to the first power module, the first power module enters a working state under the action of the high-level signal, and the system chip starts after the first power module enters the working state.
With reference to the first aspect, in certain implementations of the first aspect, the second electrical signal includes a low level signal.
With reference to the first aspect, in certain implementations of the first aspect, the delay circuit, the watchdog chip and the logic gate circuit are powered by the second power supply module.
With reference to the first aspect, in certain implementations of the first aspect, the delay circuit includes a reset chip, and the first electrical signal includes a high level signal.
With reference to the first aspect, in certain implementations of the first aspect, the logic gate includes a tri-state buffer.
In a second aspect, an embodiment of the present application provides a watchdog control method, applied to a watchdog control circuit, where the watchdog control circuit includes: the delay circuit comprises an output end; a logic gate circuit including an enable pin and an output; the watchdog chip is respectively connected with the logic gate circuit and the system chip; the output end of the delay circuit is connected with the enabling pin of the logic gate circuit, the output end of the logic gate circuit is connected with the enabling pin of the first power supply module, and the first power supply module is connected with the system chip. The watchdog control method comprises the following steps: after the power management integrated circuit is in a safe state, the control delay circuit provides a first electric signal for the logic gate circuit; under the control of a first electric signal, the control logic gate circuit outputs a blocking signal; the output signal of the watchdog chip is isolated from the first power supply module based on the blocking signal, such that the first power supply module is not affected by the output signal of the watchdog chip during the isolation.
In a third aspect, an embodiment of the present application provides an electronic device, which includes the watchdog control circuit according to the first aspect.
In the embodiment of the application, when the power management integrated circuit is in a state that the delay circuit and the logic gate circuit are added in the watchdog control circuit, the watchdog chip outputs the blocking signal when the logic gate circuit receives the first electric signal, and the isolation between the output signal of the watchdog chip and the enabling pin of the first power module is realized, so that the first power module is not influenced by the output signal of the watchdog chip during the isolation period, and the time of executing the power-on reset process of the watchdog chip is isolated from the starting time of the system chip during the power-on reset.
Drawings
The foregoing and other objects, features and advantages of the present application will become more apparent from the following more particular description of embodiments of the present application, as illustrated in the accompanying drawings. The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate the application and not constitute a limitation to the application. In the drawings, like reference numerals generally refer to like parts or steps.
Fig. 1 is a schematic diagram of a watchdog control circuit according to an exemplary embodiment of the present application.
Fig. 2 is a schematic flow chart of a watchdog control method according to an exemplary embodiment of the present application.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
With rapid development and iterative update of the automobile industry, more and more functional configurations related to auxiliary driving are provided, the integration level of a core chip in the vehicle-mounted electronic device is also higher and higher, and accordingly, the reliability requirement is also higher and higher.
The core device of the common hardware architecture consists of an MCU Chip and an SOC (System On Chip). The MCU is responsible for whole vehicle communication, fault diagnosis and recovery of the whole controller board level, and the SOC is responsible for processing images or big data operation. In order to meet the miniaturization and performance improvement, the new generation of chip architecture gradually packages the MCU and the SOC on the same chip, and the problem of high chip integration level is also accompanied. The MCU and SOC in the chip architecture may share some resources, such as DRAM (Dynamic Random Access Memory ), PMIC (Power Management IC, power management chip), eMMC (Embedded Multi Media Card, embedded multimedia controller), flash, etc., in order to save cost, which may make the start-up time of the MCU longer than that of an independent MCU, and serve as a node of the vehicle body CAN (Controller Area Network, controller area network bus) network, requiring the first frame CAN message to be sent within a specified time, otherwise, other nodes may report the node failure.
In the whole system, the work of the system chip is often interfered by an external electromagnetic field, so that data of various registers and memories are disordered, a program pointer is wrong, a program area is not left, a wrong program instruction is taken out, and the like, the normal operation of the program is interrupted, the system chip cannot continue to work normally, the whole system is in a stagnation state, and unexpected results occur. To avoid this problem, it is common to integrate a watchdog in the PMIC or to circumvent this risk with a separate watchdog. The watchdog can regularly check the execution condition inside the system chip, and once the operation is wrong, the watchdog sends a restarting signal to the system chip, and the watchdog command has the highest priority in the interruption of the program. The application of the watchdog enables the system chip to realize continuous operation in an unmanned state.
Specifically, the working principle of the watchdog is as follows: one pin of the watchdog is connected with one pin of the system chip, a high level (or a low level) is periodically sent to the pin of the watchdog, and once the system chip falls into a certain program segment to enter a dead loop state after the program runs due to interference, the watchdog cannot be executed. At this time, the watchdog will not obtain the signal sent by the system chip, and send a reset signal to the reset pin of the system chip at the pin of the watchdog, so as to reset the system chip, and execute the program from the starting position of the program memory, thus realizing the automatic reset of the system chip.
However, both of the above solutions have some drawbacks.
The defects of the watchdog module integrated in the PMIC are as follows:
at present, a high-reliability PMIC has a residual voltage detection function and a low-voltage detection function, when a plurality of low-voltage conditions continuously occur or the residual voltage condition on an output power rail is detected during starting, the PMIC can enter a safe mode and is directly powered off, recovery can be realized only by re-powering on, at the moment, the PMIC cannot work normally, the whole system cannot be restarted, and under the condition, the system battery can only be forcibly dismounted to be powered off and restarted.
The drawbacks of the independent watchdog module are as follows:
when the independent watchdog module is adopted, the output pin of the watchdog module generally directly controls the enabling pin of the power chip in front of the PMIC, so that the PMIC can be conveniently powered off and restarted. In this case, in order to power down the PMIC more thoroughly, the hold time of the watchdog module operation may be relatively long, however, the hold time may be added to the start-up time of the entire system. The watchdog module itself also belongs to a form of reset chip, so each start-up will have a power-on reset process, which will lead to an increase in the start-up time of the whole system.
It should be noted that, in addition to application to vehicle systems, the watchdog control circuit in the embodiment of the present application has application scenarios with high reliability to electrical devices, such as network, computing, storage, industry, energy, and other devices that need hardware circuits. Through the watchdog control circuit in the embodiment, the first power supply module can be powered off and then powered on, the system is thoroughly powered on and restarted, and the system is helped to recover from the abnormality caused by various hardware or software.
Fig. 1 is a schematic diagram of a watchdog control circuit according to an exemplary embodiment of the present application. As shown in fig. 1, the watchdog control circuit includes a delay circuit 10, a watchdog chip 20 and a logic gate circuit 30, wherein an output end of the delay circuit 10 is connected with an enable pin of the logic gate circuit 30, an input end of the watchdog chip 20 is connected with an input end of the logic gate circuit 30, the watchdog chip 20 is electrically connected with the system chip 40, an output end of the logic gate circuit 30 is connected with an enable pin of the first power module 50, and the first power module 50 is connected with the system chip 40. Specifically, the first power module 50 is connected to the system chip 40 through the PMIC.
In the present embodiment, the system chip 40 is an SOC. The watchdog chip 20 is essentially a timer circuit, generally comprising an input and an output, for periodically checking the internal operation of the system chip 40, and upon detecting an error, immediately sending a restart signal to the system chip 40. More specifically, the watchdog chip 20 outputs a signal to the input terminal at intervals, and if the regular time is exceeded (when the program runs off), a reset signal is given to the system chip 40 to reset the system chip 40, so that the dead halt is prevented, and the function of the watchdog chip 20 is to prevent the program from entering a dead cycle or running off. When the system chip 40 operates, i.e. the counter of the watchdog chip 20 is started, the watchdog chip 20 starts to count automatically, and if the watchdog chip 20 is not cleared up to a certain time, the counter of the watchdog chip 20 overflows to cause the watchdog chip 20 to interrupt, so that the system chip 40 resets to ensure that the vehicle is in a safe operation state. Therefore, when using the watchdog chip 20, attention is paid to resetting the watchdog chip 20. The enable pin of the logic gate 30 is an input pin of the logic gate for controlling the on-off state of the logic gate 30. Likewise, the enable pin of the first power module 50 is an input pin of the first power module 50, and when the pin is activated, the first power module 50 starts to start power supply.
The PMIC plays roles in converting, distributing, detecting and other electric energy management of electric energy in an electronic equipment system, integrates various power rails and power management functions on a single chip, and has the characteristics of high integration level, high efficiency and small volume. The PMIC may monitor the supply voltages on the system chip to ensure that they are not too high or too low. When the PMIC detects that the power rail has fallen to a certain level, the monitor will issue a reset signal which will then be sent to the MCU powered by the same power rail to avoid any data corruption or incorrect transmission at low levels. When the power supply voltage is restored to normal, the monitor also cancels the reset signal to initialize the MCU once.
In the watchdog control circuit shown in fig. 1, the watchdog chip 20 is connected to the first power supply module 50 through the logic gate circuit 30. When the PMIC is in the secure state, the delay circuit 10 outputs a first electrical signal and transmits the first electrical signal to the enable pin of the logic gate circuit 30. The enable pin of the logic gate circuit 30 outputs a blocking signal when receiving the first electrical signal. Illustratively, the blocking signal is in a high resistance state. Under the action of the blocking signal, the output signal of the watchdog chip 20 is isolated from the first power module 50, and the output of the watchdog chip 20 cannot act on the first power module 50, so that the first power module is not affected by the output signal of the watchdog chip during the isolation period.
In this embodiment, when the power management integrated circuit is in a safe state, by adding the delay circuit and the logic gate circuit to the watchdog control circuit, it is realized that when the logic gate circuit receives the first electrical signal, a blocking signal is output, and then isolation between the output signal of the watchdog chip and the enable pin of the first power module is realized, so that the first power module is not affected by the output signal of the watchdog chip during isolation, so that when power-on reset is performed, the time of the watchdog chip executing the power-on reset process is isolated from the start time of the system chip.
In some embodiments, the PMIC has a safety function, and is directly powered off to be no longer output once an abnormality is detected, so that the SOC cannot be restarted when the vehicle is running. Accordingly, when the PMIC is in the secure state, the watchdog chip 20 is configured to control the first power module 50 to stop supplying power. And further, the power supply of the system chip 40 is cut off so that the system chip 40 is powered off and restarted without adopting other manual power-off methods with destructiveness or low operation convenience. That is, by the scheme, the problem that the system chip cannot be actively powered off and started after the power management integrated circuit enters a safe state is solved.
In some embodiments, the watchdog chip is further configured to perform a power-on reset procedure after controlling the first power module to stop supplying power. Next, the following description will be given of the transmission procedure of the electric signal in the watchdog control circuit in the power-on reset procedure of the delay circuit 10 and the watchdog chip 20 by way of the following embodiment.
First, at power-on reset, the duration of the first electrical signal is greater than or equal to the duration of the watchdog chip 20 performing the power-on reset procedure. Illustratively, the duration of the first electrical signal is 1.3s and the duration of the power-on reset process of the watchdog chip 20 is 140 ms. That is, the delay circuit 10 can output the first electric signal for 1.3s from the power-on timing, and after 1.3s, the output signal changes.
At a power-on reset, the delay circuit 10 is further configured to provide a first electrical signal to the logic gate circuit 30; the logic gate circuit 30 is configured to output a blocking signal under control of the first electrical signal.
Illustratively, during a power-on reset, the watchdog chip 20 will remain low for a period of time, in order to ensure that the system-on-chip 40 is not operating until the first power module 50 is stable. Accordingly, in the present embodiment, the purpose of outputting the blocking signal is to isolate the power-on reset process of the watchdog chip 20 from the start-up process of the system chip 40. Meanwhile, the first power module 50 does not supply power to the outside, and the system chip 40 cannot operate.
The watchdog chip 20 outputs a low-level signal when performing a power-on reset procedure.
The output of the watchdog chip 20 has two states, a high level signal and a low level signal, respectively. In the present embodiment, the output of the watchdog chip 20 directly controls the system chip 40. In order to ensure that the system chip 40 is not started before all power is turned on during power-on reset of the watchdog chip 20, the reset pin of the system chip 40 needs to be pulled low by a low level signal output from the watchdog chip 20. In other words, at the time of power-on reset, the watchdog chip 20 outputs a low-level signal, aiming to ensure that the system chip 40 does not operate until the first power module 50 is stable.
The low-level signal output by the watchdog chip in the power-on reset period can ensure that the system chip starts to start working after the first power supply module completely enters the working state, and the working reliability of the system chip is improved.
After the power-on reset of the watchdog chip 20 is finished, the watchdog chip 20 outputs a high-level signal, and at this node, all the sub-power units in the first power module 50 for supplying power to the system chip 40 have already entered the working state, so the reset pin of the system chip 40 can be released by the high-level signal output by the watchdog chip 20, and the system chip 40 starts working.
The watchdog chip 20 needs to input a feeding signal in the feeding time after power-on, and if feeding operation is not completed in the feeding time, the watchdog chip 20 outputs a reset signal, and the characteristic of the reset signal is consistent with the power-on reset mentioned in the embodiment of the application. Specifically, in terms of the characteristics of the reset signal, if the output signal of the watchdog chip 20 is directly used to control the first power module 50, the start-up time of the system chip 40 needs to be added to the reset time (typically 140 ms) of the watchdog chip 20, so in this application, the output signal of the watchdog chip 20 is delayed and isolated by the delay circuit 10 and the logic gate circuit 30. The system chip typically starts feeding the dog at 200ms, thus, during the isolation period, the power-on reset time of the watchdog chip 20 is skipped, and the normal start-up of the system chip 40 is not delayed. Specifically, the control pin of the first power module 50 controlled after the power-on reset of the watchdog chip 20 is at a high level, and at this time, the output of the watchdog chip 20 is also a high level signal, so that the normal start of the system chip 40 is not affected. If the feeding dog is abnormal, the watchdog chip 20 will forcibly turn off the first power module 50.
The logic gate circuit is in a blocking state in the duration of the first electric signal, and by the scheme in the embodiment, the logic gate circuit is always in the blocking state before the power-on reset of the watchdog chip is finished, so that the complete isolation between the power-on reset process of the watchdog chip and the starting time of the system chip is realized, and the starting time of the system chip is not prolonged due to the power-on reset time of the watchdog chip.
Next, the following description will be given of the transmission process of the electric signal in the watchdog control circuit after the end of the power-on reset by the delay circuit 10 and the watchdog chip 20.
The power-on reset refers to that after the power supply is powered on, various internal or external circuits of the chip reset respective subsystems, chips or sub-circuits by monitoring the power supply voltage, and the reset mode with the largest coverage rate in the electronic circuit can cover all system circuits and chips.
The delay circuit 10 is further configured to provide a second electrical signal to the logic gate circuit 30 after the power-on reset is completed; the logic gate circuit 30 is further configured to maintain a high-low level output state after receiving the second electric signal, and the watchdog chip 20 is further configured to control an operation state of the system chip 40 through the logic gate circuit.
Illustratively, the second electrical signal is a low level signal.
Illustratively, after the power-on reset is finished, the watchdog chip 20 provides a high-level signal to the logic gate circuit 30, the logic gate circuit 30 inputs the high-level signal to the first power module 50, and the first power module 50 enters an operating state under the control of the high-level signal to supply power to the system chip 40. After the first power module 50 enters the operating state, the system chip 40 starts to start.
After the system chip 40 is started, the watchdog chip 20 intervenes in the operation of the system chip 40. Specifically, during operation of the system chip 40, a watchdog signal is sent to the watchdog chip 20 for a prescribed time to prove that it has not failed. If the system chip 40 does not send out the feeding signal within the specified time, the watchdog chip 20 defaults to the system chip 40, and at this time, the watchdog chip 20 sends out a forced reset instruction to the system chip 40, so that the system chip 40 is powered off and restarted.
In the embodiment of the application, when the delay circuit outputs a low-level signal, the logic gate circuit is in a high-low-level output state, that is, the logic gate circuit is in a conducting state, and at this time, the input of the logic gate circuit is equal to the output. Further, the high-level signal output by the watchdog chip can control the first power supply module to supply power to the system chip, so that good support on the running state of the system chip is realized.
In some implementations, the delay circuit 10, watchdog chip 20 and logic gate circuit 30 are powered by the second power supply module, either at power-down, at power-up reset, or after the power-up reset is completed.
It will be appreciated that the second power module provides the operating voltage signals for the delay circuit 10, the watchdog chip 20, and the logic gate circuit 30. In other words, the delay circuit 10, the watchdog chip 20 and the logic gate 30 are individually powered by a power source other than the first power module 50, so as to avoid affecting the operation of the delay circuit 10, the watchdog chip 20 and the logic gate 30 after the first power module 50 is powered off. In particular, to keep the watchdog chip 20 in a normal power state, the power supply of the watchdog chip needs to be decoupled from the first power module 50, so as to ensure the operational reliability of the watchdog control circuit.
On the basis of the embodiment shown in fig. 1, the logic gate 30 comprises a tri-state buffer. The delay circuit 10 includes a reset chip and the first electrical signal includes a high level signal.
A tri-state buffer is a circuit element, also called tri-state gate, tri-state driver, for controlling the transmission of signals between different logic levels. The tri-state buffer has three different states, namely a high level, a low level and a high resistance state, and the tri-state output is controlled by the input end of the enabling pin, so that the different output states of the tri-state buffer can be switched by controlling the input signal of the enabling pin of the tri-state buffer. The tri-state buffer can be applied to signal buffering and signal conversion in the fields of amplifiers, logic circuits, data communication and the like. In logic circuits, tri-state buffers are mainly used for signal transmission and signal isolation to prevent signals between stages of circuits from being disturbed. In the embodiment of the present application, when the input end of the enable pin is a high level signal, the output end of the tri-state buffer outputs a high resistance state.
It should be noted that the working principle of the tri-state buffer is different, and the corresponding relationship between the input end and the output end is also different. In some embodiments, the output of the tri-state buffer is in a high impedance state when the input of the enable pin of the tri-state buffer is a low level signal. In other words, the input-output logic of the tri-state buffer may be preconfigured.
In the embodiment of the application, when the logic gate circuit is a tri-state buffer, the output of the tri-state buffer can be adjusted by controlling the input of the enabling pins of the three buffers, so that the method is convenient and quick and has high flexibility. The reset chip has delay characteristic, and can continuously output high-level signals in a certain time interval during the power-on reset period, so that the tri-state buffer can continuously output blocking signals in the time interval, and the power-on reset time of the watchdog core can be independent of the starting time of the system chip during the power-on reset period of the system chip.
Fig. 2 is a schematic flow chart of a watchdog control method according to an exemplary embodiment of the present application. Illustratively, the watchdog control method is applied to a watchdog control circuit comprising: the delay circuit comprises an output end; a logic gate circuit including an enable pin and an output; the watchdog chip is respectively connected with the logic gate circuit and the system chip; the output end of the delay circuit is connected with the enabling pin of the logic gate circuit, the output end of the logic gate circuit is connected with the enabling pin of the first power supply module, and the first power supply module is connected with the system chip. Specifically, a schematic diagram of the structure of the watchdog control circuit is shown in fig. 1.
As shown in fig. 2, in the embodiment of the present application, the watchdog control method includes the following steps.
In step S210, after the power management integrated circuit is in a safe state, the delay circuit is controlled to provide the logic gate circuit with the first electrical signal.
When the PMIC is in a safe state, the PMIC can perform self-locking shutdown, and no external output is generated, so that the SOC can not be started in the process of realizing the vehicle. Illustratively, the first electrical signal is a high level signal.
In step S220, the control logic gate outputs a blocking signal under the control of the first electrical signal.
Illustratively, the blocking signal is in a high resistance state.
Step S230, isolating the output signal of the watchdog chip from the first power module based on the blocking signal,
under the effect of the blocking signal, the output signal of the watchdog chip is isolated from the first power supply module, and the first power supply module is not influenced by the output signal of the watchdog chip during the isolation period.
In the embodiment of the application, when the power management integration is in a state that a delay circuit and a logic gate circuit are added in the watchdog control circuit, the effect that the watchdog chip receives the first electric signal at the logic gate circuit is achieved, the blocking signal is output, the isolation of the output signal of the watchdog chip and the enabling pin of the first power supply module is achieved, the first power supply module is not affected by the output signal of the watchdog chip during the isolation period, and therefore when the power-on reset is conducted, the time of the watchdog chip executing the power-on reset process is isolated from the starting time of the system chip.
It should be understood that the description of the watchdog control method embodiments corresponds to the description of the watchdog control circuit embodiments, and therefore, parts not described in detail may be referred to the corresponding embodiments of the preceding circuits.
Some embodiments of the present application further provide an electronic device including the watchdog control circuit mentioned in any of the above embodiments. The electronic device is an electronic chip, and can be installed in a control module of the whole system; alternatively, the electronic device is an electronic computer and can be applied to a mobile communication product.
The basic principles of the present application have been described above in connection with specific embodiments, however, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are merely examples and not limiting, and these advantages, benefits, effects, etc. are not to be considered as necessarily possessed by the various embodiments of the present application. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, as the application is not intended to be limited to the details disclosed herein as such.
The block diagrams of the circuits referred to in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, the electrical components may be connected, arranged, configured in any manner. Words such as "including," "comprising," "having," and the like are words of openness and mean "including but not limited to," and are used interchangeably therewith. The terms "or" and "as used herein refer to and are used interchangeably with the term" and/or "unless the context clearly indicates otherwise. The term "such as" as used herein refers to, and is used interchangeably with, the phrase "such as, but not limited to.
It should also be noted that components or steps in embodiments of the present application may be disassembled and/or assembled. Such decomposition and/or recombination should be considered as equivalent to the present application.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the application. Thus, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the application to the form disclosed herein. Although a number of example aspects and embodiments have been discussed above, a person of ordinary skill in the art will recognize certain variations, modifications, alterations, additions, and subcombinations thereof.
Claims (10)
1. A watchdog control circuit, comprising:
the delay circuit comprises an output end;
a logic gate circuit including an enable pin and an output;
the watchdog chip is respectively connected with the logic gate circuit and the system chip;
the output end of the delay circuit is connected with an enabling pin of the logic gate circuit, the output end of the logic gate circuit is connected with an enabling pin of a first power supply module, and the first power supply module is connected with the system chip;
the delay circuit is configured to provide a first electrical signal to the logic gate circuit upon a power-on reset after the power management integrated circuit is in a secure state;
the logic gate circuit is configured to output a blocking signal under the control of the first electrical signal so as to isolate the output signal of the watchdog chip from the first power supply module by the blocking signal, so that the first power supply module is not affected by the output signal of the watchdog chip during isolation, and the time of the watchdog chip executing a power-on reset process is isolated from the starting time of the system chip during power-on reset.
2. The watchdog control circuit of claim 1, wherein the first power module is coupled to the system chip via the power management integrated circuit, the watchdog chip configured to control the first power module to cease supplying power after the power management integrated circuit is in a safe state upon detecting an abnormality in a vehicle system.
3. The watchdog control circuit of claim 2, wherein the watchdog chip is further configured to perform a power-on reset process after controlling the first power module to stop powering, wherein a duration of the first electrical signal is greater than or equal to a duration of the watchdog chip performing the power-on reset process.
4. A watchdog control circuit according to claim 3, wherein the watchdog chip outputs a low level signal when the power-on reset procedure is performed.
5. The watchdog control circuit of claim 1, wherein,
the delay circuit is further configured to provide a second electrical signal to the logic gate circuit after the first electrical signal output is completed;
wherein the logic gate circuit is further configured to maintain a high-low level output state after receiving the second electrical signal, and the watchdog chip is further configured to control an operation state of the system chip through the logic gate circuit.
6. The watchdog control circuit of claim 5, wherein the watchdog chip is further configured to control an operational state of the system chip via the logic gate circuit, comprising:
the watchdog chip is further configured to provide a high-level signal for the logic gate circuit after the power-on reset is finished, so that the logic gate circuit inputs the high-level signal to the first power supply module, the first power supply module enters a working state under the action of the high-level signal, and the system chip starts after the first power supply module enters the working state.
7. The watchdog control circuit of any of claims 1-6, wherein the delay circuit, the watchdog chip and the logic gate are powered by a second power module.
8. The watchdog control circuit of any one of claims 1 to 6, wherein the delay circuit comprises a reset chip, the first electrical signal comprises a high level signal, and the logic gate circuit comprises a tri-state buffer.
9. A watchdog control method, characterized by being applied to a watchdog control circuit, the watchdog control circuit comprising: the delay circuit comprises an output end; a logic gate circuit including an enable pin and an output; the watchdog chip is respectively connected with the logic gate circuit and the system chip; the output end of the delay circuit is connected with an enabling pin of the logic gate circuit, the output end of the logic gate circuit is connected with an enabling pin of a first power supply module, and the first power supply module is connected with the system chip;
the method comprises the following steps:
after the power management integrated circuit is in a safe state, controlling the delay circuit to provide a first electric signal for the logic gate circuit during power-on reset;
under the control of the first electric signal, controlling the logic gate circuit to output a blocking signal;
and isolating the output signal of the watchdog chip from the first power supply module based on the blocking signal, so that the first power supply module is not influenced by the output signal of the watchdog chip during isolation, and the time of the watchdog chip executing a power-on reset process is isolated from the starting time of the system chip during power-on reset.
10. An electronic device comprising the watchdog control circuit of any one of claims 1 to 8.
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| CN202311332550.9A CN117093403B (en) | 2023-10-16 | 2023-10-16 | Watchdog control circuit, control method thereof and electronic equipment |
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| CN117093403B true CN117093403B (en) | 2024-01-26 |
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| CN117093403A (en) | 2023-11-21 |
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