CN116541203A - Hardware watchdog circuit of LINUX system and dynamic ring monitoring host - Google Patents
Hardware watchdog circuit of LINUX system and dynamic ring monitoring host Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a hardware watchdog circuit of LINUX system and a dynamic ring monitoring host, including time delay control module, watchdog power management module and watchdog control reset module, the watchdog control reset module is equipped with the watchdog chip, wherein: the delay control module is used for generating a high-level trigger signal and a low-level trigger signal and sending the high-level trigger signal and the low-level trigger signal to the watchdog power management module; the watchdog power management module is used for controlling the power on or off of a watchdog chip in the watchdog monitoring and resetting module; the watchdog monitoring reset module is used for generating a low-level reset signal by the watchdog chip after the watchdog feeding of the embedded system is overtime and sending the low-level reset signal to a main control chip of the embedded system, and monitoring the working state of a LINUX system of the embedded system by whether the watchdog chip can normally receive the watchdog feeding signal sent by the main control chip of the embedded system when the power supply of the watchdog chip is connected. When the method is applied, the LINUX system can be triggered to restart until the restarting is successful when the system is abnormal.
Description
Technical Field
The invention relates to the technical field of embedded system security, in particular to a hardware watchdog circuit and a dynamic ring monitoring host of a LINUX system.
Background
With the development of intelligent terminals and mobile internet, LINUX systems are increasingly commonly applied to embedded devices, such as mobile communication base stations, industrial control devices, android smartphones based on LINUX kernels and the like. In an embedded system, when a CPU enters an error state, the system needs to be capable of realizing automatic reset, and a watchdog is generally adopted at present to realize the function of automatically recovering from faults.
In the current embedded system with LINUX system, because the loading time of LINUX system is longer (more than 10 s), and the time interval of watchdog is more than (typically 1.6 s), the watchdog cannot be fed in the process, and in order to ensure the normal starting of the system, a hardware watchdog is generally used. Hardware watchdog is generally classified into two types, internal watchdog and external watchdog, according to whether the watchdog is integrated with CPU or not. The internal watchdog is integrated in the CPU, the initialization of the internal watchdog needs software participation, the reliability cannot be ensured, and the condition that the system cannot be restarted and is halted and hung up is easily caused. The external watchdog is usually programmed by CPLD or FPGA to be a delay external circuit, which has high cost and needs to write programs, and the risk of system halt still exists.
Disclosure of Invention
The invention aims to solve the problem that the existing embedded system with LINUX system still has the problem of dead halt due to incapability of restarting after the hardware watchdog is configured, and provides a hardware watchdog circuit of the LINUX system, which is built by adopting discrete elements, has low cost, is stable and reliable, and can trigger the LINUX system to restart until the restarting is successful when the system is abnormal. The invention also discloses a dynamic ring monitoring host realized by the hardware watchdog circuit based on the LINUX system.
The aim of the invention is mainly realized by the following technical scheme:
the utility model provides a hardware watchdog circuit of LINUX system, includes delay control module, watchdog power management module and watchdog control reset module, watchdog control reset module is equipped with the watchdog chip, wherein:
the delay control module is used for receiving the high-level control signal output by the watchdog monitoring reset module and delaying according to the set delay time when the embedded system is powered on and started for the first time after power failure, generating a high-level trigger signal and sending the high-level trigger signal to the watchdog power management module; after the feeding time of the embedded system is overtime, receiving a low-level reset signal output by the watchdog monitoring reset module, generating a low-level trigger signal and sending the low-level trigger signal to the watchdog power management module; the method comprises the steps of setting delay time to be longer than LINUX system starting time;
the watchdog power management module is used for receiving the high-level trigger signal sent by the delay control module to control the watchdog chip in the watchdog monitoring reset module to be powered on, and receiving the low-level trigger signal sent by the delay control module to control the watchdog chip in the watchdog monitoring reset module to be powered off;
the watchdog monitoring reset module is used for generating a high-level control signal when the LINUX system of the embedded system is powered on and started for the first time after each time of power failure and sending the high-level control signal to the delay control module; the watchdog chip generates a low-level reset signal and sends the low-level reset signal to the delay control module and the main control chip of the embedded system after the watchdog feeding of the embedded system is overtime; the method is used for monitoring the working state of the LINUX system of the embedded system through whether the watchdog feeding signal sent by the main control chip of the embedded system can be normally received when the power supply of the watchdog chip is connected.
Further, the delay control module comprises a charge-discharge capacitor, the delay control module generates a low-level trigger signal before the charge-discharge capacitor is charged and saturated and sends the low-level trigger signal to the watchdog power management module, the watchdog power management module is used for receiving the low-level trigger signal to control the power disconnection of a watchdog chip in the watchdog monitoring and resetting module, and the delay control module generates a high-level trigger signal after the charge-discharge capacitor is charged and saturated.
Further, the delay control module further comprises a charging control module and a discharging control module, the charging control module and the discharging control module simultaneously receive signals output by the watchdog monitoring reset module, when the watchdog monitoring reset module outputs high-level control signals, the charging control module works to control the charging of the charging and discharging capacitor, the delay control module generates high-level trigger signals after the charging and discharging capacitor is saturated, and the set delay time is the time for the charging and discharging capacitor to be saturated; the discharging control module works to control the discharging of the charging and discharging capacitor after the feeding of the embedded system is overtime, and the delay control module generates a low-level trigger signal after the discharging of the charging and discharging capacitor and sends the low-level trigger signal to the watchdog power management module.
Further, the charge control module comprises a first PNP triode, a first resistor, a third resistor and a first NMOS tube, wherein the base electrode of the first PNP triode is connected with a watchdog output pin of a watchdog chip, the collector electrode of the first PNP triode is grounded, the emitter electrode of the first PNP triode is connected with the grid electrode of the first NMOS tube, the two ends of the first resistor are respectively connected with the source electrode of the first NMOS tube and a charge-discharge capacitor, the other end of the charge-discharge capacitor, which is relatively connected with the first resistor, is grounded, the two ends of the third resistor are respectively connected with the emitter electrode of the first PNP triode and a power supply, the drain electrode of the first NMOS tube is connected with the power supply, and the input end of the watchdog power supply management module is connected to a circuit between the first resistor and the charge-discharge capacitor.
Further, the discharging control module comprises a second PNP triode, a second resistor, a fourth resistor and a first PMOS tube, wherein the base electrode of the second PNP triode is connected with a watchdog output pin of a watchdog chip, the collector electrode of the second PNP triode is grounded, the emitter electrode of the second PNP triode is connected with the grid electrode of the first PMOS tube, one end of the second resistor is connected with the drain electrode of the first PMOS tube, and the other end of the second resistor is grounded; one end of the fourth resistor is connected to a circuit between the emitter of the second PNP triode and the grid electrode of the first PMOS tube, and the other end of the fourth resistor is connected with a power supply; the source electrode of the first PMOS tube is connected to a connection node of a circuit between the first resistor and the charge-discharge capacitor at the input end of the watchdog power supply management module.
Further, the watchdog power management module comprises a comparator, a first NPN triode, a fifth resistor and a second PMOS tube, wherein the watchdog power management module is connected with the output end of the delay control module through the non-inverting input end of the comparator, the inverting input end of the comparator is connected with a power supply, the output end of the comparator is connected with the base electrode of the first NPN triode, the emitter electrode of the first NPN triode is grounded, and the collector electrode of the first NPN triode is connected with the grid electrode of the second PMOS tube; one end of the fifth resistor is connected with the collector electrode of the first NPN triode, and the other end of the fifth resistor is connected with a power supply; the second PMOS tube source electrode is connected with a power supply, and the watchdog power supply management module is connected with the power supply end of the watchdog chip in the watchdog monitoring reset module through the second PMOS tube drain electrode thereof to realize connection with the watchdog monitoring reset module.
Further, the watchdog monitoring reset module further comprises a sixth resistor, the watchdog chip is connected with the embedded system main control chip through a watchdog signal input pin of the watchdog chip, is connected with the delay control module through a watchdog output pin of the watchdog chip, one end of the sixth resistor is connected to a circuit between the watchdog output pin of the watchdog chip and the delay control module, and the other end of the sixth resistor is connected with a power supply.
Further, the watchdog monitoring reset module further comprises a filter capacitor, one end of the filter capacitor is connected to a connection node of a circuit between the watchdog output pin of the watchdog chip and the delay control module, and the other end of the filter capacitor is grounded.
The movable ring monitoring host realized by the hardware watchdog circuit based on the LINUX system further comprises a power module connected with the main control chip, the main control chip starts to enable the watchdog circuit after being started, meanwhile, feeding dogs is started, and a low-level reset signal output by the watchdog circuit controls an enabling signal of the power module.
In summary, compared with the prior art, the invention has the following beneficial effects: (1) The external watchdog can ensure that the LINUX system is powered on for the first time to work normally and monitor the operation of the LINUX system after each time of power failure, can trigger the LINUX system to restart after the LINUX system fails to work normally, and can trigger the system to restart again after the first restart fails until the restart is successful.
(2) The delay starting time of the watchdog can be set according to the requirement, so that the system can be ensured to be started normally.
(3) The invention has no software, the whole circuit is designed by discrete components, the invention is stable and reliable, the components are fewer, and the cost is low.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention. In the drawings:
FIG. 1 is a schematic diagram of a watchdog circuit according to one embodiment of the present invention;
fig. 2 is a schematic diagram of a watchdog circuit of a dynamic ring monitor host and a connection of a main control chip according to an embodiment of the present invention.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
Examples:
as shown in fig. 1, a hardware watchdog circuit of a LINUX system includes a delay control module, a watchdog power management module and a watchdog monitoring and resetting module, where the watchdog monitoring and resetting module in this embodiment is provided with a watchdog chip, and the watchdog chip in this embodiment is preferably implemented by using a MAX823reuk+t chip. The delay control module is used for receiving the high-level control signal output by the watchdog monitoring reset module and delaying according to the set delay time when the embedded system is powered on and started for the first time after power failure, generating a high-level trigger signal and sending the high-level trigger signal to the watchdog power management module; after the feeding time of the embedded system is overtime, receiving a low-level reset signal output by the watchdog monitoring reset module, generating a low-level trigger signal and sending the low-level trigger signal to the watchdog power management module; the set delay time is longer than the LINUX system starting time. The watchdog power management module is used for receiving the high-level trigger signal sent by the delay control module to control the watchdog chip in the watchdog monitoring and resetting module to be powered on, and receiving the low-level trigger signal sent by the delay control module to control the watchdog chip in the watchdog monitoring and resetting module to be powered off. The watchdog monitoring reset module is used for generating a high-level control signal when the LINUX system of the embedded system is powered on and started for the first time after each time of power failure and sending the high-level control signal to the delay control module; the watchdog chip generates a low-level reset signal and sends the low-level reset signal to the delay control module and the main control chip of the embedded system after the watchdog feeding of the embedded system is overtime; the method is used for monitoring the working state of the LINUX system of the embedded system through whether the watchdog feeding signal sent by the main control chip of the embedded system can be normally received when the power supply of the watchdog chip is connected. When the embodiment is applied, the main control chip of the embedded system outputs a low-level dog feeding signal with the duration of 100ms to the outside at the timing of 500ms to the watchdog signal input pin WDI of the watchdog chip. After the LINUX system of the embedded system is started, two working states exist, wherein the first working state is that the LINUX system normally operates, at the moment, a watchdog chip can normally receive a watchdog feeding signal, and a watchdog monitoring reset module keeps monitoring the working state of the LINUX system of the embedded system; the second working state is that the LINUX system works abnormally, and the watchdog chip can not normally receive the watchdog feeding signal at the moment, namely the watchdog feeding overtime. After the watchdog is overtime, a low-level RESET signal generated by the watchdog chip is sent to a main control chip of the embedded system through a RESET pin of a watchdog output pin of the watchdog chip, and the main control chip of the embedded system restarts the LINUX system after receiving the low-level RESET signal.
The delay control module of the embodiment comprises a charge-discharge capacitor, wherein the delay control module generates a low-level trigger signal before the charge-discharge capacitor is charged and saturated and sends the low-level trigger signal to the watchdog power management module, and the watchdog power management module is used for receiving the low-level trigger signal to control the power disconnection of a watchdog chip in the watchdog monitoring and resetting module, and the delay control module generates a high-level trigger signal after the charge-discharge capacitor is charged and saturated. The delay control module of the embodiment further comprises a charging control module and a discharging control module, the charging control module and the discharging control module simultaneously receive signals output by the watchdog monitoring reset module, when the watchdog monitoring reset module outputs high-level control signals, the charging control module controls the charging of the charging and discharging capacitor, the delay control module generates high-level trigger signals after the charging and discharging capacitor is saturated, and the set delay time is the time for the charging and discharging capacitor to be saturated; the discharging control module works to control the discharging of the charging and discharging capacitor after the feeding of the embedded system is overtime (the low-level reset signal output by the watchdog monitoring and resetting module is received), and the delay control module generates a low-level trigger signal after the discharging of the charging and discharging capacitor and sends the low-level trigger signal to the watchdog power management module. In the embodiment, the time required for the charging and discharging capacitor to start to charge and saturate is taken as the set delay time, when the embedded system is powered on and started for the first time after each time of power failure in practical implementation, before the charging and discharging capacitor is charged and saturated, the delay control module also generates a low-level trigger signal to be sent to the watchdog power management module, the watchdog power management module receives the low-level trigger signal to control the power of the watchdog chip in the watchdog monitoring and resetting module to be kept off, the delay control module generates a high-level trigger signal to be sent to the watchdog power management module after the charging and discharging capacitor is charged and saturated, and the watchdog power management module receives the high-level trigger signal to control the watchdog chip in the watchdog monitoring and resetting module to be connected with the power.
The charge control module of this embodiment includes a first PNP transistor, a first resistor, a third resistor, and a first NMOS transistor, where the first PNP transistor of this embodiment is implemented by using a 2SB1132R chip, and the first NMOS transistor is implemented by using an AO3402 chip. The first PNP triode base of this embodiment is connected with the watchdog output pin (watchdog chip U3 pin 1) of watchdog chip, and first PNP triode collector ground connection, first PNP triode projecting pole is connected with first NMOS pipe grid, first resistance both ends are connected with first NMOS pipe source electrode and charge-discharge capacitor respectively, the other end ground connection of first resistance end is connected relatively to charge-discharge capacitor, third resistance both ends are connected with first PNP triode projecting pole and power respectively, first NMOS pipe drain electrode is connected with the power, watchdog power management module input is connected on the circuit between first resistance and charge-discharge capacitor.
The discharging control module of the embodiment comprises a second PNP triode, a second resistor, a fourth resistor and a first PMOS tube, wherein the second PNP triode of the embodiment is realized by a 2SB1132R chip, and the first PMOS tube is realized by an AO3401 chip. The base electrode of the second PNP triode is connected with a watchdog output pin (a U3 pin 1 of the watchdog chip) of the watchdog chip, the collector electrode of the second PNP triode is grounded, the emitter electrode of the second PNP triode is connected with the grid electrode of the first PMOS tube, one end of the second resistor is connected with the drain electrode of the first PMOS tube, and the other end of the second resistor is grounded; one end of the fourth resistor is connected to a circuit between the emitter of the second PNP triode and the grid electrode of the first PMOS tube, and the other end of the fourth resistor is connected with a power supply; the source electrode of the first PMOS tube is connected to a connection node of a circuit between the first resistor and the charge-discharge capacitor at the input end of the watchdog power supply management module.
The watchdog power management module of this embodiment includes a comparator, a first NPN triode, a fifth resistor and a second PMOS tube, where the comparator of this embodiment is implemented by using a TLV3201AIDBVR chip, the first NPN triode is implemented by using an S8050 chip, and the second PMOS tube is implemented by using an AO3401 chip. The watchdog power management module is connected with the output end of the delay control module through the non-inverting input end of the comparator, and the non-inverting input end of the comparator is used as the input end of the watchdog power management module and is specifically connected to a circuit between the first resistor and the charge-discharge capacitor. The inverting input end of the comparator is connected with a power supply, the output end of the comparator is connected with the base electrode of the first NPN triode, the emitter electrode of the first NPN triode is grounded, and the collector electrode of the first NPN triode is connected with the grid electrode of the second PMOS tube; one end of the fifth resistor is connected with the collector electrode of the first NPN triode, and the other end of the fifth resistor is connected with a power supply; the second PMOS tube source electrode is connected with a power supply, and the watchdog power management module is connected with a power supply end (a watchdog chip pin 5) of a watchdog chip in the watchdog monitoring reset module through a second PMOS tube grid electrode of the second PMOS tube source electrode to realize connection with the watchdog monitoring reset module.
The watchdog monitoring reset module of the embodiment further comprises a sixth resistor and a filter capacitor, wherein the watchdog chip is connected with the embedded system main control chip through a watchdog feeding signal input pin (a watchdog chip pin 4) and is connected with the delay control module through a watchdog output pin (a watchdog chip pin 1). One end of the sixth resistor of the embodiment is connected to a line between the watchdog output pin of the watchdog chip and the delay control module, and the other end of the sixth resistor is connected to a power supply. One end of the filter capacitor of the embodiment is connected to a connection node of a circuit between a watchdog output pin of the watchdog chip and the delay control module, and the other end of the filter capacitor is grounded.
When the embodiment is applied, the specific workflow is as follows:
process one
When the LINUX system of the embedded system is powered on again after the power supply is turned off every time, at this time, the watchdog chip of the watchdog monitoring reset module is not powered on and does not work, and the main control chip of the embedded system does not input a watchdog feeding signal to a watchdog feeding signal input pin of the watchdog chip. The watchdog output pin port WD0 of the watchdog chip is pulled up to be at a high level initially through the sixth resistor R6, bases of the first PNP triode Q3 and the second PNP triode Q4 are at a high level, the third resistor R3 and the fourth resistor R4 are pulled up to be at a power supply, so that collector electrodes of the first PNP triode Q3 and the second PNP triode Q4 are at a high level, and the first PNP triode Q3 and the second PNP triode Q4 are cut off. At this time, the gate voltage minus the source voltage (Vg-Vs) of the first NMOS transistor Q7 is greater than the threshold voltage VGS (AO 3402 has a threshold voltage of 1V), and the first NMOS transistor Q7 is turned on. The source voltage of the first PMOS tube Q1 is equal to the voltage of the charge-discharge capacitor U1, the voltage of the source electrode subtracted from the gate voltage of the first PMOS tube Q1 (Vg-Vs) is larger than 0V, and the first PMOS tube Q1 is cut off. The power supply VCC charges the charge-discharge capacitor U1 through the first resistor R1, the charging time is T=2.3RC (the charging time can be adjusted by adjusting RC parameters, namely, the circuit delay time), before full charge, the voltage of the third pin of the comparator U2 is lower than that of the fourth pin, the comparator U2 outputs a low level, the base electrode of the first NPN triode Q6 is low, the first NPN triode Q6 is cut off, the gate voltage of the second PMOS tube Q5 is equal to the power supply voltage (Vg=VCC), so Vg-vs is more than or equal to 0V, the second PMOS tube Q5 is cut off and is not conducted, the watchdog chip U3 is not electrified, the port WDO of the output pin of the watchdog chip U3 does not output a low level signal, and the LINUX system is started normally. After the charging and discharging capacitor U1 is charged, the voltage of the third pin of the comparator U2 is equal to the voltage of the fourth pin, and the comparator U2 outputs a high level to make the base of the first NPN triode Q6 be high, and the base is grounded. The first NPN triode Q6 is conducted to enable the grid voltage of the second PMOS tube Q5 to be 0V, the grid voltage minus the source voltage (Vg-Vs) is smaller than 0V, the second PMOS tube Q5 is conducted, the watchdog chip U3 is electrified and started, because the RC charging time is longer than the LINUX system starting time, the LINUX system works normally at this moment, the main control chip of the embedded system inputs a feeding signal to the feeding signal input pin of the watchdog chip, the feeding is normally carried out, and the watchdog monitors the working state of the LINUX system normally.
Therefore, the watchdog chip is started in a power-on delay way in the process, the system is started in the power-on way for the first time, the watchdog chip does not work before the system is started, after the power-on is completed, the watchdog chip is started after the delay is reached, the embedded system feeds dogs normally, and the operation of the whole LINUX system is monitored.
Process two
When the LINUX system works abnormally, the main control chip of the embedded system does not input a dog feeding signal to the dog feeding signal input pin of the watchdog chip, the dog feeding is overtime, the port WDO of the dog output pin of the watchdog chip U2 outputs a low level as a reset signal, and the whole system is reset. The low level output by the watchdog output pin port WDO of the watchdog chip U2 makes the bases of the first PNP triode Q3 and the second PNP triode Q4 low, the first PNP triode Q3 and the second PNP triode Q4 are connected to ground, the gate voltage of the first NMOS tube Q7 is 0V, the gate voltage is smaller than the source voltage, the first NMOS tube Q7 is disconnected, the gate voltage of the first PMOS tube Q1 is 0V, the gate voltage minus the source voltage VG-vs=0v, the first PMOS tube Q1 is turned on, the charge-discharge capacitor U1 discharges to ground through the second resistor R2, at this time, the third pin of the comparator U2 is lower than the fourth pin voltage, the comparator U2 outputs a low level, the base of the first NPN triode Q6 is 0V, the first NPN triode Q6 is turned off, the gate of the second PMOS tube Q5 is pulled up to the power supply by R5, at this time, the gate voltage minus the source voltage VS-V of the second PMOS tube Q5 is greater than 0V, the second PMOS tube Q5 is turned off, the gate voltage is turned off, and the gate voltage of the second PMOS tube Q5 is turned off, and the dog chip is turned off. After the watchdog chip U3 stops working, the watchdog output pin port WDO of the watchdog chip U3 is pulled up to the power supply by the sixth resistor R6 and becomes high level, so that the watchdog circuit enters the power-on delay, and the working flow of the first flow is repeated. After the system is restarted successfully, the main control chip of the embedded system outputs a dog feeding signal, and after the delay time is reached, the watchdog chip U3 is electrified to start working, the whole system operates normally, and the watchdog chip U3 monitors the system operation condition again.
Process three
If the LINUX system is restarted abnormally, the first restart is unsuccessful, the watchdog chip U3 does not have a feeding dog signal input, and the circuit repeats the second condition to restart until the system is started successfully.
The embodiment also comprises a movable ring monitoring host realized by a hardware watchdog circuit based on the LINUX system, wherein the movable ring monitoring host is used for carrying out centralized monitoring on power equipment and environment variables in various machine rooms. In the embodiment, the embedded system main control chip of the movable ring monitoring host is realized by adopting an intelligent core micro SCM701 main control chip, the SCM701 main control chip is designed by adopting ARM Cortex-A7 IP, is of a single-core 4-core architecture, is embedded with a Mali400 MP2 GPU, and enhances the parallel operation capability of the chip through the GPU. The main control chip has rich peripheral interfaces. As shown in fig. 2, the rotating ring monitoring host of the present embodiment includes a power module connected to a main control chip, and the power module is preferably implemented by using an ETA8156 power chip. The main control chip of the embodiment starts to enable the watchdog circuit after being started, and starts to feed dogs at the same time, and the low-level reset signal output by the watchdog circuit controls the enabling signal of the power supply module.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (9)
1. The utility model provides a hardware watchdog circuit of LINUX system, its characterized in that includes delay control module, watchdog power management module and watchdog control reset module, watchdog control reset module is equipped with the watchdog chip, wherein:
the delay control module is used for receiving the high-level control signal output by the watchdog monitoring reset module and delaying according to the set delay time when the embedded system is powered on and started for the first time after power failure, generating a high-level trigger signal and sending the high-level trigger signal to the watchdog power management module; after the feeding time of the embedded system is overtime, receiving a low-level reset signal output by the watchdog monitoring reset module, generating a low-level trigger signal and sending the low-level trigger signal to the watchdog power management module; the method comprises the steps of setting delay time to be longer than LINUX system starting time;
the watchdog power management module is used for receiving the high-level trigger signal sent by the delay control module to control the watchdog chip in the watchdog monitoring reset module to be powered on, and receiving the low-level trigger signal sent by the delay control module to control the watchdog chip in the watchdog monitoring reset module to be powered off;
the watchdog monitoring reset module is used for generating a high-level control signal when the LINUX system of the embedded system is powered on and started for the first time after each time of power failure and sending the high-level control signal to the delay control module; the watchdog chip generates a low-level reset signal and sends the low-level reset signal to the delay control module and the main control chip of the embedded system after the watchdog feeding of the embedded system is overtime; the method is used for monitoring the working state of the LINUX system of the embedded system through whether the watchdog feeding signal sent by the main control chip of the embedded system can be normally received when the power supply of the watchdog chip is connected.
2. The hardware watchdog circuit of the LINUX system according to claim 1, wherein the delay control module comprises a charge-discharge capacitor, the delay control module generates a low-level trigger signal before the charge-discharge capacitor is charged and saturated and sends the low-level trigger signal to the watchdog power management module, the watchdog power management module is used for receiving the low-level trigger signal to control the power disconnection of a watchdog chip in the watchdog monitoring and resetting module, and the delay control module generates a high-level trigger signal after the charge-discharge capacitor is charged and saturated.
3. The hardware watchdog circuit of the LINUX system according to claim 2, wherein the delay control module further comprises a charging control module and a discharging control module, the charging control module and the discharging control module simultaneously receive signals output by a watchdog monitoring reset module, when the watchdog monitoring reset module outputs high-level control signals, the charging control module works to control charging of the charging and discharging capacitor, the delay control module regenerates high-level trigger signals after the charging and discharging capacitor is saturated, and the set delay time is the time for the charging and discharging capacitor to be saturated; the discharging control module works to control the discharging of the charging and discharging capacitor after the feeding of the embedded system is overtime, and the delay control module generates a low-level trigger signal after the discharging of the charging and discharging capacitor and sends the low-level trigger signal to the watchdog power management module.
4. The hardware watchdog circuit of the LINUX system according to claim 3, wherein the charging control module comprises a first PNP triode, a first resistor, a third resistor and a first NMOS tube, a base electrode of the first PNP triode is connected with a watchdog output pin of the watchdog chip, a collector electrode of the first PNP triode is grounded, an emitter electrode of the first PNP triode is connected with a grid electrode of the first NMOS tube, two ends of the first resistor are respectively connected with a source electrode of the first NMOS tube and a charging and discharging capacitor, the other end of the charging and discharging capacitor is grounded, two ends of the third resistor are respectively connected with an emitter electrode of the first PNP triode and a power supply, a drain electrode of the first NMOS tube is connected with the power supply, and an input end of the watchdog power supply management module is connected to a circuit between the first resistor and the charging and discharging capacitor.
5. The hardware watchdog circuit of the LINUX system according to claim 4, wherein the discharging control module comprises a second PNP triode, a second resistor, a fourth resistor and a first PMOS transistor, a base of the second PNP triode is connected with a watchdog output pin of the watchdog chip, a collector of the second PNP triode is grounded, an emitter of the second PNP triode is connected with a gate of the first PMOS transistor, one end of the second resistor is connected with a drain of the first PMOS transistor, and the other end of the second resistor is grounded; one end of the fourth resistor is connected to a circuit between the emitter of the second PNP triode and the grid electrode of the first PMOS tube, and the other end of the fourth resistor is connected with a power supply; the source electrode of the first PMOS tube is connected to a connection node of a circuit between the first resistor and the charge-discharge capacitor at the input end of the watchdog power supply management module.
6. The hardware watchdog circuit of the LINUX system according to claim 3, wherein the watchdog power management module comprises a comparator, a first NPN triode, a fifth resistor and a second PMOS tube, the watchdog power management module is connected with the output end of the delay control module through the non-inverting input end of the comparator, the inverting input end of the comparator is connected with a power supply, the output end of the comparator is connected with the base electrode of the first NPN triode, the emitter electrode of the first NPN triode is grounded, and the collector electrode of the first NPN triode is connected with the gate electrode of the second PMOS tube; one end of the fifth resistor is connected with the collector electrode of the first NPN triode, and the other end of the fifth resistor is connected with a power supply; the second PMOS tube source electrode is connected with a power supply, and the watchdog power supply management module is connected with the power supply end of the watchdog chip in the watchdog monitoring reset module through the second PMOS tube drain electrode thereof to realize connection with the watchdog monitoring reset module.
7. The hardware watchdog circuit of a LINUX system according to any one of claims 1 to 6, wherein the watchdog monitoring reset module further comprises a sixth resistor, the watchdog chip is connected to the embedded system main control chip through a watchdog signal input pin thereof, and is connected to the delay control module through a watchdog output pin thereof, and one end of the sixth resistor is connected to a line between the watchdog output pin of the watchdog chip and the delay control module, and the other end of the sixth resistor is connected to a power supply.
8. The hardware watchdog circuit of a LINUX system of claim 7, wherein the watchdog monitor reset module further comprises a filter capacitor, one end of the filter capacitor is connected to a connection node of a circuit between a watchdog output pin of the watchdog chip and the delay control module of the sixth resistor, and the other end of the filter capacitor is grounded.
9. The movable ring monitoring host realized by a hardware watchdog circuit of a LINUX system according to any one of claims 1 to 8, further comprising a power module connected with a main control chip, wherein the main control chip starts to enable the watchdog circuit after being started, and starts to feed dogs at the same time, and a low level reset signal output by the watchdog circuit controls an enable signal of the power module.
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