JP2015225360A - Watchdog timer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a watchdog timer device, which sets time-out time by using a capacitance value on a capacitor, capable of changing the time-out time while preventing unintended reset.SOLUTION: A watchdog timer device 3 includes: a control signal delay circuit 38 for delaying a control signal for changing a capacitance value on a capacitor part 35; an INH control circuit 37 that, when a control signal is input without via the control signal delay circuit 38 and when the control signal is input or stopped, disables the watchdog timer device 3 for a predetermined period; and a capacitance value alteration circuit 36 that changes the capacitance value on the capacitor part 35 based on the signal output from the control signal delay circuit 38.

Description

  The present invention relates to a watchdog timer device that monitors an abnormality of a monitoring target (for example, a CPU).

  Conventionally, a watchdog timer device for monitoring an abnormality of a CPU mounted on a system has been used.

  FIG. 1 shows a general configuration of a watchdog timer device composed of a constant current source and a capacitor among conventional watchdog timer devices.

  As shown in FIG. 1, the conventional watchdog timer device 1 includes a voltage monitoring circuit 11, a reset signal generation circuit 12, a clock detection circuit 13, a constant current source circuit 14, and a capacitor unit 15.

  The voltage monitoring circuit 11 monitors the voltage of power supplied from the power source (not shown) to the watchdog timer device 1. The voltage monitoring circuit 11 monitors the voltage applied to the capacitor unit 15.

  In addition, when the voltage applied to the capacitor unit 15 is equal to or lower than a threshold value (VctL described later), the voltage monitoring circuit 11 notifies the reset signal generation circuit 12 to that effect.

  The constant current source circuit 14 is a circuit for charging the capacitor Ct included in the capacitor unit 15 with a constant current based on the power supplied from the power source. The constant current source circuit 14 is also used for discharging the capacitor Ct with a constant current.

  The capacitor unit 15 includes a capacitor Ct, and the monitoring time (timeout time) can be set according to the capacitance value of the capacitor unit 15.

  The capacitor Ct is charged with a constant current by the constant current source circuit 14, and is discharged with a constant current when charging is completed (switching from charging to discharging).

  When the clock detection circuit 13 detects the presence of an SCK signal, which will be described later, the constant current source circuit 14 starts charging the capacitor Ct (switching from discharging to charging).

  The clock detection circuit 13 monitors the presence or absence of an SCK signal output from a monitoring target (for example, CPU) of the watchdog timer device 1 and controls the constant current source circuit 14. The monitoring target periodically outputs an SCK signal during normal operation.

  The reset signal generation circuit 12 issues a reset signal (RESET) based on the signal from the voltage monitoring circuit 11.

  In FIG. 1, Vdd indicates a voltage supplied from the power source to the watchdog timer device 1.

  SCK indicates a clock signal output from a target (for example, CPU) monitored by the watchdog timer device 1.

  Further, INH is a signal for switching the watchdog timer device 1 between valid and invalid, and is output from a CPU (not shown).

  The watchdog timer device 1 monitors the SCK signal. If the SCK signal is not input for a predetermined time (timeout time) or longer, the watchdog timer device 1 determines that the monitoring target is in an abnormal state and outputs a reset signal (RESET) for resetting the system. Issue.

  FIG. 2 shows the operation of the conventional watchdog timer device 1.

  Vdd indicates a voltage supplied from the power source to the watchdog timer device 1.

  + Vdet indicates a lower limit voltage when the watchdog timer device 1 starts operating normally, and -Vdet indicates an upper limit voltage when the watchdog timer device 1 stops operating.

  Vinh represents the voltage of the INH signal. Here, it is described that the watchdog timer device 1 is valid at the H level and invalid at the L level.

  When the watchdog timer device 1 is invalidated, the reset signal generation circuit 12 does not issue a reset signal even if Vct described later falls below VctL.

  When Vinh becomes L level, the capacitor Ct is discharged by a system (not shown) short-circuited to GND, and Vct becomes GND level.

  Vct represents a voltage applied to the capacitor unit 15.

  VctH is a threshold value at which the capacitor Ct starts discharging, and VctL indicates a threshold value at which a reset signal is issued.

  Vsck indicates the voltage of the SCK signal output from the monitoring target (for example, CPU). Here, the rising edge is described as valid.

  Vreset indicates the voltage of the reset signal (RESET). Here, the H level is described as a reset release state (the system is not reset), and the L level is described as a reset state (the system is reset).

  Note that the fact that Vreset becomes L level is also expressed as issuing a reset signal.

  Next, the operation of the conventional watchdog timer device 1 will be described with reference to FIG.

  First, when Vdd is supplied to the watchdog timer device 1 and Vdd exceeds + Vdet, the constant current source circuit 14 starts charging the capacitor Ct, and the watchdog timer device 1 starts operating (T1).

  When the capacitor Ct is charged and Vct reaches VctH, charging to the capacitor Ct is stopped and the capacitor Ct starts discharging (T2).

  At the same time, when Vct reaches VctH, the reset signal generation circuit 12 sets Vreset to the H level and sets the reset release state.

  A monitoring target (for example, CPU) periodically outputs an SCK signal. When the SCK signal is input before Vct reaches VctL, charging of the capacitor Ct is started by the constant current source circuit 14 (switching from discharging to charging). (T3).

  Thereafter, as described above, when Vct reaches VctH, charging of the capacitor Ct is stopped, and the capacitor Ct starts discharging.

  Here, when an abnormality occurs in the monitoring target (for example, CPU) and the SCK signal is not input to the clock detection circuit 13, the discharge is continued and Vct reaches VctL (T4).

  When Vct reaches VctL, it is determined that the monitoring target is abnormal, and the reset signal generation circuit 12 sets Vreset to L level and sets the reset state (resets the system).

  In such a watchdog timer device, in order to prevent an unintended system reset, it is necessary that the SCK signal is input to the clock detection circuit 13 before Vct reaches VctL.

  In other words, the SCK signal issuance period (hereinafter referred to as Tvsck) is longer than the time (timeout time) from when the previous SCK signal is input until Vct reaches VctL (timeout time) (Vct charging time + Vct discharging time (hereinafter referred to as Tvct)). Shortness (Tvct> Tvsck) is a necessary condition.

  Therefore, normally, the capacitance value of the capacitor Ct is optimally determined, and control is performed so that the SCK signal is output at an SCK signal issue cycle (Tvsck) corresponding to the capacitance value.

  Further, the conventional watchdog timer device can invalidate the watchdog timer device 1 by the INH signal. Specifically, as shown in FIG. 2, by setting Vinh to L level, the watchdog timer device 1 is invalidated (T5).

  When the watchdog timer device 1 is disabled, the capacitor Ct is completely discharged. At this time, even if Vct falls below VctL, the reset signal generation circuit 12 maintains Vreset at the H level.

  Further, when the watchdog timer device 1 is invalidated, the reset signal generation circuit 12 maintains Vreset at the H level even if the SCK signal is not input (T6).

  Thereafter, by setting Vinh to H level, the watchdog timer device 1 can be validated again (T7).

  In such a watchdog timer device, it is desired to quickly find an abnormality to be monitored, that is, to reduce the capacitance value of the capacitor unit 15 and to shorten the timeout time as much as possible.

  However, when a monitoring target (for example, a CPU) performs large-capacity data processing (for example, download of an OS), there is a state in which an SCK signal cannot be output in a normal issue cycle even in a normal operation.

  Therefore, it has been necessary to set a longer timeout time in consideration of large-capacity data processing so that an unintended system reset does not occur.

  On the other hand, in order to shorten the time-out time, there is a method of invalidating the watchdog timer device 1 by outputting an INH signal during large-capacity data processing.

  However, with this method, there are concerns such as forgetting to cancel the invalidation and the occurrence of an abnormality during the invalidation.

  In order to solve such a problem, in the watchdog timer described in Patent Document 1, an integration circuit including a resistor and a capacitor for setting a timeout time, a controlled device controlled by a monitoring target CPU, or the It has a sensor for detecting the driving state of the components constituting the controlled device, and a resistance value switching circuit for switching the resistance value of the integrating circuit in at least two stages based on the output of the sensor, and the timeout time can be changed. .

JP 2008-262443 A

  However, in the above-mentioned Patent Document 1, since the timeout time is changed based on the output of the sensor, the timeout time cannot be changed actively.

  Moreover, if the timeout time is set by the integration circuit as in Patent Document 1, the timeout time can be changed by switching the resistance value. In the case of a configured watchdog timer device, the time-out time must be changed by changing the capacitance value of the capacitor unit.

  Here, for example, as a method for changing the capacitance value of the capacitor unit, when a method is used in which a plurality of capacitors having different capacitance values are provided and the capacitors are switched as necessary, the switching destination capacitor has no charge, so switching is performed. At the moment, the voltage Vct applied to the capacitor section falls below VctL, and there is a problem that the system is reset unintentionally.

  Even when the capacitance value is changed by another method, similarly, the capacitance value of the capacitor portion and the charge are relatively changed, and the system is reset unintentionally due to Vct being lower than VctL. There is a fear.

  Accordingly, the present invention provides a watchdog timer device in which the timeout time can be changed while preventing an unintended reset in the watchdog timer device in which the timeout time is set by the capacitance value of the capacitor unit. And

The present invention provides a clock detection circuit that acquires a clock signal output from a monitoring target, a capacitor unit that sets a timeout time, a voltage monitoring circuit that monitors a voltage applied to the capacitor unit, and a capacitor unit. A constant current source circuit for supplying power with current and discharging power with a constant current from the capacitor unit; and a reset signal generating circuit for issuing a reset signal when a voltage applied to the capacitor unit falls below a threshold value; The watchdog timer device includes a control signal delay circuit that delays a control signal for changing the capacitance value of the capacitor unit, and the control signal delay circuit without passing through the control signal delay circuit. When a control signal is input and the control signal is input or stopped, the watchdog timer device is disabled for a predetermined period. And INH control circuit for reduction, based on a signal output from the control signal delay circuit, and the capacitance value changing circuit for changing the capacitance value of the capacitor portion,
The delay by the control signal delay circuit is performed so that the capacitance value of the capacitor unit is changed during a period when the watchdog timer device is invalidated based on the INH control circuit.

  According to the present invention, in the watchdog timer device in which the timeout time is set by the capacitance value of the capacitor unit, it is possible to change the timeout time while preventing an unintended reset.

Configuration diagram of a conventional watchdog timer device The figure explaining operation of the conventional watchdog timer device 1 is a configuration diagram of a watchdog timer device according to a first embodiment of the present invention. The figure explaining the subject when changing the capacity value of a capacitor part The figure explaining operation | movement of the watchdog timer apparatus concerning Example 1 of this invention. Configuration diagram of a watchdog timer device according to Embodiment 2 of the present invention The figure explaining operation | movement of the watchdog timer apparatus concerning Example 2 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  However, the following embodiments are described by exemplifying a watch dog timer device for embodying the technical idea of the present invention, and the present invention is intended to be specified to this watch dog timer device. The present invention can be applied equally to other watchdog timer devices without departing from the technical idea shown in the claims.

  FIG. 3 is a configuration diagram illustrating the configuration of the watchdog timer device 3 of the present invention.

  The watchdog timer device 3 includes a voltage monitoring circuit 11, a reset signal generation circuit 12, a clock detection circuit 13, a constant current source circuit 14, a capacitor unit 35, a capacitor addition circuit 36, an INH control circuit 37, and a control signal delay circuit 38. Is done.

  The same components as those of the watchdog timer device 1 in FIG.

  Note that INH in FIG. 3 is a signal for switching the watchdog timer device between valid and invalid as in FIG. 1, but is different from FIG. 1 in that it is based on a control signal and an INH control circuit 37 described later.

  The following description will be given on the assumption that the monitoring target of the watchdog timer device 3 is a CPU (not shown).

  The capacitor unit 35 includes a capacitor Ca and a capacitor Cb. The time-out time of the watchdog timer device 3 is determined based on the capacitance value of the capacitor unit 35.

  The capacitor Ca is connected to the constant current source circuit 14, and the capacitor Cb is connected to the constant current source circuit 14 via the capacitor addition circuit 36.

  The capacitor addition circuit 36 includes a switch that opens and closes the connection between the capacitor Cb and the constant current source circuit 14.

  The capacitor addition circuit 36 opens and closes the switch according to the control signal output from the CPU.

  When the switch included in the capacitor addition circuit 36 is closed, the capacitor Cb functions in addition to the capacitor Ca. Therefore, the capacitance value of the capacitor unit 35 increases and the timeout time becomes longer.

  The INH control circuit 37 is composed of a differentiation circuit composed of a capacitor and a resistor, and an FET.

  The INH control circuit 37 receives a control signal and functions to generate an INH signal (Vinh becomes L level) for a predetermined time from the rise of the control signal.

  Specifically, the differentiation circuit of the INH control circuit 37 detects the rise of the control signal, the output of the differentiation circuit is input to the gate of the FET, and the FET operates. While the FET is operating, Vinh becomes L level by the FET of the INH control circuit 37.

  Since the INH signal is based on the power supply voltage (Vdd), Vinh becomes H level when the watchdog timer device 3 is activated. However, by operating the FET and shorting the INH signal to GND, Vinh is reduced. L level can be set.

  That is, the watchdog timer device 3 is invalidated by the INH control circuit 37 for a predetermined time from the rise of the control signal.

  The control signal delay circuit 38 includes a delay circuit composed of a resistor and a capacitor, delays the control signal, and outputs the delayed control signal to the capacitor addition circuit 36.

  Here, the delay time of the control signal by the control signal delay circuit 38 is set to be shorter than the time during which the watchdog timer device 3 is invalidated by the INH control circuit 37.

  That is, while the watchdog timer device 3 is disabled, a control signal is output to the capacitor adding circuit 36, and the delay time is set so that the capacitance value of the capacitor unit 35 changes.

  As shown in FIG. 3, the control signal output from the CPU is branched and input to the INH control circuit 37 and the control signal delay circuit 38, respectively.

  Here, the problem of the present invention will be described with reference to FIG.

  FIG. 4 illustrates the operation of the watchdog timer apparatus when the INH control circuit 37 and the control signal delay circuit 38 are not provided in the watchdog timer apparatus of FIG.

  In FIG. 4, the control signal is a signal output from the CPU and is a signal for changing the capacitance value of the capacitor unit 35.

  Here, the capacitance value of the capacitor unit 35 is increased by closing the switch of the capacitor addition circuit 36 at the H level and causing the capacitor Cb to function.

  On the other hand, at the L level, the switch of the capacitor addition circuit 36 is opened and the capacitor Cb is not functioned.

  The capacitor in FIG. 4 indicates a functioning capacitor. If it is “Ca”. Only the capacitor Ca is functioning, and “Ca + Cb” indicates that the capacitor Ca and the capacitor Cb are functioning.

  In FIG. 4, when the CPU performs large-capacity data processing in a state where only the capacitor Ca is functioning, it is necessary to lengthen the timeout time in order to prevent unintended issuance of a reset signal.

  Therefore, the CPU outputs a control signal (Ty) before starting large-capacity data processing.

  Based on the control signal, the capacitor addition circuit 36 closes the switch of the capacitor addition circuit 36 to cause the capacitor Cb to function.

  Here, when the capacitor Cb is made to function, since the capacitor Cb has no electric charge, the voltage Vct applied to the capacitor portion is rapidly reduced to be lower than VctL and an unintended reset signal is issued (Tz).

  Therefore, in the present invention, by providing the INH control circuit 37 and the control signal delay circuit 38, an unintended reset signal issuance accompanying a change in the capacitance value of the capacitor unit 35 is prevented.

  FIG. 5 shows the operation of the watchdog timer device 3 of FIG.

  In FIG. 5, Vct indicates a voltage applied to the capacitor unit 35.

  During normal operation, no control signal is output from the CPU (L level), and only the capacitor Ca of the capacitor unit 35 functions.

  That is, the timeout time is set short, and when an abnormality occurs in the CPU and the SCK signal cannot be output, it is possible to quickly detect the abnormality and reset the system.

  During normal operation, if it is in a normal state, the CPU outputs an SCK signal at the issue cycle Tvcka. Since Tvcka is shorter than the timeout time based on the capacitor Ca, no reset signal is issued during normal operation.

  Here, when the CPU performs large-capacity data processing, the SCK signal issuance cycle becomes longer and Tvckb (Tvcka <Tvckb).

  Since Tvckb is longer than the timeout time based on the capacitor Ca, a reset signal is issued even if the operation is normal unless the timeout time is increased.

  Therefore, in the present invention, an unintended reset signal accompanying the change in the capacitance value of the capacitor unit 35 is prevented while changing the timeout time.

First, before starting large-capacity data processing, the CPU outputs a control signal to increase the timeout time (Ta). The control signal is preferably output by the hardware configuration of the CPU.

  The control signal output from the CPU is input to the INH control circuit 37 and the control signal delay circuit 38.

  When a control signal is input to the INH control circuit 37, the INH control circuit 37 makes Vinh L level for a predetermined time from the rise of the control signal, and the watchdog timer device 3 is invalidated (Ta to Tc). while).

  On the other hand, the control signal input to the control signal delay circuit 38 is delayed and output to the capacitor addition circuit 36. Here, the delay time by the control signal delay circuit 38 is Tb-Ta, which is shorter than the invalidation time (Tc-Ta) of the watchdog timer device 3.

  The capacitor addition circuit 36 causes the capacitor Cb to function by closing the switch based on the control signal output from the control signal delay circuit 38 (Tb).

  At this time, since Vinh is already at the L level, Vct is at the GND level.

  At the timing (Tb) when the capacitor Cb functions, the watchdog timer device 3 is invalidated and no reset signal is issued (Vreset maintains H level).

  Thereafter, when the invalidation time by the INH control circuit 37 elapses and Vinh becomes H level, charging of the capacitor unit 35 is started and the watchdog timer device 3 is validated (Tc).

  Thereby, the timeout time after Tc is longer than the timeout time before Ta and longer than Tvckb.

  Therefore, even if the CPU performs large-capacity data processing after Tc, the reset signal is not issued if the SCK signal is normally output in the Tvckb cycle.

  Further, when an abnormality occurs during large-capacity data processing and the SCK signal is not output, Vct falls below VctL and a reset signal is issued. That is, it is possible to find an abnormal state even during large-capacity data processing.

  When the large-capacity data processing ends and the output cycle of the SCK signal returns to Tvcka, the CPU stops outputting the control signal (Td).

  The capacitor adding circuit 36 delays the delay time by the control signal delay circuit 38 and opens the switch so that the capacitor Cb does not function (Te).

  As a result, the time-out period is shortened, and the watchdog timer device 3 is in a state where it can quickly determine whether the CPU is abnormal.

  In FIG. 5, the watchdog timer device 3 is invalidated only for a predetermined time from the rise of the control signal by the INH control circuit 37, and is not invalidated when the control signal falls.

  This is because, even when the capacitor Cb is not functioning, the capacitor Ca has already been charged, so there is no fear that Vct will decrease rapidly.

  The watchdog timer device 3 may be invalidated for a predetermined time from the falling edge of the control signal by the INH control circuit 37. In this case, the capacitor Cb may be disabled. The watchdog timer device 3 is invalidated.

  As described above, according to the present invention, in the watchdog timer device 3 in which the time-out time is determined based on the capacitance value of the capacitor unit 35, by providing the INH control circuit 37 and the control signal delay circuit 38, an unintended reset signal can be generated. It is possible to change the timeout period while preventing issuance.

  Accordingly, even if the monitoring target (CPU) has a long output cycle of the SCK signal due to large-capacity data processing or the like, it is possible to prevent an unintentional reset signal from being issued.

  Further, the watchdog timer device 3 is invalidated by the INH control circuit 37 only for a predetermined time from the rising edge of the control signal, so that it is not forgotten to cancel the invalidation.

  Next, a second embodiment of the present invention will be described with reference to FIG.

  In the second embodiment, the case where the capacitance value of the capacitor unit is changed by switching the capacitor of the capacitor unit will be described.

  FIG. 6 is a block diagram illustrating the configuration of the watchdog timer device 6 of the present invention.

  The watchdog timer device 6 includes a voltage monitoring circuit 11, a reset signal generation circuit 12, a clock detection circuit 13, a constant current source circuit 14, a capacitor unit 65, a capacitor switching circuit 66, an INH control circuit 67, and a control signal delay circuit 38. Is done.

  Here, with respect to the same configuration as the watch dog timer device of FIG. 1 or FIG.

  The following description will be given on the assumption that the monitoring target of the watchdog timer device 6 is a CPU (not shown).

  The capacitor unit 65 includes a capacitor Ca and a capacitor Cb. The time-out time of the watchdog timer device 6 is determined based on the capacitance value of the capacitor unit 65.

  The INH control circuit 67 is constituted by a rising / falling detection circuit to which an integrating circuit composed of a resistor and a capacitor is applied.

The INH control circuit 67 receives a control signal and functions to generate an INH signal (Vinh becomes L level) for a predetermined time from the rise and fall of the control signal.
Specifically, when the control signal is switched from the L level to the H level, the INH control circuit 67 detects the rising edge of the control signal, outputs the L level for a certain time, and invalidates the watchdog timer device 3. After a predetermined time has elapsed, the output of the INH control circuit 67 becomes H level and the watchdog timer device 3 is enabled. Similarly, when the control signal is switched from the H level to the L level, the falling edge of the control signal is detected and the L level is output for a predetermined time to invalidate the watchdog timer device 3. After a predetermined time has elapsed, the output of the INH control circuit 67 becomes H level and the watchdog timer device 3 is enabled.

  In other words, the INH control circuit 67 invalidates the watchdog timer device 3 for a predetermined time after the rising edge of the control signal and for a predetermined time after the falling edge of the control signal.

  Capacitor Ca and capacitor Cb are connected to constant current source circuit 14 via capacitor switching circuit 66.

  The following description will be made assuming that the capacitance value of the capacitor Cb is larger than the capacitance value of the capacitor Ca.

  The capacitor switching circuit 66 includes a switch that opens and closes the connection between the capacitor Ca or the capacitor Cb and the constant current source circuit 14.

  The capacitor switching circuit 66 opens and closes the switch according to the control signal output from the control signal delay circuit 38.

  The capacitance value of the capacitor unit 65 is larger and the timeout time is longer when the capacitor Cb is functioning than when the capacitor Ca is functioning due to the switch of the capacitor switching circuit 66.

  In the second embodiment, the capacitor switching circuit 66 causes the capacitor Cb to function when the control signal is output (H level), and causes the capacitor Ca to function when it is not output (L level). Perform switching.

  FIG. 7 shows the operation of the watchdog timer device 6 of FIG.

  The same components as those in the operation explanatory diagram of FIG.

  First, before starting large-capacity data processing, the CPU outputs a control signal to increase the timeout time (Ta).

  The control signal output from the CPU is input to the INH control circuit 67 and the control signal delay circuit 38.

  When a control signal is input to the INH control circuit 67, the INH control circuit 67 causes Vinh to become L level for a predetermined time from the rise of the control signal, and the watchdog timer device 6 is invalidated (Ta to Tc). while).

  On the other hand, the control signal input to the control signal delay circuit 38 is delayed and output to the capacitor switching circuit 66.

  The capacitor switching circuit 66 switches the connection from the capacitor Ca to the capacitor Cb based on the control signal (Tb).

  At this time, since Vinh is already at the L level, Vct is at the GND level.

  At the timing (Tb) when the capacitor Cb functions, the watchdog timer device 6 is invalidated and no reset signal is issued (Vreset maintains H level).

  Thereafter, when the invalidation time by the INH control circuit 67 elapses and Vinh becomes H level, charging of the capacitor unit 65 is started, and the watchdog timer device 6 is validated (Tc).

  Thereby, the timeout time after Tc is longer than the timeout time before Ta and longer than Tvckb.

  Therefore, even if the CPU performs large-capacity data processing after Tc, the reset signal is not issued if the SCK signal is normally output in the Tvckb cycle.

  Further, when an abnormality occurs during large-capacity data processing and the SCK signal is not output, Vct falls below VctL and a reset signal is issued. That is, it is possible to find an abnormal state even during large-capacity data processing.

  When the large-capacity data processing ends and the output cycle of the SCK signal returns to Tvcka, the CPU stops outputting the control signal (Td).

  The INH control circuit 67 detects the fall of the control signal, and the watchdog timer device 6 is invalidated (between Td and Tf) for a predetermined time from the fall of the control signal.

  The capacitor switching circuit 66 switches the connection from the capacitor Cb to the capacitor Ca after being delayed by the delay time by the control signal delay circuit 38 (Te).

  At this time, since Vinh is already at the L level, Vct is at the GND level.

  At the timing (Te) when the capacitor Ca functions, the watchdog timer device 6 is invalidated and no reset signal is issued (Vreset maintains H level).

  Thereafter, when the invalidation time by the INH control circuit 67 elapses and Vinh becomes H level, charging of the capacitor unit 65 is started and the watchdog timer device 6 is validated (Tf).

  As a result, the time-out time is shortened, and the watchdog timer device 6 is in a state where it can quickly determine whether the CPU is abnormal.

  As described above, according to the present invention, in the watchdog timer device 6 in which the timeout time is determined based on the capacitance value of the capacitor unit 65, by providing the INH control circuit 67 and the control signal delay circuit 38, an unintended reset signal can be generated. It is possible to change the timeout period while preventing issuance.

  The watchdog timer device of the present invention is useful for changing the timeout time.

1, 3, 6 Watchdog timer device 11 Voltage monitoring circuit 12 Reset signal generation circuit 13 Clock detection circuit 14 Constant current source circuit 15, 35, 65 Capacitor section 36 Capacitor addition circuit 37, 67 INH control circuit 38 Control signal delay circuit 66 Capacitor switching circuit

Claims (5)

A clock detection circuit for acquiring a clock signal output from the monitoring target;
The capacitor part which sets the timeout time,
A voltage monitoring circuit for monitoring the voltage applied to the capacitor unit;
A constant current source circuit for supplying power to the capacitor unit with a constant current, and discharging the power with a constant current from the capacitor unit;
A reset signal generation circuit for issuing a reset signal when the voltage applied to the capacitor section is equal to or lower than a threshold;
A watchdog timer device comprising:
The watchdog timer device is
A control signal delay circuit for delaying a control signal for changing the capacitance value of the capacitor unit;
An INH control circuit for invalidating the watchdog timer device for a predetermined period when the control signal is input without going through the control signal delay circuit and the control signal is input or stopped;
Based on the signal output from the control signal delay circuit, a capacitance value changing circuit that changes the capacitance value of the capacitor unit;
Have
During the period when the watchdog timer device is invalidated based on the INH control circuit, a delay by the control signal delay circuit is performed so that the capacitance value of the capacitor unit is changed.
Watchdog timer device. When the issuing period of the clock signal is increased, the capacitance value of the capacitor unit is changed to a large value, and when the issuing period of the clock signal is reduced, the capacitance value of the capacitor unit is changed to a small value.
The watch dog timer device according to claim 1. The control signal is output when a change in the issuing period of the clock signal is predicted,
The watchdog timer device according to claim 1 or 2. The capacitor unit has a plurality of capacitors,
The capacitance value changing circuit is composed of a switch that opens and closes the connection of the capacitor, and changes the capacitance value of the capacitor unit by changing the number of connections of the plurality of capacitors.
The watch dog timer device according to claim 1. The capacitor unit has two or more capacitors having different capacitance values,
The capacitance value changing circuit changes the capacitance value of the capacitor unit by changing the capacitor to function.
The watch dog timer device according to claim 1.

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