CN112701899B - Main controller starting circuit and method and electronic equipment - Google Patents

Main controller starting circuit and method and electronic equipment Download PDF

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Publication number
CN112701899B
CN112701899B CN202011462351.6A CN202011462351A CN112701899B CN 112701899 B CN112701899 B CN 112701899B CN 202011462351 A CN202011462351 A CN 202011462351A CN 112701899 B CN112701899 B CN 112701899B
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circuit
output
power supply
controller
input
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CN112701899A (en
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姚秀军
桂晨光
许哲涛
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Jingdong Technology Information Technology Co Ltd
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Jingdong Technology Information Technology Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The utility model provides a main controller start-up circuit, a method and an electronic device, wherein the main controller start-up circuit comprises: the power input circuit is used for providing external power input; the controller power supply is used for supplying power to the internal chip of the main controller after power is on; the power supply control signal generation circuit is connected with the output of the power supply input circuit and the input of the controller power supply and is used for controlling the electrification of the controller power supply; and the starting signal generating circuit is connected to the power supply output of the controller and is used for outputting a starting signal for triggering the starting of the main controller.

Description

Main controller starting circuit and method and electronic equipment
Technical Field
The present disclosure relates to the field of electronic technologies, and in particular, to a circuit and a method for starting up a main controller, and an electronic device.
Background
With the rapid development of artificial intelligence, automatic control, communication and computer technologies, electronic devices with human-computer interaction devices are widely used. For example, service robots having a human-computer interaction device are gradually present in crowded places such as shopping malls, station waiting halls, and hospital halls, and provide services such as guidance, question answering, and service introduction. The robot master controller is generally composed of a plurality of chips to realize complex tasks such as logic control, program scheduling, algorithm calculation and the like. When the robot main controller is started, the power-on sequence is required, the power-on sequence of the main controller is met, and the robot main controller can normally work on the premise. But currently, in order to simplify the use, the mode of directly powering on all the power is generally adopted.
In the course of implementing the disclosed concept, the inventors found that there are at least the following problems in the prior art:
1. when the system is started, direct power-on can not ensure that a power-on time sequence meets design requirements, and normal starting can be influenced if a time sequence error occurs during power-on;
2. the existing power-on mode starting circuit has uncontrollable time sequence and may cause transient logic output errors.
Disclosure of Invention
In view of the above, the present disclosure provides a circuit and a method for starting up a host controller, and an electronic device.
One aspect of the present disclosure provides a main controller boot starting circuit, including:
the power input circuit is used for providing external power input;
the controller power supply is used for supplying power to the internal chip of the main controller after power is on;
the power supply control signal generating circuit is connected with the output of the power supply input circuit and the input of the controller power supply and is used for controlling the electrification of the controller power supply; and
and the starting signal generating circuit is connected to the power supply output of the controller and is used for outputting a starting signal for triggering the starting of the main controller.
According to an embodiment of the present disclosure, the power control signal generation circuit includes:
the first delay circuit is connected to the output of the power input circuit and used for delaying a first time length to output a first control signal after the output voltage of the power input circuit meets a stable condition; and
and the first conduction control circuit is connected to the output of the power supply input circuit and the output of the first delay circuit, and controls the power-on of the controller power supply according to a first control signal.
According to an embodiment of the present disclosure, the first delay circuit includes:
and the positive input end of the first comparator is connected to the output of the power input circuit through a first resistor and is grounded through a first capacitor, and the negative input end of the first comparator is connected with a first reference voltage.
According to an embodiment of the present disclosure, the first conduction control circuit includes:
a first switch device, a third terminal of which is connected to an output of the first delay circuit, a first terminal of which is connected to an output of the power input circuit through a first branch circuit, and a second terminal of which is grounded, wherein the first terminal and the second terminal of the first switch device are turned on when the first delay circuit outputs a first control signal, and an output terminal of the first branch circuit outputs a second control signal; and
and a second switching device, wherein a first end of the second switching device is connected to an input of a controller power supply, a second end of the second switching device is connected to an output of the power input circuit, a third end of the second switching device is connected to an output end of the first branch circuit, and the first end and the second end of the second switching device are turned on when the first branch circuit outputs a second control signal.
According to an embodiment of the present disclosure, the first branch includes:
a second resistor having a first end connected to an output of the power input circuit; and
and a third resistor, wherein a first end of the third resistor is connected to a second end of the second resistor, and an output end of the first branch is disposed between the first end of the third resistor and the second end of the second resistor.
According to an embodiment of the disclosure, the first switch device is an NMOS transistor, a gate of the NMOS transistor is connected to an output of the first delay circuit, a drain of the NMOS transistor is connected to the second end of the third resistor, and a source of the NMOS transistor is grounded.
According to an embodiment of the present disclosure, the second switching device is a PMOS transistor, a gate of the PMOS transistor is connected to the output terminal of the first branch, a source of the PMOS transistor is connected to the output of the power input circuit, and a drain of the PMOS transistor is connected to the input of the controller power supply.
According to an embodiment of the present disclosure, the start signal generating circuit includes:
the second delay circuit is connected to the output of the controller power supply and is used for delaying a second time length to output a third control signal after the controller power supply is electrified; and
and a second on control circuit connected to an output of the second delay circuit and an output of the controller power supply, the second on control circuit generating the enable signal according to a third control signal.
According to an embodiment of the present disclosure, the second delay circuit includes:
and the positive input end of the second comparator is connected with a second reference voltage, and the negative input end of the second comparator is connected to the output of the controller power supply through a fourth resistor and is grounded through a second capacitor.
According to an embodiment of the present disclosure, the second conduction control circuit includes:
the signal duration determining circuit is connected with the output of the controller power supply and the output of the second delay circuit and is used for determining the duration of the starting signal;
and the logic gate circuit is used for outputting the starting signal, the input of the logic gate circuit is respectively connected with the output of the second delay circuit and the output of the signal duration determining circuit, the logic gate circuit starts to output the starting signal when the second delay circuit outputs the third control signal, and the starting signal output is ended according to the output signal of the signal duration determining circuit.
According to an embodiment of the present disclosure, the signal duration determination circuit includes:
a third comparator, wherein the reverse input end of the third comparator is connected with a third reference voltage, and the forward input end of the third comparator is connected to the output of the controller power supply through a fifth resistor and is grounded through a third capacitor; and
a third switching device, a first end of the third switching device is connected to the positive input end of the third comparator, a second end of the third switching device is grounded, a third end of the third switching device is connected to the output of the second delay circuit, and the third switching device is turned off after the second delay circuit outputs a third control signal, so that the third capacitor starts to be charged;
the logic gate circuit is an or gate, a first input end of the or gate is connected with the output of the second delay circuit, and a second input end of the or gate is connected with the output of the third comparator.
According to an embodiment of the present disclosure, the third switching device is an NPN transistor, a base of the NPN transistor is connected to the output of the second delay circuit, a collector of the NPN transistor is connected to the positive input terminal of the third comparator, and an emitter of the NPN transistor is grounded.
According to an embodiment of the present disclosure, the controller power supply is an internal power supply of the main controller.
According to another aspect of the present disclosure, there is provided a method of the host controller boot circuit as described above, including: the power supply control signal generation circuit delays a first time length to output a power supply control signal after the output voltage of the power supply input circuit meets a stable condition, and controls the power supply of the controller to be electrified; and after the controller power supply is electrified, delaying the second time length to output a starting signal for triggering the main controller to start, wherein the starting signal keeps the third time length.
According to another aspect of the present disclosure, there is provided an electronic device including the main controller power-on start circuit as described above.
According to the embodiment of the disclosure, the problem that normal startup is affected by a time sequence error when the main controller is directly powered on can be at least partially solved, and therefore, the technical effect of ensuring that the main controller completes power-on startup according to a design specification time sequence can be achieved.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:
FIG. 1 schematically illustrates a host controller boot sequence to which a host controller boot startup circuit may be applied, according to an embodiment of the disclosure.
Fig. 2 schematically shows a structural schematic diagram of a main controller power-on start circuit according to an embodiment of the present disclosure.
FIG. 3 schematically shows a circuit diagram of a host controller power-on startup circuit according to an embodiment of the present disclosure.
FIG. 4 schematically shows a timing diagram of a host controller power-on startup circuit according to an embodiment of the present disclosure.
FIG. 5 schematically illustrates a flowchart of a method of a host controller boot circuit, according to an embodiment of the disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It is noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of this specification and should not be interpreted in an idealized or overly formal sense.
Where a convention analogous to "at least one of A, B and C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B and C" would include but not be limited to systems that have a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.). Where a convention analogous to "A, B or at least one of C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B or C" would include but not be limited to systems that have a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.).
The embodiment of the present disclosure provides a main controller startup circuit, including: the power input circuit is used for providing external power input; the controller internal power supply is used for supplying power to the main controller internal chip after power is on; the power supply control signal generating circuit is connected with the output of the power supply input circuit and the input of the power supply in the controller and is used for controlling the electrification of the power supply in the controller; and the starting signal generating circuit is connected to the internal power output of the controller and is used for outputting a starting signal for triggering the starting of the main controller.
FIG. 1 schematically illustrates a host controller boot sequence to which a host controller boot startup circuit may be applied, according to an embodiment of the disclosure. The starting circuit of the main controller can be used for controlling the power-on sequence of the main controller of the service robot.
As shown in fig. 1, the main controller of the service robot in this embodiment starts a power-on timing diagram, when the main controller is powered on, after the external input power VIN is stabilized for t1 time, the internal power PWR of the controller starts to be powered on, after the PWR is powered on and stabilized for t2 time, the start signal PWRBTN is triggered to output a low level, and the PWRBTN output of the start signal needs to keep a low level at t3 time intervals. When the output voltage of the power input circuit is continuously greater than the preset voltage value for a certain time, the output voltage of the power input circuit can be determined to meet the stable condition.
The starting circuit for the main controller can ensure that the main controller completes power-on starting according to a design standard time sequence, namely, an internal power supply of the controller is powered on after external power supply is stable, a starting signal is generated after the internal power supply of the controller is powered on, and the starting signal triggers the main control chip to start. The starting circuit of the main controller can adjust the interval of the power-on sequence, so that the robot can work normally.
Fig. 2 schematically shows a structural diagram of a main controller boot startup circuit according to an embodiment of the present disclosure.
As shown in fig. 2, the main controller boot start circuit 100 includes a power input circuit 110, a controller internal power source 120, a power control signal generation circuit 130 and a start signal generation circuit 140. The power input circuit 110 is used to access an external power source, so as to provide an external power input. The controller internal power supply 120 is used for supplying power to the main controller internal chip after power-on. The power control signal generating circuit 130 is connected to the output of the power input circuit and the input of the controller internal power source, and is configured to control the power-on of the controller internal power source. The start signal generating circuit 140 is connected to the output of the power output and power input circuit inside the controller, and is used for outputting a start signal triggering the start of the main controller.
The power control signal generating circuit 130 includes a first delay circuit 131 and a first conduction control circuit 132. The first delay circuit 131 is configured to delay the first time period t1 to output the first control signal after the voltage output by the power input circuit is stabilized. Illustratively, the first delay circuit may employ an RC delay circuit or other types of delay circuits.
The first conduction control circuit 132 controls the power-on of the controller internal power supply according to a first control signal. Specifically, the first conduction control circuit includes a first switching device and a second switching device. Illustratively, the first switching device and the second switching device are MOS transistors, a first end of the first switching device is connected to the output of the power input circuit through a first branch, a second end of the first switching device is grounded, a control end of the first switching device is connected to the output of the first delay circuit, and the first end and the second end of the first switching device are turned on when the first delay circuit outputs a first control signal, so that the output end of the first branch outputs a second control signal. The on/off of the second switching device may be controlled by the second control signal.
A first end of the second switching device is connected to an input of the controller internal power supply, a second end of the second switching device is connected to an output of the power supply input circuit, a third end of the second switching device is connected to an output end of the first branch circuit, and the first end and the second end of the second switching device are turned on when the first branch circuit outputs the second control signal, so that the output of the power supply input circuit 110 is connected to the input of the controller internal power supply 120, and the controller internal power supply 120 completes power-up after the output of the power supply input circuit 110 stabilizes for the first time period t 1.
The start signal generating circuit 140 includes a second delay circuit 141 and a second conduction control circuit 142, where the second delay circuit 141 is configured to delay the second time period t2 to output a third control signal after the controller internal power supply is powered on. Illustratively, the second delay circuit 141 may employ an RC delay circuit or another type of delay circuit.
The second conduction control circuit 142 generates the enable signal according to a third control signal. Specifically, the second conduction control circuit 142 includes a signal duration determination circuit 1421 and a logic gate circuit 1422. The signal duration determining circuit 1421 is connected to the output of the controller internal power supply and the output of the second delay circuit, and is configured to determine the duration of the start signal.
The logic gate circuit 1422 is configured to output the start signal, an input of the logic gate circuit 1422 is connected to the output of the second delay circuit 141 and the output of the signal duration determining circuit 1421, respectively, and the logic gate circuit starts to output the start signal when the second delay circuit 141 outputs the third control signal and ends the start signal output according to the output signal of the signal duration determining circuit 1421.
FIG. 3 schematically shows a circuit diagram of a host controller power-on startup circuit according to an embodiment of the present disclosure. As shown in fig. 3, the device of the present invention comprises a comparator, a PMOS transistor, an NMOS transistor, an NPN transistor, a capacitor, a resistor, and an or gate.
Specifically, the first delay circuit comprises a comparator 1, wherein a positive input end of the comparator 1 is connected to the output of the power input circuit through a resistor R5 and is grounded through a capacitor C1, and a negative input end of the first comparator is connected to the output of the power input circuit through a resistor R3 and is grounded through a resistor R4. The first delay circuit realizes the t1 delay through an RC circuit formed by a resistor R5 and a capacitor C1.
The first branch circuit comprises a resistor R1 and a resistor R2 which are connected in series, the first end of the resistor R1 is connected with the output of the power input circuit, the first end of the resistor R2 is connected with the second end of the resistor R1, and the output end of the first branch circuit is arranged between the first end of the resistor R2 and the second end of the resistor R1.
The first switching device and the second switching device both adopt MOS tubes. The first switching device is an NMOS transistor, a gate of the NMOS transistor is connected to the output of the comparator 1, a drain of the NMOS transistor is connected to the second end of the resistor R2, and a source of the NMOS transistor is grounded. The second switch device is a PMOS tube, the grid electrode of the PMOS tube is connected with the output end of the first branch circuit, the source electrode of the PMOS tube is connected with the output end of the power input circuit, and the drain electrode of the PMOS tube is connected with the input end of the power supply in the controller.
The second delay circuit comprises a comparator 2, wherein a positive input end of the comparator 2 is connected to the output of the power input circuit through a resistor R6 and is grounded through a resistor R7. The inverting input terminal of the comparator 1 is connected to the output of the controller internal power supply through a resistor R8 and to ground through a capacitor C2. The second delay circuit realizes the t2 delay through an RC circuit formed by a resistor R8 and a capacitor C2.
The signal duration determining circuit in the second conduction control circuit comprises a comparator 3 and an NPN triode, wherein the reverse input end of the comparator 3 is connected to the output of the controller internal power supply unit through a resistor R10 and is grounded through a resistor R11, and the forward input end of the comparator 3 is connected to the output of the controller internal power supply through a resistor R9 and is grounded through a capacitor C3. The base electrode of the NPN triode is connected with the output of the comparator 2, the collector electrode of the NPN triode is connected with the positive input end of the comparator 3, and the emitting electrode of the NPN triode is grounded. The NPN transistor is turned on after the power input circuit is connected to an external power source, and then turned off when the output of the comparator 2 changes from high to low, so that the capacitor C3 starts to be charged.
The logic gate circuit is an or gate, a first input end of the or gate is connected with the output of the second delay circuit, and a second input end of the or gate is connected with the output of the third comparator. The logic gate is an or gate for outputting the low level of the third time period t3 as the enable signal PWRBTN.
FIG. 4 schematically shows a timing diagram of a host controller power-on startup circuit according to an embodiment of the disclosure. Referring to fig. 4, the operation principle of the main controller startup circuit is as follows:
the power input circuit inputs a power VIN, the capacitor C1 connected to the positive input terminal IN + of the comparator 1 starts to charge after the power-on, and when the voltage of the positive input terminal IN + of the comparator 1 is higher than the voltage of the negative input terminal IN-, the comparator 1 outputs a high level. The inverting input terminal of the comparator 1 is connected to a first reference voltage VIN
VIN-＝VIN*R4/(R3+R4)
After the power input is stabilized, the capacitor C1 starts to charge, and the charging time of the RC circuit is calculated, and a time interval of t1 is passed
t1＝R5*C1Ln(VIN/(VIN-VIN*R4/(R3+R4)))
The voltage at the positive input terminal IN + of the comparator 1 is greater than the voltage at the negative input terminal IN-, the comparator 1 outputs a high level, when the NMOS1 is turned on, the gate voltage VG of the PMOS1 is:
VG＝VIN*R2/(R1+R2)
the difference between the gate voltage and the source voltage of PMOS1 is:
VG-VS＝VIN*R1/(R1+R2)＜Vth
wherein, VthThe voltage difference is turned on for PMOS1, so that PMOS1 is turned on, i.e., the power-up of internal power PWR of the controller is completed after input power VIN completes t1 time.
After the internal power supply PWR of the controller is powered on, the capacitor C2 starts to charge, and the voltage of the positive input terminal IN + the input terminal of the comparator 2 is:
VCOMP2IN+＝VIN*R7/(R6+R7)
when the capacitor C2 starts to charge, the voltage at the inverting input terminal IN-of the comparator 2 is lower than the voltage at the inverting input terminal IN +, the comparator 2 outputs a high level, the transistor NPN1 is IN a conducting state, and the collector is at a low level, so that the comparator 3 outputs a low level, and the start signal PWRBTN output by the or gate is at a high level. With the charging of the capacitor C2, the voltage at the inverting input terminal IN-of the comparator 2 gradually increases, and after a time t2 elapses, the voltage at the inverting input terminal TN-of the comparator 2 exceeds the voltage at the forward input terminal IN + of the comparator 2, where t2 is:
t2＝R8*C2Ln(VIN/(VIN-VIN*R7/(R6+R7)))
at this time, the output of the comparator 2 changes from high to low, and the transistor NPN1 enters the off state. Since the output of the comparator 2 and the output of the comparator 3 are both low at this time, that is, the input terminal of the or gate 1 is both low, the enable signal PWRBTN output by the or gate enters a low state after a high state at time t1+ t 2.
When the output of the comparator 2 changes from high level to low level, the NPN1 enters an off state, the resistor R9 and the capacitor C3 form an RC delay circuit, the internal power supply PWR of the controller charges the capacitor C3 through the resistor R9, and the reverse input end voltage of the comparator 3 is
VCOMP3IN-＝VIN*R11/(R10+R11)
When t3 time interval has elapsed
t3＝R9*C3Ln(VIN/(VIN-VIN*R11/(R10+R11)))
At this time, the voltage at the forward input terminal of the comparator 3 is higher than that at the reverse input terminal, so that the comparator 3 outputs a high level, and positive logic appears at the input terminal of the or gate 1, so that the output becomes a high level. That is, the start signal PWRBTN output from the or gate 1 becomes high after maintaining the low level at t3 time interval, and the main controller completes the power-on sequence.
By adopting the main controller startup circuit shown in fig. 3, after the power supply VIN is stabilized for t1 time, the internal power supply PWR of the controller starts to be powered on, and after the power on of the PWRBTNPWR is completed and stabilized for t2 time, the startup signal PWRBTN changes to the high level after keeping the low level of the time interval t 3.
In addition, the starting current of the main controller can adjust the interval of the power-on time sequence, so that the robot can work normally. Wherein the first time length t1 is adjustable by the values of R3, R4, R5 and C1; the second duration t2 is adjustable by the values of R6, R7, R8, C2; the third duration t3 is adjustable by the values of R9, R10, R11, C3.
In yet another exemplary embodiment of the present disclosure, a method of the host controller boot startup circuit as described above is provided. FIG. 5 schematically illustrates a flowchart of a method of a host controller boot circuit, according to an embodiment of the disclosure. As shown in fig. 5, the method includes operations S510-S520. In operation S510, after the output voltage of the power input circuit meets the stable condition, the power control signal generation circuit delays a first time period t1 to output a power control signal, so as to control the power supply inside the controller to be powered on. In operation S520, after the power supply inside the controller is powered on, a second time delay t2 is used to output a start signal for triggering the main controller to start, and the start signal is maintained for a third time period t 3.
In yet another exemplary embodiment of the present disclosure, an electronic device is provided, which includes the main controller power-on start circuit according to the foregoing embodiments. The main controller comprises a plurality of chips and has a specific starting time sequence. Illustratively, the electronic device is a service robot.
Any of the modules according to embodiments of the present disclosure, or at least part of the functionality of any of them, may be implemented in one module. Any one or more of the modules according to the embodiments of the present disclosure may be implemented by being split into a plurality of modules. Any one or more of the modules according to the embodiments of the present disclosure may be implemented at least in part as a hardware circuit, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system on a chip, a system on a substrate, a system on a package, an Application Specific Integrated Circuit (ASIC), or may be implemented in any other reasonable manner of hardware or firmware by integrating or packaging the circuit, or in any one of three implementations, or in any suitable combination of any of the software, hardware, and firmware.
Those skilled in the art will appreciate that various combinations and/or combinations of features recited in the various embodiments and/or claims of the present disclosure can be made, even if such combinations or combinations are not expressly recited in the present disclosure. In particular, various combinations and/or combinations of the features recited in the various embodiments and/or claims of the present disclosure may be made without departing from the spirit or teaching of the present disclosure. All such combinations and/or associations are within the scope of the present disclosure.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (13)

1. A main controller start-up circuit comprises:
the power input circuit is used for providing external power input;
the controller power supply is used for supplying power to the main controller after power is on;
the power supply control signal generation circuit is connected with the output of the power supply input circuit and the input of the controller power supply and is used for controlling the electrification of the controller power supply; and
the starting signal generating circuit is connected to the power supply output of the controller and used for outputting a starting signal for triggering the starting of the main controller;
wherein the power control signal generation circuit includes:
the first delay circuit is connected to the output of the power input circuit and used for delaying a first time length to output a first control signal after the output voltage of the power input circuit meets a stable condition; and
the first conduction control circuit is connected to the output of the power supply input circuit and the output of the first delay circuit, and controls the power-on of the controller power supply according to a first control signal;
wherein the first conduction control circuit includes:
a third end of the first switching device is connected with the output of the first delay circuit, a first end of the first switching device is connected to the output of the power input circuit through a first branch circuit, a second end of the first switching device is grounded, the first end and the second end of the first switching device are conducted when the first delay circuit outputs a first control signal, and an output end of the first branch circuit outputs a second control signal; and
and the first end and the second end of the second switching device are conducted when the first branch circuit outputs a second control signal.
2. The host controller boot-up circuit of claim 1, wherein the first delay circuit comprises:
the positive input end of the first comparator is connected to the output of the power input circuit through a first resistor and is grounded through a first capacitor, and the reverse input end of the first comparator is connected with a first reference voltage.
3. The host controller boot-up circuit of claim 1, wherein the first branch comprises:
a first end of the second resistor is connected with the output of the power input circuit; and
and the first end of the third resistor is connected with the second end of the second resistor, and the output end of the first branch circuit is arranged between the first end of the third resistor and the second end of the second resistor.
4. The main controller power-on start-up circuit of claim 3, wherein the first switching device is an NMOS transistor, a gate of the NMOS transistor is connected to the output of the first delay circuit, a drain of the NMOS transistor is connected to the second end of the third resistor, and a source of the NMOS transistor is grounded.
5. The main controller power-on start-up circuit of claim 3, wherein the second switching device is a PMOS transistor, a gate of the PMOS transistor is connected to the output terminal of the first branch, a source of the PMOS transistor is connected to the output of the power input circuit, and a drain of the PMOS transistor is connected to the input of the controller power supply.
6. The host controller boot startup circuit of claim 1, wherein the startup signal generation circuit comprises:
the second delay circuit is connected to the output of the controller power supply and is used for delaying a second time length to output a third control signal after the controller power supply is powered on; and
and the second conduction control circuit is connected to the output of the second delay circuit and the output of the controller power supply, and generates the starting signal according to a third control signal.
7. The host controller boot-up circuit of claim 6, wherein the second delay circuit comprises:
and the positive input end of the second comparator is connected with a second reference voltage, and the negative input end of the second comparator is connected to the output of the controller power supply through a fourth resistor and is grounded through a second capacitor.
8. The host controller boot-up circuit of claim 6, wherein the second conduction control circuit comprises:
the signal duration determining circuit is connected with the output of the controller power supply and the output of the second delay circuit and is used for determining the duration of the starting signal;
and the logic gate circuit is used for outputting the starting signal, the input of the logic gate circuit is respectively connected with the output of the second delay circuit and the output of the signal duration determining circuit, the logic gate circuit starts to output the starting signal when the second delay circuit outputs the third control signal, and the starting signal output is finished according to the output signal of the signal duration determining circuit.
9. The host controller boot startup circuit of claim 8, wherein,
the signal duration determination circuit includes:
the reverse input end of the third comparator is connected with a third reference voltage, and the forward input end of the third comparator is connected to the output of the controller power supply through a fifth resistor and is grounded through a third capacitor; and
a third switching device, a first end of the third switching device is connected to the positive input end of the third comparator, a second end of the third switching device is grounded, a third end of the third switching device is connected to the output of the second delay circuit, and the third switching device is turned off after the second delay circuit outputs a third control signal, so that the third capacitor starts to be charged;
the logic gate circuit is an or gate, a first input end of the or gate is connected with the output of the second delay circuit, and a second input end of the or gate is connected with the output of the third comparator.
10. The main controller boot-up circuit of claim 9, wherein the third switching device is an NPN transistor, a base of the NPN transistor is connected to the output of the second delay circuit, a collector of the NPN transistor is connected to the positive input terminal of the third comparator, and an emitter of the NPN transistor is grounded.
11. The host controller power-on startup circuit of claim 1, wherein the controller power supply is an internal power supply of the host controller.
12. A method of a host controller boot-up circuit as claimed in any one of claims 1 to 11, comprising:
the power supply control signal generation circuit delays a first time length to output a power supply control signal after the output voltage of the power supply input circuit meets a stable condition, and controls the power supply of the controller to be powered on; and
and after the controller power supply is powered on, delaying the second time length to output a starting signal for triggering the main controller to start, wherein the starting signal keeps the third time length.
13. An electronic device comprising a master controller power-on startup circuit as claimed in any one of claims 1-11.
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