CN115453949A

CN115453949A - Time sequence control device and unmanned vehicle

Info

Publication number: CN115453949A
Application number: CN202211205207.3A
Authority: CN
Inventors: 许哲涛
Original assignee: Beijing Jingdong Qianshi Technology Co Ltd
Current assignee: Beijing Jingdong Qianshi Technology Co Ltd
Priority date: 2022-09-29
Filing date: 2022-09-29
Publication date: 2022-12-09
Also published as: WO2024066304A1

Abstract

The utility model provides a sequential control device and unmanned car can be applied to automatic driving technical field. The device comprises: the first voltage reduction module comprises a first power input end and a first power output end, the first power input end is configured to be connected with a power supply, and the first power output end is configured to be connected with a load switch; the first time delay module comprises a first signal input end and a first signal output end, the first signal input end is configured to be connected with the first power output end, and the first signal output end is configured to be connected with the second time delay module and the load switch respectively; and a second delay module comprising a second signal input configured to connect to the first signal output and a second signal output configured to connect to the deserializer.

Description

Time sequence control device and unmanned vehicle

Technical Field

The present disclosure relates to the field of automatic driving technologies, and more particularly, to a timing control device and an unmanned vehicle.

Background

With the rapid development of artificial intelligence, automatic control, communication and computer technologies, unmanned vehicles are increasingly used in many fields such as industrial and agricultural production, buildings, logistics, daily life and the like. However, along with the increasingly complex application environment and functions that need to be implemented, the types of sensors such as cameras that need to be integrated by the unmanned vehicle are increasing, and in order to simplify the line distribution of the unmanned vehicle, a Serial Link, such as a GMSL Link (Gigabit Multimedia Serial Link), is generally used in the related art to establish a communication connection between the processor and the camera of the unmanned vehicle.

In the related art, the driving control timing sequence is generally used to control the establishment of the serial link, but because the establishment of the serial link has strict requirements on the timing sequence, if the driving timing sequence is wrong, the establishment of the serial link may be realized, so that the processor cannot acquire the camera data. Therefore, the related art has at least a problem of poor reliability of the serial link.

Disclosure of Invention

In view of this, the present disclosure provides a timing control apparatus and an unmanned vehicle.

One aspect of the present disclosure provides a timing control apparatus including: a first voltage reduction module, including a first power input terminal and a first power output terminal, the first power input terminal being configured to be connected to a power supply, the first power output terminal being configured to be connected to a load switch, the first voltage reduction module being configured to supply power to a serial link via the load switch and a filter inductor in sequence, wherein one end of the serial link is configured to be connected to a deserializer via a first capacitor, and the other end of the serial link is configured to be connected to a camera module via a second capacitor; a first delay module, including a first signal input terminal and a first signal output terminal, where the first signal input terminal is configured to be connected to the first power output terminal, the first signal output terminal is configured to be connected to a second delay module and the load switch, respectively, and the first delay module is configured to provide a first enable signal to the load switch when a first voltage received by the first signal input terminal satisfies a first preset condition in a first time period, where the first enable signal is configured to control the load switch to be in an activated state; and the second delay module, including a second signal input terminal and a second signal output terminal, where the second signal input terminal is configured to be connected to the first signal output terminal, the second signal output terminal is configured to be connected to the deserializer, and the second delay module is configured to provide a second enable signal to the deserializer if a second voltage received by the second signal input terminal meets a second preset condition within a second time period, where the second enable signal is configured to control the deserializer to be in an activated state.

According to an embodiment of the present disclosure, the first delay module includes a voltage regulator tube, a first resistor, and a third capacitor; the anode of the voltage regulator tube is configured to be connected with the first signal input end, and the cathode of the voltage regulator tube is configured to be connected with one end of a first resistor; the other end of the first resistor is configured to be connected with the first signal output end; and one end of the third capacitor is configured to be connected to the first signal output terminal, and the other end of the third capacitor is configured to be grounded.

According to an embodiment of the present disclosure, the first preset condition indicates that the first voltage is greater than a breakdown voltage of the zener diode; the first voltage is configured to charge the third capacitor when the first voltage meets the first preset condition in the first period, and the third capacitor is configured to output the first enable signal through the first signal output terminal after the first period, wherein the voltage of the first enable signal is greater than the start threshold voltage of the load switch.

According to an embodiment of the present disclosure, the second delay module includes a first buffer, a second resistor, a fourth capacitor, and a second buffer; wherein an input terminal of the first buffer is configured to be connected to the second signal input terminal, and an output terminal of the first buffer is configured to be connected to one end of the second resistor; the other end of the second resistor is configured to be connected to the input end of the second buffer; one end of the fourth capacitor is configured to be connected to the input end of the second buffer, and the other end of the fourth capacitor is configured to be grounded; and an output of the second buffer is configured to be connected to the second signal output.

According to an embodiment of the present disclosure, the second preset condition indicates that the second voltage is greater than a threshold voltage of the first buffer; wherein, in a case that the second voltage satisfies the second preset condition within the second period, the second voltage is configured to charge the fourth capacitor, and the fourth capacitor is configured to output the second enable signal through the second buffer after the second period, wherein a voltage of the second enable signal is greater than a threshold voltage of the second buffer.

According to an embodiment of the present disclosure, the above apparatus further includes: a second voltage dropping module comprising a second power input terminal and a second power output terminal, the second power input terminal configured to be connected to the power supply, the second power output terminal configured to be connected to the deserializer.

According to an embodiment of the present disclosure, the apparatus further includes: and the singlechip comprises a first control end, and the first control end is configured to be connected with the first voltage reduction module through a third buffer and connected with the second voltage reduction module through a fourth buffer so as to respectively provide a first control signal for the first voltage reduction module and the second voltage reduction module.

According to the embodiment of the present disclosure, the single chip further includes a second control end, and the second control end is configured to output a camera synchronization pulse; the above-mentioned device still includes: the AND gate circuit comprises a first gate input end, a second gate input end and a gate output end; wherein the first gate input terminal is configured to be connected to the second control terminal to receive the camera synchronization pulse; the second gate input terminal is configured to be connected to the feedback terminal of the deserializer to receive a first level signal representing the state of the serial link; and said gate output is configured to be connected to a third control terminal of said deserializer; the and circuit is configured to perform a logic operation on the camera synchronization pulse and the first level signal to obtain a second level signal, and output the second level signal to the third control terminal.

Another aspect of the present disclosure provides an unmanned vehicle including: a chassis including a battery device and a power device; and an autopilot kit comprising a timing control device, a deserializer, a processor, and a camera module; wherein, the time sequence control device comprises: a first voltage reduction module including a first power input terminal and a first power output terminal, the first power input terminal being configured to be connected to the battery device, the first power output terminal being configured to be connected to a load switch, the first voltage reduction module being configured to supply power to a serial link via the load switch and a filter inductor in sequence, wherein one end of the serial link is configured to be connected to the deserializer via a first capacitor, and the other end of the serial link is configured to be connected to the camera module via a second capacitor; a first delay module, including a first signal input terminal and a first signal output terminal, where the first signal input terminal is configured to be connected to the first power output terminal, the first signal output terminal is configured to be connected to a second delay module and the load switch, respectively, and the first delay module is configured to provide a first enable signal to the load switch when a first voltage received by the first signal input terminal satisfies a first preset condition in a first time period, where the first enable signal is configured to control the load switch to be in an activated state; and the second delay module, including a second signal input terminal and a second signal output terminal, where the second signal input terminal is configured to be connected to the first signal output terminal, the second signal output terminal is configured to be connected to the deserializer, and the second delay module is configured to provide a second enable signal to the deserializer if a second voltage received by the second signal input terminal meets a second preset condition within a second time period, where the second enable signal is configured to control the deserializer to be in an activated state.

According to an embodiment of the present disclosure, the battery device includes a power supply and a power management module, the power supply is configured to supply power to the power device through the power management module and to supply power to the autopilot through the power management module; the camera module configured to acquire environmental information of the unmanned vehicle and transmit the environmental information to the processor; the processor configured to process the environmental information, generate a motion control signal, and transmit the motion control signal to the power plant; and the power device is configured to respond to the motion control signal to control the unmanned vehicle to move.

According to the embodiment of the disclosure, through the first time delay module, the load switch can be controlled to be turned on under the condition that the level state of the voltage output by the first voltage reduction module meets the first preset condition within the first time period; after the load switch is started, the serial link is powered on, correspondingly, the camera module is also powered on, the camera in the camera module starts to be started, and the camera is started in a second time period; and then the second time delay module can start the deserializer after the second time interval. The starting of the camera and the deserializer can be controlled to be carried out according to a normal time sequence through the arrangement of the first time delay module and the second time delay module, the starting time sequence control of the camera and the deserializer is realized by utilizing the logic of a hardware circuit, the dependence of the time sequence control of the camera starting on a driving control time sequence is reduced, and the reliability of a serial link of the camera is improved.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

fig. 1 schematically shows a drive control timing diagram of a setup process of a serial link in the related art.

Fig. 2 schematically illustrates a schematic diagram of a timing control apparatus according to an embodiment of the present disclosure.

Fig. 3 schematically illustrates a schematic diagram of a first voltage reduction module according to an embodiment of the disclosure.

Fig. 4 schematically illustrates a schematic diagram of a first latency module according to an embodiment of the disclosure.

Fig. 5 schematically illustrates a schematic diagram of a second latency module according to an embodiment of the present disclosure.

Fig. 6 schematically shows a schematic diagram of a timing control apparatus according to another embodiment of the present disclosure.

Fig. 7 schematically shows a schematic diagram of a timing control apparatus according to another embodiment of the present disclosure.

Fig. 8 schematically illustrates a schematic diagram of a timing control apparatus according to another embodiment of the present disclosure.

Fig. 9 schematically shows an operation timing diagram of a timing control apparatus according to another embodiment of the present disclosure.

Fig. 10 schematically illustrates a structural schematic of an unmanned vehicle according to an embodiment of the present disclosure.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that these descriptions are illustrative only and are not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.

All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It is noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of this specification and should not be interpreted in an idealized or overly formal sense.

Where a convention analogous to "at least one of A, B, and C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B, and C" would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). Where a convention analogous to "at least one of A, B, or C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B, or C" would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.).

The components such as the resistor and the capacitor mentioned in the circuit of the embodiment of the present disclosure may refer to a single component, or may be equivalent components formed by combining multiple components of the same type in a serial or parallel manner, and are not limited herein.

With the rapid development of artificial intelligence, automatic control, communication and computer technologies, unmanned vehicles are increasingly used in many fields such as industrial and agricultural production, construction, logistics, and daily life. However, along with the increasingly complex application environments and functions to be implemented, the types of sensors such as cameras that the unmanned vehicle needs to integrate are increasing, and in order to simplify the line distribution of the unmanned vehicle, a serial link, such as a GMSL link, is generally used in the related art to establish a communication connection between the processor and the camera of the unmanned vehicle.

The serial link generally includes a serializer and a deserializer, the serializer can be used at a transmitting end to convert an image collected by a camera into serial data and transmit the serial data by using the serial link, and the deserializer can be used at a receiving end to restore the serial data into parallel data, that is, into an original image.

Since the establishment of the serial link has strict requirements on the timing, in the related art, a strict driving control timing is generally set for the establishment process of the serial link.

As shown in fig. 1, the camera is powered by POC (Power over Coax). In the process of establishing the serial link, a deserializer power supply and a camera voltage stabilizing source need to be electrified at the moment t1, and the deserializer power supply and the camera voltage stabilizing source do not have the requirement of the sequence; after the camera voltage stabilizing source works stably, a camera load switch is powered on at the time t 2; after delaying for a period of time, pulling up a starting control end of the deserializer at the time t3 to enable the deserializer to enter a working state and trigger the establishment of a serial link; by time t4 GMSL link establishment is complete. A camera synchronization pulse may be input at time t5, and the camera may output a video signal according to a synchronization pulse period.

However, if the power-on timing does not meet the requirement, the serial link may be established in failure if the driving timing is wrong, so that the processor cannot acquire the camera data. For example, in the starting process of the deserializer, if the level of the start control signal drops, the serial link establishment will fail; for another example, a deserializer generally needs a period of time to establish a serial link after being powered on, and in the process, if a camera synchronization pulse occurs in the serial link, the serial link is failed to be established, and the camera is abnormally started. Therefore, the method of performing serial link establishment using the driving control timing may result in a decrease in reliability of the serial link.

In view of this, the embodiments of the present disclosure provide a timing control apparatus and an unmanned vehicle. The time sequence control device comprises a first voltage reduction module, a first time delay module and a second time delay module, the time sequence control device disclosed by the embodiment of the disclosure realizes the starting time sequence control of the camera and the deserializer by using the logic of a hardware circuit, reduces the dependence of the time sequence control of the camera starting on the driving control time sequence, and improves the reliability of the serial link of the camera.

Fig. 2 schematically shows a schematic diagram of a timing control apparatus according to an embodiment of the present disclosure.

As shown in fig. 2, the timing control apparatus may include a first voltage step-down module 100, a first time delay module 200, and a second time delay module 300.

According to an embodiment of the present disclosure, the first buck module 100 may include a first power input terminal Pin1 and a first power output terminal Pout1, the first power input terminal Pin1 may be configured to be connected to the power supply 400, and the first power output terminal Pout1 may be configured to be connected to the load switch 500.

According to an embodiment of the present disclosure, the first voltage-reducing module 100 may be configured to supply power to the serial link sequentially through the load switch 500 and the filter inductor L. The first buck module 100 may reduce the input voltage of the power supply 400 to a voltage suitable for serial link operation. One end of the serial link is configured to be connected to the deserializer 600 through the first capacitor C1, and the other end is configured to be connected to the camera module 700 through the second capacitor C2.

According to an embodiment of the present disclosure, in case of the deserializer 600 lacking the external power access, the first voltage dropping module 100 may also supply power to the deserializer 600 through the first power output terminal Pout1.

According to an embodiment of the present disclosure, the first time delay module 200 may include a first signal input terminal Sin1 and a first signal output terminal Sout1, the first signal input terminal Sin1 may be configured to be connected to the first power output terminal Pout1, and the first signal output terminal Sout1 may be configured to be connected to the second time delay module 300 and the load switch 500, respectively.

According to an embodiment of the present disclosure, the first time delay module 200 may be configured to provide a first enable signal to the load switch 500 in a case that the first voltage V1 received at the first signal input terminal Sin1 satisfies a first preset condition within a first period, and the first enable signal may be configured to control the load switch 500 to be in a start-up state. The first preset condition may be, for example, that the first voltage V1 is greater than a voltage threshold, and the first enable signal may be, for example, a level signal greater than a turn-on voltage of the load switch 500. Specifically, the first time delay module 200 may control the voltage of the first signal output terminal Sout1 to slowly rise after the first signal input terminal Sin1 receives the first voltage V1, or start to rise after a period of time, until the first enable signal output by the first signal output terminal Sout1 is greater than the turn-on voltage of the load switch 500.

According to an embodiment of the present disclosure, the second delay module 300 may include a second signal input terminal Sin2 and a second signal output terminal Sout2, the second signal input terminal Sin2 may be configured to be connected to the first signal output terminal Sout1, and the second signal output terminal Sout2 may be configured to be connected to the deserializer 600.

According to an embodiment of the present disclosure, the second delay module 300 may be configured to provide a second enable signal to the deserializer 600 if the second voltage V2 received at the second signal input terminal satisfies a second preset condition within a second period, wherein the second enable signal is configured to control the deserializer 600 to be in a startup state. The second preset condition may be, for example, that the second voltage V2 is greater than a voltage threshold, and the second enable signal may be, for example, a level signal greater than a start voltage of the deserializer 600. Specifically, the second delay module 300 may control the voltage of the second signal output terminal Sout2 to slowly rise after the second signal input terminal Sin2 receives the second voltage V2, or start to rise after a period of time, until the second enable signal output by the second signal output terminal Sout2 is greater than the start voltage of the deserializer 600.

According to the embodiment of the disclosure, through the first time delay module, the load switch can be controlled to be turned on under the condition that the level state of the voltage output by the first voltage reduction module meets the first preset condition within the first time period; after the load switch is turned on, the serial link is powered on, correspondingly, the camera module is also powered on, the camera in the camera module starts to be started, and the camera is started in a second time period; and then the second time delay module can start the deserializer after the second time interval. The starting of the camera and the deserializer can be controlled to be carried out according to a normal time sequence through the arrangement of the first time delay module and the second time delay module, the starting time sequence control of the camera and the deserializer is realized by utilizing the logic of a hardware circuit, the dependence of the time sequence control of the camera starting on a driving control time sequence is reduced, and the reliability of a serial link of the camera is improved.

The method shown in fig. 2 is further described with reference to fig. 3-5 in conjunction with specific embodiments.

According to an embodiment of the present disclosure, the first voltage-reducing module 100 may be a circuit module constructed based on any BUCK topology, or may be a circuit module constructed by a voltage-reducing chip, such as MAX20079, TPS54620, and peripheral circuits thereof, and is not limited herein. In the following embodiments, the structure of the first buck module 100 is described with reference to fig. 3 by taking a buck chip as an example.

As shown in fig. 3, the first buck module 100 may include a buck chip 110, an inductor Lb, resistors Rb1 and Rb2, and capacitors Cb1 and Cb2.

According to an embodiment of the present disclosure, the buck chip 110 may include at least an input terminal, an output terminal, an enable terminal, a feedback terminal, and other ports or pins. The input may be configured to be connected to a first power input Pin1 for receiving an input voltage from the power supply 400. The output terminal may be configured to be connected to the first power output terminal Pout1 through the inductor Lb. The inductor Lb may be used to provide a suitable operating frequency for the buck chip 110. The capacitors Cb1, cb2 may be configured to form a filter circuit for adjusting the frequency of the output voltage of the buck chip 110 and filtering out low-frequency noise. One end of the series resistors Rb1 and Rb2 may be configured to be connected to the first power output terminal Pout1, the other end may be configured to be grounded, and the feedback terminal may be configured to be connected between the resistor Rb1 and the resistor Rb2 to receive a divided voltage of the output voltage of the buck chip 110 with respect to the resistor Rb2, so as to determine the operating state of the buck chip 110. The enable terminal may be configured to be connected to an external control device for controlling the turn-on and turn-off of the buck chip 110.

As shown in fig. 4, the first delay module 200 may include a voltage regulator D, a first resistor R1, and a third capacitor C3.

According to an embodiment of the present disclosure, the anode of the zener diode D may be configured to be connected to the first signal input terminal Sin1, and the cathode of the zener diode D may be configured to be connected to one end of the first resistor R1.

According to an embodiment of the present disclosure, the other end of the first resistor R1 may be configured to be connected to the first signal output terminal Sout1.

According to an embodiment of the present disclosure, one end of the third capacitor C3 may be configured to be connected to the first signal output terminal Sout1, and the other end of the third capacitor C3 is configured to be grounded.

According to the embodiment of the present disclosure, the breakdown voltage of the zener diode D may be set according to a specific service scenario, for example, may be set to be half of the output voltage of the first voltage-reducing module 100.

According to the embodiment of the disclosure, when the first voltage V1 received by the anode of the voltage regulator tube D is less than the breakdown voltage of the voltage regulator tube D, the voltage regulator tube D exhibits a high resistance characteristic, that is, the current between the anode and the cathode of the voltage regulator tube D is close to zero. When the first voltage V1 is greater than the breakdown voltage of the zener diode D, the zener diode D exhibits a voltage stabilization characteristic, that is, the cathode voltage of the zener diode D is equal to the breakdown voltage of the zener diode D.

According to an embodiment of the present disclosure, the first preset condition may be expressed as the first voltage V1 being greater than a breakdown voltage of the zener. In a case that the first voltage V1 satisfies the first preset condition within a first time period, through the first signal input terminal Sin1, the first voltage-reducing module 100 may continuously charge the third capacitor C3 within the first time period, so that the voltage of the first signal output terminal Sout1 continuously increases until the voltage of the first signal output terminal Sout1 increases to be greater than the start threshold voltage of the load switch at the end of the first time period, that is, the third capacitor C3 is configured to output a first enable signal through the first signal output terminal Sout1 after the first time period, where the voltage of the first enable signal is greater than the start threshold voltage of the load switch.

According to the embodiment of the present disclosure, the first period may be determined by a resistance value of the first resistor R1, a capacitance value of the third capacitor C3, a breakdown voltage of the zener diode D, and a start threshold voltage of the load switch, as shown in formula (1):

in the formula (1), t1 represents a first period, R1 represents the resistance value of the first resistor R1, C3 represents the capacitance value of the third capacitor C3, v1 represents the breakdown voltage of the voltage regulator tube D, and vth1 represents the starting threshold voltage of the load switch.

According to the embodiment of the disclosure, through the arrangement of the first time delay module 200, the slow increase of the output voltage of the first signal output end can be realized by using the third capacitor C3 and the voltage regulator tube D, so that the purpose of controlling the load switch to delay the first time period and then electrify the load switch after electrifying is realized, and the reliability of the starting time sequence of the load switch is higher.

As shown in fig. 5, the second delay module 300 may include a first buffer Q1, a second resistor R2, a fourth capacitor C4, and a second buffer Q2.

According to an embodiment of the present disclosure, an input terminal of the first buffer Q1 may be configured to be connected to the second signal input terminal Sin2, and an output terminal of the first buffer Q1 may be configured to be connected to one end of the second resistor R2.

According to an embodiment of the present disclosure, the other end of the second resistor R2 may be configured to be connected to an input terminal of the second buffer Q2.

According to an embodiment of the present disclosure, one end of the fourth capacitor C4 may be configured to be connected to the input terminal of the second buffer Q2, and the other end of the fourth capacitor C4 is configured to be grounded.

According to an embodiment of the present disclosure, the output terminal of the second buffer Q2 is configured to be connected to the second signal output terminal Sout2.

According to the embodiment of the present disclosure, the first buffer Q1 and the second buffer Q2 may be constituted by any type of operational amplifier. The voltages of the input end and the output end of the first buffer Q1 and the second buffer Q2 can be equal, and the buffers can be used for isolating the two ends of the buffers to reduce the interference of the noise of the input end to the output end, and can also be used for enhancing the driving capability of the output end, namely the external power supply is used for improving the power of the output end.

According to the embodiment of the present disclosure, each of the first buffer Q1 and the second buffer Q2 may have a certain turn-on threshold voltage, that is, when the voltage of the input terminal of the buffer is less than the turn-on threshold voltage, the voltage of the output terminal of the buffer is close to zero, and when the voltage of the input terminal of the buffer is greater than or equal to the turn-on threshold voltage, the voltage of the output terminal of the buffer is equal to the voltage of the input terminal of the buffer.

According to an embodiment of the present disclosure, the second preset condition may be represented as the second voltage V2 being greater than the threshold voltage of the first buffer Q1. In the case that the second voltage V2 satisfies the second preset condition in the second period, after the second voltage V2 is boosted by the driving of the first buffer Q1, the second voltage V2 may be configured to charge the fourth capacitor C4, so that the fourth capacitor C4 continuously accumulates charges, which is represented by that the voltage at the input end of the second buffer Q2 continuously increases until the second period is ended, the voltage at the input end of the second buffer Q2 increases to be greater than the threshold voltage of the second buffer Q2, that is, the fourth capacitor C4 is configured to output a second enable signal through the second buffer Q2 after the second period, and the voltage of the second enable signal is greater than the threshold voltage of the second buffer.

According to an embodiment of the present disclosure, the second period may be determined by a resistance value of the second resistor R2, a capacitance value of the fourth capacitor C4, a voltage value of the second voltage V2, and a threshold voltage of the second buffer, as shown in equation (2):

in formula (2), t2 represents the second period, R2 represents the resistance value of the second resistor R2, C4 represents the capacitance value of the fourth capacitor C4, V2 represents the voltage value of the second voltage V2, and vth2 represents the threshold voltage of the second buffer.

According to the embodiment of the present disclosure, through the configuration of the second delay module 300 as described above, the second enable signal generated by the second delay module 300 may be output through the second signal output terminal Sout2 to provide a high-level signal to the start control terminal of the deserializer 600, so that the deserializer 600 starts to start after the first time period plus the second time period of power-on of the power supply, thereby ensuring the start timing sequence of the deserializer 600 and improving the reliability of the serial link.

Fig. 6 schematically illustrates a schematic diagram of a timing control apparatus according to another embodiment of the present disclosure.

As shown in fig. 6, the timing control apparatus may further include a second voltage-decreasing module 800.

According to an embodiment of the present disclosure, the second voltage dropping module 800 may include a second power input terminal Pin2 and a second power output terminal Pout2, the second power input terminal Pin2 may be configured to be connected to the power supply 400, and the second power output terminal Pout2 may be configured to be connected to the deserializer 600.

According to an embodiment of the present disclosure, the second voltage-reducing module 800 may have the same or similar structure as the first voltage-reducing module 100, and the detailed description of the second voltage-reducing module 800 may refer to the description part of the first voltage-reducing module 100, which is not repeated herein.

According to an embodiment of the present disclosure, the second voltage-reducing module 800 may be used to replace an external power supply to supply power to the deserializer 600, so that the start control end of the deserializer 600 may control the deserializer 600 to start directly when receiving a high-level signal, thereby ensuring the reliability of the timing control.

As shown in fig. 7, the timing control apparatus may further include a single chip microcomputer 900.

According to the embodiment of the present disclosure, the single chip microcomputer 900 may include a first control terminal IO1, the first control terminal IO1 may be configured to be connected to the first voltage-reducing module 100 through the third buffer Q3, and to be connected to the second voltage-reducing module 800 through the fourth buffer Q4, specifically, an output terminal of the third buffer Q3 may be connected to an enable terminal of the first voltage-reducing module 100, and an output terminal of the fourth buffer Q4 may be connected to an enable terminal of the second voltage-reducing module 800, so as to provide the first control signal to the first voltage-reducing module 100 and the second voltage-reducing module 800, respectively.

According to an embodiment of the present disclosure, the first control signal may control the start and stop of the first voltage-reducing module 100 and the second voltage-reducing module 800 according to a preset level command rule. The preset level command rule may be, for example, high level start, low level stop, etc.

Fig. 8 schematically shows a schematic diagram of a timing control apparatus according to another embodiment of the present disclosure.

As shown in fig. 8, the timing control apparatus may further include an and gate circuit 1000.

According to an embodiment of the present disclosure, the and gate circuit 1000 may include a first gate input terminal Gin1, a second gate input terminal Gin2, and a gate output terminal Gout.

According to the embodiment of the present disclosure, the first gate input Gin1 may be configured to be connected to the single chip microcomputer 900, that is, the single chip microcomputer 900 may further include a second control terminal IO2, and the first gate input Gin1 may be configured to be connected to the second control terminal IO2.

According to an embodiment of the present disclosure, the single chip microcomputer 900 may be configured to output a camera synchronization pulse through the second control terminal IO2, and the first gate input terminal Gin1 may be configured to receive the camera synchronization pulse, which may be represented as a periodic signal formed by combining a high-level signal and a low-level signal.

According to an embodiment of the present disclosure, the second gate input Gin2 may be configured to be connected to the feedback terminal FB of the deserializer 600 to receive the first level signal indicating a state of the serial link, that is, a level state of the first level signal may be used to indicate whether the serial link has been completely established, for example, when the first level signal shows a high level state, it may be determined that the serial link has been completely established, and when the first level signal shows a low level state, it may be determined that the serial link has not been completely established, or the establishment has failed.

According to an embodiment of the present disclosure, the gate output Gout is configured to connect the third control terminal IO3 of the deserializer 600.

According to an embodiment of the present disclosure, the and circuit 1000 may be configured to perform a logic operation on the camera synchronization pulse and the first level signal to obtain the second level signal, and a truth table of the logic operation performed by the and circuit 1000 may be as shown in table 1, where "1" represents a high level state and "0" represents a low level state.

TABLE 1

Gin1	Gin2	Gout
				1	1	1
1	0	0
			0	1	0
0	0	0

According to the embodiment of the present disclosure, when the first level signal received by the second gate input terminal Gin2 is a low level signal, the second level signal output by the gate output terminal Gout is a low level signal; when the first level signal received by the second gate input terminal Gin2 is a high level signal, the second level signal output by the gate output terminal Gout is a camera synchronization pulse received by the first gate input terminal Gin 1.

According to the embodiment of the present disclosure, the second level signal may be input to the deserializer 600 through the third control terminal IO3, so that after the serial link is determined to be established, the camera synchronization pulse is loaded to the deserializer 600, thereby ensuring normal acquisition of an image acquired by the camera module 700, and improving reliability of the serial link.

As shown in fig. 9, when the camera module 700 needs to operate, the power-on timing of the camera module 700 may not be considered. At the time T1, the single chip microcomputer 900 may directly output a high level signal at the first control terminal IO1 and output a camera synchronization pulse at the second control terminal IO2. The high level signal output by the single chip microcomputer is input to the enabling ends of the first voltage reduction module 100 and the second voltage reduction module 800 through the buffer respectively, the first voltage reduction module 100 and the second voltage reduction module 800 start to work, the power supply 400 starts to supply power to the deserializer 600 through the second voltage reduction module 800, the voltage stabilizing source in the deserializer 600 is in a working state, at this moment, the deserializer 600 does not establish a serial link, namely does not enter a LOCK state, the voltage output by the feedback end of the deserializer 600 represents a serial link establishment identifier, and at this moment, the voltage is in a low level state. Although the first control terminal IO1 can output the synchronization pulse signal, the gate output terminal Gout of the and circuit 1000 outputs a low level signal because the other input terminal of the and circuit 1000 is in a low level state.

The first period may be represented as T2-T1, at time T2, the first voltage V1 completes charging the third capacitor C3, the load switch 500 enters the working state, the first voltage-reducing module 100 may supply power to the serial link through the load switch 500, and accordingly, the camera in the camera module 700 starts to start.

The second time period may be represented as T3-T2, and at time T3, the second voltage V2 completes charging the fourth capacitor C4, and the deserializer 600 enters an operating state to trigger the serial link to start building.

At time T4, the serial link establishment flag output by the feedback terminal of the deserializer 600 starts to be in a high level state, at this time, the output of the gate output terminal Gout of the and circuit 100 is equal to the output of the second control terminal IO2, that is, the gate output terminal Gout of the and circuit 100 starts to output the camera synchronization signal, so as to control the camera to normally operate.

According to the embodiment of the disclosure, based on the technical means, the dependence on the drive control time sequence can be reduced through hardware logic, the starting time sequence is ensured to meet the requirement of establishing the serial link, the reliability of the serial link of the camera is improved, and the camera can be normally started when being started every time.

As shown in fig. 10, the drone vehicle may include a chassis and an autopilot kit.

According to embodiments of the present disclosure, the chassis may include a battery device and a power device, and the autopilot kit may include a timing control device, a deserializer 600, a processor, and a camera module 700.

According to an embodiment of the present disclosure, the timing control apparatus may include a first voltage step-down module 100, a first time delay module 200, and a second time delay module 300.

According to an embodiment of the present disclosure, the first voltage-reducing module 100 may be configured to supply power to the serial link sequentially through the load switch 500 and the filter inductor L. One end of the serial link is configured to be connected to the deserializer 600 through the first capacitor C1, and the other end is configured to be connected to the camera module 700 through the second capacitor C2.

According to an embodiment of the present disclosure, the first delay module 200 may be configured to provide a first enable signal to the load switch 500 in a case that the first voltage V1 received by the first signal input terminal Sin1 satisfies a first preset condition within a first period, and the first enable signal may be configured to control the load switch 500 to be in an activated state.

According to an embodiment of the present disclosure, the second time delay module 300 may include a second signal input terminal Sin2 and a second signal output terminal Sout2, the second signal input terminal Sin2 may be configured to be connected to the first signal output terminal Sout1, and the second signal output terminal Sout2 may be configured to be connected to the deserializer 600.

According to an embodiment of the present disclosure, the second delay module 300 may be configured to provide a second enable signal to the deserializer 600 if the second voltage V2 received at the second signal input terminal satisfies a second preset condition within a second period, wherein the second enable signal is configured to control the deserializer 600 to be in a startup state.

According to an embodiment of the present disclosure, the battery device may include a power supply 400 and a power management module, the power supply 400 being configured to supply power to the power device through the power management module and to supply power to the autopilot kit through the power management module.

According to an embodiment of the present disclosure, the camera module 700 may be configured to acquire environment information of the unmanned vehicle and transmit the environment information to the processor.

According to an embodiment of the present disclosure, the processor may be configured to process the environmental information, generate a motion control signal, and transmit the motion control signal to the power plant.

According to embodiments of the present disclosure, the power plant may be configured to control the unmanned vehicle to move in response to a motion control signal.

It should be noted that, in the embodiment of the present disclosure, the timing control device portion of the unmanned vehicle corresponds to the timing control device portion in the embodiment of the present disclosure, and the description of the timing control device portion of the unmanned vehicle specifically refers to the timing control device portion, which is not described herein again.

Those skilled in the art will appreciate that various combinations and/or combinations of features recited in the various embodiments and/or claims of the present disclosure can be made, even if such combinations or combinations are not expressly recited in the present disclosure. In particular, various combinations and/or combinations of the features recited in the various embodiments of the present disclosure and/or the claims may be made without departing from the spirit and teachings of the present disclosure. All such combinations and/or associations are within the scope of the present disclosure.

The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the disclosure, and these alternatives and modifications are intended to fall within the scope of the disclosure.

Claims

1. A timing control apparatus, comprising:

a first voltage reduction module comprising a first power input terminal and a first power output terminal, the first power input terminal being configured to be connected to a power supply, the first power output terminal being configured to be connected to a load switch, the first voltage reduction module being configured to supply power to a serial link via the load switch and a filter inductor in sequence, wherein one end of the serial link is configured to be connected to a deserializer via a first capacitor, and the other end is configured to be connected to a camera module via a second capacitor;

a first time delay module including a first signal input terminal and a first signal output terminal, the first signal input terminal being configured to be connected to the first power output terminal, the first signal output terminal being configured to be connected to a second time delay module and the load switch, respectively, the first time delay module being configured to provide a first enable signal to the load switch when a first voltage received at the first signal input terminal satisfies a first preset condition within a first time period, wherein the first enable signal is configured to control the load switch to be in an activated state; and

the second delay module comprises a second signal input end and a second signal output end, the second signal input end is configured to be connected with the first signal output end, the second signal output end is configured to be connected with the deserializer, and the second delay module is configured to provide a second enabling signal to the deserializer when a second voltage received by the second signal input end meets a second preset condition in a second period, wherein the second enabling signal is configured to control the deserializer to be in an activated state.

2. The apparatus of claim 1, wherein the first delay module comprises a voltage regulator, a first resistor, and a third capacitor;

the anode of the voltage regulator tube is configured to be connected with the first signal input end, and the cathode of the voltage regulator tube is configured to be connected with one end of a first resistor;

the other end of the first resistor is configured to be connected with the first signal output end; and

one end of the third capacitor is configured to be connected to the first signal output end, and the other end of the third capacitor is configured to be grounded.

3. The apparatus of claim 2, wherein the first preset condition indicates that the first voltage is greater than a breakdown voltage of the zener;

wherein, in a case that the first voltage satisfies the first preset condition within the first period, the first voltage is configured to charge the third capacitor, and the third capacitor is configured to output the first enable signal through the first signal output terminal after the first period, wherein a voltage of the first enable signal is greater than a start threshold voltage of the load switch.

4. The apparatus of claim 1, wherein the second delay module comprises a first buffer, a second resistor, a fourth capacitor, and a second buffer;

wherein an input terminal of the first buffer is configured to be connected to the second signal input terminal, and an output terminal of the first buffer is configured to be connected to one terminal of the second resistor;

the other end of the second resistor is configured to be connected with the input end of the second buffer;

one end of the fourth capacitor is configured to be connected with the input end of the second buffer, and the other end of the fourth capacitor is configured to be grounded; and

an output of the second buffer is configured to be connected to the second signal output.

5. The apparatus of claim 4, wherein the second preset condition indicates that the second voltage is greater than a threshold voltage of the first buffer;

wherein, in a case that the second voltage satisfies the second preset condition within the second period, the second voltage is configured to charge the fourth capacitor, and the fourth capacitor is configured to output the second enable signal through the second buffer after the second period, wherein a voltage of the second enable signal is greater than a threshold voltage of the second buffer.

6. The apparatus of any of claims 1-5, further comprising:

a second voltage-dropping module comprising a second power input configured to connect to the power supply and a second power output configured to connect to the deserializer.

7. The apparatus of claim 6, further comprising:

the single chip microcomputer comprises a first control end, wherein the first control end is configured to be connected with the first voltage reduction module through a third buffer and connected with the second voltage reduction module through a fourth buffer so as to respectively provide a first control signal for the first voltage reduction module and the second voltage reduction module.

8. The apparatus of claim 7, wherein the single-chip further comprises a second control terminal configured to output a camera synchronization pulse;

the device further comprises:

the AND gate circuit comprises a first gate input end, a second gate input end and a gate output end;

wherein the first gate input terminal is configured to connect to the second control terminal to receive the camera synchronization pulse;

the second gate input terminal is configured to be connected to a feedback terminal of the deserializer to receive a first level signal representing a state of the serial link; and

the gate output terminal is configured to be connected to a third control terminal of the deserializer;

the AND gate circuit is configured to perform a logic operation on the camera synchronization pulse and the first level signal to obtain a second level signal, and output the second level signal to the third control terminal.

9. An unmanned vehicle comprising:

the chassis comprises a battery device and a power device; and

the automatic driving kit comprises a time sequence control device, a deserializer, a processor and a camera module;

wherein the timing control apparatus includes:

a first voltage reduction module comprising a first power input terminal and a first power output terminal, the first power input terminal configured to be connected to the battery device, the first power output terminal configured to be connected to a load switch, the first voltage reduction module configured to supply power to a serial link via the load switch and a filter inductor in sequence, wherein one end of the serial link is configured to be connected to the deserializer via a first capacitor, and the other end is configured to be connected to the camera module via a second capacitor;

a first delay module comprising a first signal input terminal and a first signal output terminal, the first signal input terminal being configured to be connected to the first power output terminal, the first signal output terminal being configured to be connected to a second delay module and the load switch, respectively, the first delay module being configured to provide a first enable signal to the load switch if a first voltage received at the first signal input terminal satisfies a first preset condition within a first time period, wherein the first enable signal is configured to control the load switch to be in an activated state; and

10. The unmanned vehicle of claim 9,

the battery device comprising a power source and a power management module, the power source configured to provide power to the power device via the power management module and to provide power to the autopilot kit via the power management module;

the camera module configured to acquire environmental information of the unmanned vehicle and transmit the environmental information to the processor;

the processor configured to process the environmental information, generate a motion control signal, and send the motion control signal to the power plant; and

the power plant configured to control the unmanned vehicle to move in response to the motion control signal.