Utility model content
In order to the deficiency in solving the problems of the technologies described above, the purpose of this utility model is: provide one to power on and power-off sequential control circuit, can solve the power supply sequence problem of the same voltage source of two-way, the different voltage source time-sharing power in a road and power-off.
The technical scheme that the utility model adopts for its technical problem of solution is:
Describedly to power on and power-off sequential control circuit, comprise first, second DC power supply, first, second delay circuit, first, second switching circuit, first, second discharge circuit and first, second feeder ear, the input of the first switching circuit directly connects the second DC power supply on the one hand, is connected, for receiving power supply on the other hand by the first delay circuit with the first DC power supply; The output of the first switching circuit is connected with second switch circuit by the second delay circuit on the one hand, another aspect respectively with first, second discharge circuit, the first feeder ear is connected; The input of second switch circuit is directly connected to the first DC power supply, and output is connected to the second feeder ear; First, second feeder ear is connected with first, second discharge circuit respectively.
The conducting that first delay circuit is mainly the first switching circuit provides certain time delay, and the conducting that the second delay circuit is mainly second switch circuit provides certain time delay; First discharge circuit is mainly the first feeder ear repid discharge and provides path, and the voltage of the first feeder ear is declined rapidly, and the second discharge circuit is mainly the first feeder ear repid discharge and provides path, and the voltage of the second feeder ear is declined rapidly.
Further preferably, the first delay circuit comprises the 3rd resistance and the first electric capacity, and the second delay circuit comprises the 11 resistance and the second electric capacity; First switching circuit mainly comprises the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the first resistance, the second resistance, the 4th resistance, the 5th resistance and the 6th resistance; Second switch main circuit will comprise the 4th metal-oxide-semiconductor, the 9th resistance, the tenth resistance and the 12 resistance; First discharge circuit mainly comprises the 7th resistance, the 8th resistance and the 3rd metal-oxide-semiconductor, and the second discharge circuit mainly comprises the 13 resistance and the 5th metal-oxide-semiconductor.
Further preferably, the grid of the first metal-oxide-semiconductor connects the first end of the 4th resistance, second end of the 4th resistance is connected the first DC power supply by the 3rd resistance with the series circuit of the first resistance on the one hand, pass through series circuit first capacity earth in parallel of the second resistance and the 3rd resistance on the other hand, the source ground of the first metal-oxide-semiconductor, the drain electrode of the first metal-oxide-semiconductor is connected the second DC power supply by the 5th resistance with the series circuit of the 6th resistance; The grid of the second metal-oxide-semiconductor connects the node between the 5th resistance and the 6th resistance, and the source electrode of the second metal-oxide-semiconductor connects the second DC power supply, and the drain electrode of the second metal-oxide-semiconductor connects the first feeder ear; The grid of the 3rd metal-oxide-semiconductor connects the drain electrode of the first metal-oxide-semiconductor by the 7th resistance, the direct ground connection of source electrode of the 3rd metal-oxide-semiconductor, and the drain electrode of the 3rd metal-oxide-semiconductor connects the first feeder ear by the 8th resistance; The grid of the 4th metal-oxide-semiconductor connects the first end of the 12 resistance, second end of the 12 resistance is connected the first feeder ear by the 11 resistance with the series circuit of the 9th resistance on the one hand, pass through series circuit second capacity earth in parallel of the 11 resistance and the tenth resistance on the other hand, the source electrode of the 4th metal-oxide-semiconductor connects the second feeder ear, and the drain electrode of the 4th metal-oxide-semiconductor connects the first DC power supply; The grid of the 5th metal-oxide-semiconductor connects the node between the grid of the 3rd metal-oxide-semiconductor and the 7th resistance, and the direct ground connection of source electrode of the 5th metal-oxide-semiconductor, the drain electrode of the 5th metal-oxide-semiconductor connects the second feeder ear by the 13 resistance.
Further preferably, the first metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor and the 5th metal-oxide-semiconductor are N channel enhancement metal-oxide-semiconductor, and the second metal-oxide-semiconductor is P-channel enhancement type metal-oxide-semiconductor.
Compared with prior art, the utility model has following beneficial effect:
The utility model circuit form is simple, cost is lower, be applicable to 20 to 70V DC power supply, can prevent from burning out chip, in addition, the function of the same voltage source of two-way, a different voltage source time-sharing power in road and power-off can also be realized, can be widely used on the power supply of the products such as Homeplug, there is higher practicality.
Embodiment
Below in conjunction with accompanying drawing, the utility model embodiment is described further:
Embodiment 1
As shown in Figure 1-2, described in the utility modelly to power on and power-off sequential control circuit, comprise first, second DC power supply, first, second delay circuit, first, second switching circuit, first, second discharge circuit and first, second feeder ear, the input of the first switching circuit directly connects the second DC power supply on the one hand, be connected with the first DC power supply by the first delay circuit, for receiving power supply on the other hand; The output of the first switching circuit is connected with second switch circuit by the second delay circuit on the one hand, another aspect respectively with first, second discharge circuit, the first feeder ear is connected; The input of second switch circuit is directly connected to the first DC power supply, and output is connected to the second feeder ear; First, second feeder ear is connected with first, second discharge circuit respectively; The conducting that first delay circuit is mainly the first switching circuit provides certain time delay, and the conducting that the second delay circuit is mainly second switch circuit provides certain time delay; First discharge circuit is mainly the first feeder ear repid discharge and provides path, and the voltage of the first feeder ear is declined rapidly, and the second discharge circuit is mainly the first feeder ear repid discharge and provides path, and the voltage of the second feeder ear is declined rapidly.
Wherein, the first delay circuit comprises the 3rd resistance R3 and the first electric capacity C1, and the second delay circuit comprises the 11 resistance R11 and the second electric capacity C2; First switching circuit mainly comprises the first metal-oxide-semiconductor VT1, the second metal-oxide-semiconductor VT2, the first resistance R1, the second resistance R2, the 4th resistance R4, the 5th resistance R5 and the 6th resistance R6; Second switch main circuit will comprise the 4th metal-oxide-semiconductor VT4, the 9th resistance R9, the tenth resistance R10 and the 12 resistance R12; First discharge circuit mainly comprises the 7th resistance R7, the 8th resistance R8 and the 3rd metal-oxide-semiconductor VT3, and the second discharge circuit mainly comprises the 13 resistance R13 and the 5th metal-oxide-semiconductor VT5; The grid of the first metal-oxide-semiconductor VT1 connects the grid of the 4th resistance R4, the source electrode of the 4th resistance R4 is connected the first DC power supply by the 3rd resistance R3 with the series circuit of the first resistance R1 on the one hand, on the other hand by the series circuit of the second resistance R2 and the 3rd resistance R3 the first electric capacity C1 ground connection in parallel, the source ground of the first metal-oxide-semiconductor VT1, the drain electrode of the first metal-oxide-semiconductor VT1 is connected the second DC power supply by the 5th resistance R5 with the series circuit of the 6th resistance R6; The grid of the second metal-oxide-semiconductor VT2 connects the node between the 5th resistance R5 and the 6th resistance R6, and the source electrode of the second metal-oxide-semiconductor VT2 connects the second DC power supply, and the drain electrode of the second metal-oxide-semiconductor VT2 connects the first feeder ear; The grid of the 3rd metal-oxide-semiconductor VT3 connects the drain electrode of the first metal-oxide-semiconductor VT1 by the 7th resistance R7, the direct ground connection of source electrode of the 3rd metal-oxide-semiconductor VT3, and the drain electrode of the 3rd metal-oxide-semiconductor VT3 connects the first feeder ear by the 8th resistance R8; The grid of the 4th metal-oxide-semiconductor VT4 connects the grid of the 12 resistance R12, the source electrode of the 12 resistance R12 is connected the first feeder ear by the 11 resistance R11 with the series circuit of the 9th resistance R9 on the one hand, on the other hand by the series circuit of the 11 resistance R11 and the tenth resistance R10 the second electric capacity C2 ground connection in parallel, the source electrode of the 4th metal-oxide-semiconductor VT4 connects the second feeder ear, and the drain electrode of the 4th metal-oxide-semiconductor VT4 connects the first DC power supply; The grid of the 5th metal-oxide-semiconductor VT5 connects the node between the grid of the 3rd metal-oxide-semiconductor VT3 and the 7th resistance R7, the direct ground connection of source electrode of the 5th metal-oxide-semiconductor VT5, and the drain electrode of the 5th metal-oxide-semiconductor VT5 connects the second feeder ear by the 13 resistance R13; First metal-oxide-semiconductor VT1, the 3rd metal-oxide-semiconductor VT3, the 4th metal-oxide-semiconductor VT4 and the 5th metal-oxide-semiconductor VT5 are N channel enhancement metal-oxide-semiconductor, and the second metal-oxide-semiconductor VT2 is P-channel enhancement type metal-oxide-semiconductor.
Second feeder ear, the first direct current power source voltage scope are 3V-5V, and the voltage of performance the best is+3.3V, and the second direct current power source voltage scope is 8V-18V, and the voltage of performance the best is+11.4V; 4th resistance R4 and the performance of the 7th resistance R7 to circuit play certain optimization function, can remove if desired.
In circuit, first resistance R1 and the second resistance R2 mainly carries out dividing potential drop to the first DC source, for the conducting of a N channel enhancement metal-oxide-semiconductor VT1 provides threshold grid voltage, 5th resistance R5 and the 6th resistance R6 mainly plays dividing potential drop effect, for the conducting of the second P-channel enhancement type metal-oxide-semiconductor VT2 provides grid threshold voltage, R5 plays the effect of pull-up resistor simultaneously, for a N channel enhancement metal-oxide-semiconductor VT1 provides one to determine level, the conducting that the 9th resistance and the tenth resistance are mainly the 4th N channel enhancement metal-oxide-semiconductor VT2 provides a grid threshold voltage.
Circuit working principle:
In the moment that the first DC power supply and the second DC power supply power on simultaneously, first electric capacity C1 two terminal shortcircuit, the grid voltage Va of a N channel enhancement metal-oxide-semiconductor VT1 pulled down to low level, now, grid and the source voltage of the one N channel enhancement metal-oxide-semiconductor VT1 are that 0, VT1 is in cut-off state, the grid voltage Vb of the second P-channel enhancement type metal-oxide-semiconductor VT2 is pulled upward to high level by the 5th resistance R5, now, the grid of the second P-channel enhancement type metal-oxide-semiconductor VT2 and source voltage are that 0, VT2 is in cut-off state, and corresponding 3rd N channel enhancement metal-oxide-semiconductor VT3 is also in cut-off state, the grid voltage Vd of the 4th N channel enhancement metal-oxide-semiconductor VT4 is pulled down to low level by R12, R11, R10, grid and the source voltage of the 4th N channel enhancement metal-oxide-semiconductor VT4 are 0,4th N channel enhancement metal-oxide-semiconductor VT4 is in cut-off state, and corresponding 5th N channel enhancement metal-oxide-semiconductor VT5 ends, because the second P-channel enhancement type metal-oxide-semiconductor VT2 and the 4th N channel enhancement metal-oxide-semiconductor VT4 is all in cut-off state, so the first feeder ear and the equal Non voltage output of the second feeder ear, along with the first electric capacity C1 constantly charges, voltage can constantly raise, when reaching the threshold voltage of a N channel enhancement metal-oxide-semiconductor VT1, one N channel enhancement metal-oxide-semiconductor VT1 conducting, now, the grid voltage Vc of the 3rd N channel enhancement metal-oxide-semiconductor is low level, 3rd N channel enhancement metal-oxide-semiconductor VT3 and the 5th N channel enhancement metal-oxide-semiconductor VT5 all ends, when the grid voltage of the second P-channel enhancement type metal-oxide-semiconductor reaches threshold voltage, second P-channel enhancement type metal-oxide-semiconductor VT2 conducting, now, first feeder ear output voltage, through the time delay of the second delay circuit, 4th N channel enhancement metal-oxide-semiconductor VT4 conducting after a period of time, second feeder ear output voltage, the upper order of power supply is the first DC source, first feeder ear, second feeder ear.
During power-off, first DC source, first feeder ear, second feeder ear voltage slowly declines, time below the threshold voltage that the first DC source voltage drops to a N channel enhancement metal-oxide-semiconductor VT1 conducting, one N channel enhancement metal-oxide-semiconductor VT1 ends, 3rd N channel enhancement metal-oxide-semiconductor VT3 and the 5th N channel enhancement metal-oxide-semiconductor VT5 conducting, first feeder ear and the second feeder ear are discharged by the 8th resistance R8 and the 13 resistance R13 rapidly respectively, because the second feeder ear is faster than the first feeder ear velocity of discharge, so the sequencing discharged during power-off is the second feeder ear, second feeder ear, first DC source, achieve the inverse time sequence that power-off sequential is electrifying timing sequence.
During application, can by arranging the 3rd resistance R3, the first electric capacity C1 and the 11 resistance R11, the second electric capacity C2 adjust the delayed time; In addition, also the power cut off delay time can be adjusted by arranging the 8th resistance R8 and the 13 resistance R13.
Embodiment 2
On the basis of embodiment 1, can metal-oxide-semiconductor be changed into triode.