CN111900792A

CN111900792A - Intelligent lock reset circuit and method for replacing physical keys

Info

Publication number: CN111900792A
Application number: CN202010815633.3A
Authority: CN
Inventors: 高威
Original assignee: Shenzhen Youlock Technologies Co ltd
Current assignee: Shenzhen Youlock Technologies Co ltd
Priority date: 2020-07-27
Filing date: 2020-08-14
Publication date: 2020-11-06

Abstract

The invention discloses an intelligent lock reset circuit and method for replacing a physical key, which trigger the hardware reset action of an intelligent lock by using a mode of accessing a general mobile power supply or a charger, and are used for taking measures for processing software and hardware abnormity which can not be automatically recovered and occurs in special conditions of the intelligent lock. The intelligent lock reset circuit replacing the physical key relates to modules including a main power supply, an emergency power supply, a main power supply isolation circuit, an emergency power supply isolation circuit, a discharge circuit, a delayed power-on circuit, a power supply management module, an MCU and other power utilization modules. All the modules cooperate with each other to act together to complete the hardware reset work of the intelligent lock according to the preset sequential logic.

Description

Intelligent lock reset circuit and method for replacing physical keys

Technical Field

The invention relates to a method for resetting an intelligent lock, in particular to a method for restoring hardware reset to a normal working state when the intelligent lock fails to correct automatically due to errors under a specific condition.

Background

With the wider and wider application of the intelligent lock, the requirement of a user on the reliability of the intelligent lock is higher and higher, and the requirement on fault recoverability is basically surpassed for general consumer electronics such as mobile phones, household appliances and the like. Therefore, equipment manufacturers are required to strictly control all links such as software and hardware research and development, production and manufacturing, installation and after-sale, the quality of products is improved, and the frequency of faults is reduced. But also prevent the electrostatic discharge phenomenon under extreme conditions, such as electron current impact in special occasions, strong electromagnetic interference environment, outdoor lightning impact, dry environment in winter in the north; in addition, the battery power is low, which can cause the abnormal operation of the lockset and can not be automatically recovered; and the other part is that the hardware state is abnormal due to the defect of the software, and the program runs away. In this case, the crystal oscillator may stop, the MCU (micro controller Unit) may not work, and when the measures such as hardware WatchDog and software exception interception cannot be effectively reset, the MCU needs to be powered off and restarted (unlike the patent of application No. CN201920832958.5, the MCU cannot send a reset signal to the reset circuit module). For safety reasons, the battery compartment is typically housed in the inner housing of the lock and the battery can only be removed from the door. If the door is opened, the door can be restarted by taking down the battery power supply and the like. However, if the door is locked outdoors and the battery cannot be removed, the door cannot be restarted in this manner. Most manufacturers have a reset switch in the hidden place of the lock casing for this situation, but this physical button will destroy the integrity of the lock appearance, and importantly will lower the expectation of the user on the product quality, and will create the illusion that the product is defective in user mind.

The invention introduces a reset method for replacing a physical reset key, which is triggered by an emergency power supply of an intelligent lock, is realized by a relevant switch circuit and a power-on circuit and a discharge circuit in the intelligent lock, and can restore and restart a lock in an abnormal state.

The invention utilizes an emergency power supply to trigger restarting, shares the common emergency power supply interface of the lockset, continues to use the interfaces of a Universal mobile power supply and a charger, namely a USB Micro-B interface or a Type-C interface (Universal Serial BUS), and preferentially uses the USB Type-C interface. The port is used by a plurality of mobile phones on the market, so that the emergency power supply has high availability.

When the system detects the insertion of the external emergency power supply, the main power supply is disconnected, then the power is discharged, and finally the emergency power supply is connected to power on the system, so that the lock is restarted.

Different from the patent application number of CN202010108631.0, according to the claim points 2, 3, 6 and 7 of the scheme, the standby power supply is arranged in the lock, and when the lock needs to be restarted, a special plug equipped with the lock is used for connecting the standby power supply to trigger; the special plug storage and acquisition mode is the same as that of a standby mechanical key of a common lock, and the functions are also overlapped (if the standby key is available, the lock can be unlocked, and then the battery is taken down in the door opening state, namely if the standby key is carried with a person, the lock can be restarted without carrying a special restarting plug), which is not convenient for acquiring a common mobile power supply or a charger used by the invention.

Unlike patent application No. CN202010108631.0, the embodiment of the present invention includes a main power supply and an emergency power supply isolation switch circuit. Because the types of the main power supply and the emergency power supply are different (the main power supply is generally 4 AA alkaline batteries, and the emergency power supply is generally a lithium battery), the power supply capacity and the internal resistance are different, the residual power is also different, and if no isolation circuit exists, the mutual interference can be caused, so that the conduction voltage of an output PMOS (P-channel Metal-Oxide-Semiconductor Field-Effect transistor, short for P-channel Metal-Oxide-Semiconductor Field-Effect transistor) can not be determined, and the power supply output is influenced. Thereby influencing the power supply of the lock and achieving the aim of restarting.

Unlike patent application No. CN202010108631.0, the embodiment of the present invention includes a discharge circuit. Normally, the lockset is taken as a battery power supply device, so that the battery endurance is very emphasized, all modules can sleep when the lockset does not work, and the dormancy current can be reduced to 10-20 uA; and when unblanking, want the actuating motor to unblank, audio module still drives loudspeaker sound production simultaneously, and operating current is great, can reach 200~300mA, and the electric current can be bigger in the twinkling of an eye, all can have great electric capacity to come the energy storage on the mainboard consequently. Therefore, after the power supply is disconnected, the voltage of the main board can be reduced under the action of the large capacitor for a period of time. If calculated in terms of a capacitance of two 470uF on board, the resting current 20uA and the battery compartment voltage 6V. For simplicity, during the discharge of the large capacitor, the system keeps the sleep state and the sleep current is constant, and the system can be simplified into an RC discharge circuit, so that the resistance R = U/I =6/20=0.3 megaohms, and according to the discharge formula of the RC circuit, the discharge time t can be shown in fig. 3,

wherein:

vc is the capacitor voltage

E is the supply voltage

Vc is then 4.3 volts-if the power module is a LDO (Low drop out Regulator Low Dropout Regulator), its minimum supply is 4.3 volts (as derived from the specification of the relevant devices, the operating voltage of the MCU is 3.3 volts, the minimum input voltage of the power module is 3.3 volts +1 volt =4.3 volts)

Then, as can be seen from the formula in fig. 3, the power module voltage decreases from 6 volts to 4.3 volts, and the required time t = -0.3 × 2 × 470 × ln (4.3/6) =94 seconds; that is, if the lock fails in the sleep state (the lock is in the sleep state for most of the time), the MCU is still powered up after 94 seconds of power off. Without a discharge circuit to speed up the discharge process, the restart time is too lengthy and unacceptable to the user.

Disclosure of Invention

The invention discloses a reset method for replacing a physical reset key. When the lockset is in failure, the intelligent lock is triggered by an emergency power supply, and the intelligent lock is realized by a relevant switch circuit and a power-on and discharge circuit inside the intelligent lock, and can be restored and restarted under the abnormal state.

The invention relates to a main module which comprises a main power supply, an emergency power supply, a reset module, a power supply management module and a power utilization module.

The main power supply related to the invention is arranged in an inner shell of the lock and generally consists of 4 AA alkaline batteries.

The emergency power supply is a universal mobile power supply or a charger baby and is arranged outside the lockset. A USB Micro-B or USB Type-C interface is reserved at a proper position of a shell of the lock, preferably a USB Type-C interface, an emergency power supply is connected into the lock through the interface, system resetting is completed, and power supply is provided for subsequent operation of the lock.

The power management module consists of a power management chip and a related circuit, and is used for providing adaptation of working voltage for other modules of the lockset and storing electric energy for driving the modules with high power consumption to work.

The invention relates to an electricity utilization module, which is a functional module required by the normal work of a lockset, such as an MCU (microprogrammed control Unit), a motor, an audio module and the like.

The reset module consists of a power isolation circuit, a discharge circuit and a delay power-on circuit.

The power isolation circuit comprises a main power isolation circuit and an emergency power isolation circuit.

The invention relates to a main power isolation circuit which comprises a PMOS (P-channel metal oxide semiconductor) tube, an NPN (Negative-Positive-Negative Bipolar Transistor) and two pull-down resistors thereof. The source electrode of the PMOS tube is connected with the positive electrode Vbatt of the main power supply, the drain electrode of the PMOS tube is connected with the voltage output end Vout, the grid electrode of the PMOS tube is grounded through a pull-down resistor, and the grid electrode of the PMOS tube is simultaneously connected with the emitter electrode of the NPN triode. The base electrode of the NPN triode is connected with the anode Vusb of the emergency power supply and is grounded through the pull-down resistor, the emitter electrode of the NPN triode is connected with the grid electrode of the PMOS tube, and the collector electrode of the NPN triode is connected with the anode Vbatt of the main power supply.

The invention relates to an emergency power supply isolation circuit which comprises a PMOS (P-channel metal oxide semiconductor) tube and a diode anode. The source electrode of the PMOS tube is connected with the anode Vusb of the emergency power supply, the drain electrode of the PMOS tube is connected with the voltage output Vout through a diode, and the grid electrode of the PMOS tube is connected with the collector electrode of the control triode of the delay electrifying circuit; and the grid electrode of the PMOS tube is connected with the anode Vusb of the emergency power supply through a pull-up resistor of a collector electrode of a control triode in the shared delay power-on circuit. The anode of the diode is connected with the drain of the PMOS tube, and the cathode of the diode is connected with the anode of the voltage output end Vout.

The discharge circuit related by the invention is composed of an NMOS (N-channel Metal-Oxide-semiconductor field-Effect Transistor) and a discharge resistor. The drain electrode of the NMOS tube is connected with the output end Vout of the power supply, the source electrode of the NMOS tube is grounded through the discharge resistor, and the grid electrodes of the NMOS tube and the discharge resistor are respectively connected with the grid electrode of the PMOS of the emergency power supply and the collector electrode of the control triode of the delay discharge circuit.

The invention relates to a delay power-on circuit which comprises a capacitor and a charging resistor thereof, and an NPN control triode and a pull-up resistor thereof. One electrode of the capacitor is grounded, the other electrode is connected with a charging resistor, and the charging resistor is connected with the anode of the emergency power supply Vusb. The other pole of the charging resistor is connected with the charging capacitor and simultaneously connected with the base electrode of the control triode, the emitting electrode of the control triode is grounded, and the collecting electrode is connected with the grid electrode of the PMOS tube of the emergency power isolation circuit and the grid electrode of the NMOS tube of the discharge circuit.

Drawings

FIG. 1 is a diagram of the reset module composition and relationship with other modules according to the present invention

FIG. 2 is a circuit diagram of a reset module according to the present invention

FIG. 3 shows the discharge time formula of RC circuit

Fig. 4 shows the charging time equation of the RC circuit.

Detailed Description

As shown in fig. 1, the system according to the present invention is composed of a reset module 10, a main power supply 11, an emergency power supply 12, a power management module 13, and other power utilization modules 14 such as an MCU.

The main power supply 11 according to the invention is placed in the inner housing of the lock, typically consisting of 4 AA alkaline batteries.

The emergency power supply 12 is a universal mobile power supply or a charger and is arranged outside the lockset. A USB Micro-B or USB Type-C interface, preferably a USB Type-C interface, is reserved at a proper position of a shell of the lock, and an emergency power supply 12 is connected into the lock through the interface to complete system resetting and provide emergency power supply for the MCU and other modules 14.

The power management module 13 provided by the invention consists of a power management chip and related circuits, provides adaptation of working voltage for other modules such as a lock MCU, a developed fingerprint head and the like, and uses a large-capacity capacitor to store electric energy for driving the module with high power consumption to work.

The reset module 10 according to the present invention is composed of a main power isolation circuit 101, an emergency power isolation circuit 102, a discharging circuit 103, and a delayed power-on circuit 104.

The power isolation circuit according to the present invention is divided into a main power isolation circuit 101 and an emergency power isolation circuit 102.

The main power isolation circuit 101 according to the present invention is composed of a PMOS Transistor 1011, an NPN Transistor 1012 (Negative-Positive-Negative Bipolar Transistor, referred to as NPN Transistor for short) and two pull-

down resistors

1013 and 1014. The source of the PMOS transistor 1011 is connected to the positive electrode Vbatt of the main power supply 11, the drain is connected to the positive electrode of the voltage output terminal Vout, the gate is grounded via a pull-down resistor 1013, the gate is connected to the emitter of the NPN transistor 1012, and the base of the NPN transistor 1012 is connected to the positive electrode Vusb of the emergency power supply and is grounded via a pull-down resistor 1014. Therefore, the voltage between the base electrode and the emitter electrode of the triode 1012 can be changed to control the conduction and the cut-off of the main power isolation PMOS pipe 1011, and further control the disconnection and the connection of the main power 11.

If the battery of the main power supply 11 is reversely connected by human error, the source voltage of the PMOS transistor 1011 is lower than the gate voltage, and is in an off state. Therefore, the PMOS transistor 1011 can also prevent the reverse connection of the battery and protect the MCU and other circuits from damage.

The emergency power isolation circuit 102 according to the present invention includes a PMOS transistor 1021 and an anode of a diode 1022. The anode of the diode 1022 is connected with the drain of the PMOS tube 1021, and the cathode of the diode is connected with the anode of the voltage output end Vout; the source of the PMOS transistor 1021 is connected to the positive terminal Vusb of the emergency power supply 12, and the gate of the PMOS transistor 1021 is connected to the collector of the control transistor 1043 of the delay power-up circuit 104.

If the control transistor 1043 is turned on according to the condition, the gate of the PMOS transistor 1021 is pulled low, and the PMOS transistor 1021 is turned on. Due to the unidirectional conductive property of the diode 1022, the emergency power supply 12 supplies power to the MCU and other power modules 14 through the PMOS transistor 1021 and the diode 1022.

The diode 1022 also has an important role in that the main power supply supplies power to the MCU and other power modules 14 when the emergency power supply is not plugged in. Without the isolation diode 1022, Vout will pull up the Vusb voltage through the parasitic diode of the PMOS transistor 1021 in the emergency power isolation circuit 12, and further pull up the base voltage of the control transistor 1012 in the main power isolation circuit, so that the PMOS transistor 1011 in the main power isolation circuit is disconnected, and the MCU and the power consumption module 14 will be in the no-power supply state. And by using the reverse cut-off characteristic of the diode 1022, Vusb is prevented from being influenced by Vout, and the normal operation of the control transistor 1012 and the PMOS transistor 1011 is ensured.

The discharge circuit 103 according to the present invention includes an NMOS 1031 (N-channel Metal-Oxide-Semiconductor Field-Effect Transistor, abbreviated as N-channel Metal-Oxide-Semiconductor Field-Effect Transistor) and a discharge resistor 1032. The drain of the NMOS tube 1031 is connected to the power output terminal Vout, the source is grounded through the discharging resistor 1032, and the gates are respectively connected to the gate of the PMOS tube 1021 of the emergency power supply and the delay discharging circuit 104. The delay discharge circuit can control the on/off of the discharge NMOS 1031, and then the discharge resistor 1032 discharges the charges remaining in the energy storage capacitor of the power management module 13.

The delay power-on circuit 104 according to the present invention is composed of a capacitor 1044 and a charging resistor 1041 thereof, and an NPN control transistor 1043 and a pull-up resistor 1042 thereof. One electrode of the capacitor 1044 is grounded, the other electrode is connected with the charging resistor 1041, and the charging resistor 1041 is connected with the anode Vusb of the emergency power supply 12.

The mechanism of the delayed power-on circuit 104 according to the present invention is that the voltage at the two ends of the charging capacitor 1044 does not suddenly change at once, the emergency power supply 12 charges the charging capacitor 1044 through the charging resistor 1041, when the voltage at the two ends of the charging capacitor 1044 is slowly raised, and when the threshold voltage for controlling the conduction of the triode 1043 is reached, the conduction of the triode 1043 is controlled, so as to control the on/off of the isolation PMOS transistor of the emergency power supply and the NMOS transistor 1031 of the discharging circuit.

The delay power-on time related to the present invention can be calculated according to an RC charging formula (as shown in fig. 4). The charging time t can be calculated through the capacitance value C of the charging capacitor, the resistance value R of the charging resistor, the voltage E of the emergency power supply and the voltage Vc to be reached by the charging capacitor in the formula. In general, the power supply voltage E and the charging power supply Vc are determined, and the capacitance value C of the charging capacitor and the resistance value R of the charging resistor can be changed to adjust the charging time t, so as to change the on-off time sequence of the isolation PMOS transistor 1021 and the discharging NMOS transistor 1031 of the emergency power supply.

The following states of the control triode and the MOS tube and the system power supply state are sequentially described through the following scenes:

a scene in which the main power supply 11 is switched on and the emergency power supply 12 is not switched on;

a scene when the main power supply 11 is switched on and the emergency power supply 12 is just switched on;

a main power supply 11 is switched on, an emergency power supply 12 is switched on for a period of time, and a system power supply is switched to a complete state;

a scene when the main power supply 11 is switched on and the emergency power supply 12 is unplugged;

when the main power supply 11 is unplugged and the power supply 12 is also unplugged.

In a scenario where the main power supply 11 is connected and the emergency power supply 12 is not connected:

in the main power isolation circuit, the base of the transistor 1012 is grounded through a pull-down resistor 1014, and the emitter is grounded through a pull-down resistor 1013, so that the voltage Ube between the base and the emitter of the transistor 1012 is zero, and the transistor operates in an off state. The grid electrode of the main power isolation circuit PMOS tube 1011 is grounded through the pull-down resistor 1013, the source electrode is the voltage of the main power 1011, the voltage Ugs between the grid electrode and the source electrode is greater than the threshold voltage of the MOS tube, and the PMOS tube 1011 is conducted at the moment;

the delay power-on circuit controls the triode 1043, and since the Vusb end is grounded through the resistor 1014, the base, the emitter and the collector are all low, and at this time, the triode is in a cut-off state; the voltage at the two ends of the charging capacitor is low, and no charge is distributed;

since the emergency power supply is not connected, the gate of the NMOS tube 1031 in the discharge circuit is grounded through the resistor 1042 and the resistor 1014, the source is grounded through the pull-down resistor 1032, and the NMOS tube 1031 is turned off at this time;

the source electrode of a PMOS tube 1021 in the emergency power supply isolation circuit is grounded through a pull-down resistor 1014, the grid electrode of the PMOS tube 1021 is grounded through

resistors

1042 and 1014, and the PMOS tube 1021 is cut off;

thus, in this scenario, MCU and other power modules 14 are powered by main power supply 11, and Vbatt voltage passes through PMOS transistor 1011 of main power isolation circuit 101 to output Vout.

When the main power supply 11 is connected, just plugged in the emergency power supply 12:

the base voltage of a control triode 1012 in the main power isolation circuit is Vusb, an emitter is grounded through a pull-down resistor 1014, the voltage is zero, the voltage between the base and the emitter of the triode 1012 is greater than a threshold voltage (the conduction threshold voltage of a general triode is 0.7V), and the triode 1012 is controlled to be conducted;

at this time, the grid electrode of the PMOS tube 1011 is connected to the positive electrode Vbatt of the main power supply through the triode 1012, and the source electrode is also connected to the positive electrode voltage Vbatt of the main power supply 11, so that the absolute value of the grid-source voltage Vgs of the PMOS tube 1011 is smaller than the threshold voltage of the conduction of the PMOS tube 1011, the conduction condition is not met, the PMOS tube 1011 is cut off, and the main power supply 11 is immediately disconnected;

since the emergency power supply 12 is just switched in, and the voltage at the two ends of the charging capacitor 1044 of the delay power-on circuit is still zero, the triode is controlled to be in a cut-off state;

the source electrode of a PMOS tube 1021 of the emergency power supply isolation circuit is connected to Vbatt, the source electrode is at a high level, the grid electrode is also at a high level through a pull-up resistor 1042, and the PMOS tube 1021 is cut off at the moment;

the grid of the NMOS tube 1031 of the discharge circuit is connected to Vbatt through a pull-up resistor 1042 and is at a high level, the source is grounded through a discharge resistor 1032, and the NMOS tube 1031 is turned on at this time;

therefore, in this scenario, the

PMOS transistors

1021 and 1011 are both turned off, and the main power supply and the emergency power supply are both turned off; the discharge NMOS tube is conducted, and charges stored in the power management module are rapidly released through the discharge NMOS tube and the discharge resistor 1032.

After the emergency power supply 12 is connected for a period of time, the emergency power supply charges the charging capacitor 1044 through the charging resistor 1041, and when the voltage at the two ends of the capacitor 1044 slowly rises to the conduction threshold voltage of the delay circuit control triode 1043, the triode 1043 is conducted; the gate of the PMOS transistor 1021 of the emergency power supply circuit is pulled down by the transistor 1043 to be at a low level, and the source is connected to the positive electrode Vusb of the emergency power supply to be at a high voltage, at this time, the PMOS transistor 1021 is turned on;

because the triode 1043 is controlled to be turned on, the grid electrode of the NMOS tube 1031 in the discharge circuit is also pulled down by the triode 1043 to be at a low level, the NMOS tube 1031 is grounded through the discharge resistor and is also at a low level, and at this time, the NMOS tube 1031 is cut off;

the control triode 1012 is conducted because the base electrode of the control triode is pulled high by Vusb, the grid electrode of the PMOS tube 1011 in the main power isolation circuit is connected to the positive end of the main power by the triode 1012 and is at high level, the source electrode is also connected to the positive end of the main power and is also at high level, and at the moment, the PMOS tube 1011 is cut off;

therefore, in this scenario, the MCU and other power modules 14 are powered by the emergency power supply 12, and the Vusb voltage passes through the PMOS transistor 1021 and the diode 1022 of the emergency power isolation circuit 102 to reach the output terminal Vout.

In the scenario of the previous paragraph, the system is powered by the emergency power supply 12, and when the emergency power supply 12 is unplugged:

the charging capacitor 1044 discharges through the

resistors

1041 and 1014, the voltage at the two ends of the capacitor 1044 slowly drops below the threshold voltage for controlling the conduction of the triode 1043, and the triode 1043 is cut off; the grid electrode of the PMOS tube 1021 in the emergency power supply isolation circuit is grounded through the resistor 1042 and the resistor 1014 and is at a low level, the source electrode of the PMOS tube 1021 is also grounded through the resistor 1014 and is also at a low level, and at the moment, the PMOS tube 1021 is cut off;

the grid electrode of the PMOS tube 1031 of the discharge circuit is at a low level like the grid electrode of the PMOS tube 1021, the source electrode is grounded through a resistor 1032 and is also at a low level, and at the moment, the NMOS tube 1031 is cut off;

the base voltage of the control triode 1012 in the main power isolation circuit is reduced along with the discharge of the capacitor 1044 and finally becomes low level, the emitter of the triode 1012 is grounded through the resistor 1013 and is also low level, and at this time, the triode 1012 is cut off; the gate of the PMOS transistor 1011 is grounded through the resistor 1013, and the source is connected to the positive electrode Vbatt of the main power supply 12, and is at a high level, at this time, the PMOS transistor 1011 is turned on;

after the emergency power supply 12 is pulled out, because the voltage Uc of the capacitor voltage 1044 is not high, the voltage drop of the PN junction of the base electrode and the emitter electrode of the control triode 1043 is 0.7v, and the anode of the emergency power supply is not pulled high, the source electrode and the grid electrode of the PMOS transistor 1021 immediately become low level and are immediately cut off; the same gate voltage of the NMOS 1031 is the divided voltage of the capacitor voltage Uc on the resistor 1014, which is less than 0.7v, so the NMOS 1031 is also cut off immediately; similarly, the base of the transistor 1012 is immediately at a low level due to the pull-up of the anode Vusb of the emergency power supply, the transistor 1012 is immediately turned off, and the PMOS transistor 1011 in the main power supply isolation circuit is immediately turned on to take over the emergency power supply to supply power to other power utilization modules 14 such as the MCU.

Therefore, after the emergency power supply 12 is unplugged, the main power isolation circuit 101 and the emergency isolation circuit 102 immediately operate, the switching channel continuously supplies power to other power utilization modules 14 such as the MCU, and the discharging circuit is disconnected, and in addition, under the action of the energy storage capacitor of the power management module 13, during the switching process, the voltage at the power output terminal Vout, which supplies power to other power utilization modules 14 such as the MCU, is substantially stable without fluctuation.

By integrating the above scenes, the lock is halted under special conditions, and after the emergency power supply 12 is inserted, the main power supply 11 is immediately disconnected through the main power supply isolation circuit 101; the emergency power supply 12 is under the action of the delayed power-on circuit 104, and the emergency power supply isolation circuit 102 is switched from an off state to an on state after a period of time; during this time period, the charge stored in the large capacitor of the power management module 13 will be discharged to ground through the discharging circuit 103; the voltage of the power output end Vout for supplying power to other power utilization modules 14 such as the MCU and the like is changed to zero through the voltage of the main power supply 11, and then is changed to the voltage of the emergency power supply 12 after a period of time; the length of this time period can also be adjusted within a certain range by changing the capacitance of the charging capacitor 1044 and the resistance of the charging resistor 1041; the requirement of simulating hardware keys by a system can be met, and the purpose of hardware resetting is achieved.

The technical principle of the present invention is described above in connection with specific embodiments. These descriptions are only intended to explain the invention

The principles, and not to be construed in any way as limiting the scope of the invention. Based on the explanations herein, the techniques of the art

Other embodiments of the invention will suggest themselves to persons of ordinary skill in the art without the need for inventive faculty, all of which will fall within the scope of the invention

The invention is within the scope of protection.

Claims

1. The intelligent lock reset method replacing the physical key is characterized in that a universal charger or a mobile power supply on the market is used for triggering hardware of the intelligent lock to restart, and special equipment or a device does not need to be restarted.

2. The intelligent lock reset method replacing the physical key is characterized in that when the intelligent lock is reset, the existing portable emergency power socket of the intelligent lock is used, a special reset key opening is not required to be arranged, and the appearance integrity of the shell of the intelligent lock is ensured.

3. The intelligent lock reset method replacing the physical key is characterized in that an isolating device is arranged for isolating mutual charging and discharging interference of a portable emergency power supply and a main power supply with different energy storage media, different internal resistances and different residual voltages.

4. The intelligent lock reset method replacing the physical key is characterized in that a discharge device is arranged and used for quickly releasing residual charges stored in an energy storage capacitor in the intelligent lock when a main power supply and an emergency power supply are switched.

5. The intelligent lock reset method replacing the physical key is characterized in that a delay power-on device is arranged, and when an emergency power supply is connected, the delay circuit controls the isolation circuit to delay for a period of time to be conducted to the power supply output end so as to be used by other power utilization modules.

6. The intelligent lock reset method replacing the physical key is characterized in that the time for conducting the emergency power supply is delayed, and the time can be adjusted by changing devices with different nominal values of an internal circuit so as to adapt to the requirements of different types of intelligent locks.

7. The intelligent lock reset circuit replacing the physical key relates to modules comprising a main power supply, an emergency power supply, a reset module, a power supply management module, an MCU and other power utilization modules; the reset module comprises an isolation circuit, a discharge circuit and a delay power-on circuit.

8. The intelligent lock reset circuit replacing the physical key is characterized by comprising a main power supply isolation circuit and an emergency power supply isolation circuit, wherein the main power supply isolation circuit and the emergency power supply isolation circuit cooperate with each other through a delay power-on circuit and a discharge circuit to jointly act to complete hardware reset logic.

9. The invention relates to an intelligent lock reset circuit for replacing a physical key, wherein a device for playing a switching role is characterized in that the on-off work of an internal module of an intelligent lock is completed.

10. The delayed power-on circuit of the intelligent lock reset circuit for replacing the physical key is characterized in that the emergency power supply is triggered to be conducted in a delayed mode.