CN107579562B - Mobile terminal and battery cell protection circuit - Google Patents
Mobile terminal and battery cell protection circuit Download PDFInfo
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- CN107579562B CN107579562B CN201710787845.3A CN201710787845A CN107579562B CN 107579562 B CN107579562 B CN 107579562B CN 201710787845 A CN201710787845 A CN 201710787845A CN 107579562 B CN107579562 B CN 107579562B
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Abstract
The invention discloses a mobile terminal and a battery cell protection circuit, wherein the battery cell protection circuit comprises a charge-discharge control circuit, a switch circuit and a trigger circuit; the charging and discharging control circuit comprises a control chip and a first control switch; one end of the first control switch is connected with the negative end of the battery cell, and the other end of the first control switch is connected with the negative output end P-; the control chip is connected with the battery cell in parallel, collects the working condition of the battery cell and controls the working state of the first control switch according to the working condition; the switch circuit receives the level signal and controls the working state of the first control switch according to the level signal; the trigger circuit is connected with the switch circuit, generates a level signal and sends the level signal to the switch circuit. According to the invention, the switch circuit and the trigger circuit are connected on the charge-discharge control circuit, the working state of the charge-discharge control circuit is controlled through the level signal sent by the trigger circuit, the battery cell is controlled to stop discharging through the trigger circuit, the battery is detached without disassembling the shell, and the operation of safety protection of a user on the mobile terminal is facilitated.
Description
Technical Field
The invention relates to the field of electronic equipment, in particular to a mobile terminal and a battery cell protection circuit.
Background
Along with the improvement of the performance and the function of mobile terminals such as smart phones, the requirements of people on the battery endurance time and the appearance are higher and higher, and in order to obtain longer endurance time under a thinner appearance, a plurality of mobile terminals adopt non-detachable built-in lithium batteries.
The detachable battery can be removed when the mobile phone is in a dead halt, the battery can be removed for activation when the mobile phone is overdischarged and can not be charged, but the non-detachable battery cannot be activated when the non-detachable battery has the same problem, some platforms have a function of resetting by pressing a Power-on key in a PMU (Power Management Unit), but sometimes the PMU has a problem and cannot function, particularly, the mobile terminals such as the mobile phone and the like are very hot, and users want to Power off as soon as possible, and the method cannot be used.
Disclosure of Invention
The invention mainly aims to provide a mobile terminal and a battery cell protection circuit which can actively realize battery protection without disassembling a battery.
In order to achieve the above object, the present invention provides a battery cell protection circuit, which includes a charge/discharge control circuit, a switch circuit, and a trigger circuit;
the charging and discharging control circuit comprises a control chip and a first control switch; one end of the first control switch is connected with the negative end of the battery cell, and the other end of the first control switch is connected with the negative output end P-; the control chip is connected with the battery cell in parallel, collects the working condition of the battery cell and controls the working state of the first control switch according to the working condition;
the switch circuit receives a level signal and controls the working state of the first control switch according to the level signal;
the trigger circuit is connected with the switch circuit, generates the level signal and sends the level signal to the switch circuit.
Further, the first control switch comprises a first NMOS transistor, a second NMOS transistor, a first parasitic diode, and a second parasitic diode;
the drain electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube; the grid electrode of the first NMOS tube is connected with the discharge control interface of the control chip, and the grid electrode of the second NMOS tube is connected with the charge control interface of the control chip; the source electrode of the first NMOS tube is connected with the negative electrode end of the battery cell, and the source electrode of the second NMOS tube is connected with the negative electrode output end P-.
Further, the switch circuit comprises a third NMOS tube, an electrode K, a first voltage-dividing resistor and a second voltage-dividing resistor;
the grid electrode of the third NMOS tube is connected with the electrode K, the source electrode of the third NMOS tube is connected with the negative electrode end of the battery cell, and the drain electrode of the third NMOS tube is connected with the grid electrode of the first NMOS tube;
the grid electrode of the first NMOS tube is connected with a discharge control interface of the control chip through the first divider resistor;
the electrode K is connected with the trigger circuit to receive the level signal;
the electrode K is connected with the negative electrode output end P < - > through the second voltage-dividing resistor.
Further, the second voltage-dividing resistor is a thermistor.
Further, the battery cell protection circuit further comprises a charging diode, wherein the anode of the charging diode is connected with the cathode end of the battery cell, and the cathode of the charging diode is connected with the electrode K.
Furthermore, a first capacitor is connected between the source electrode of the first NMOS tube and the source electrode of the second NMOS tube.
Furthermore, the electric core protection circuit further comprises a sampling resistor, one end of the sampling resistor is connected with the source electrode of the second NMOS tube, and the other end of the sampling resistor is connected with the sampling interface of the control chip.
Furthermore, the trigger circuit comprises a key, a first falling edge trigger single binary pulse counter, a second falling edge trigger single binary pulse counter and a delay reset time circuit;
the positive output end of the battery cell is respectively connected with the first falling edge trigger single binary pulse counter and the second falling edge trigger single binary pulse counter; the key is respectively connected with the first falling edge trigger single binary pulse counter and the second falling edge trigger single binary pulse counter; the first falling edge trigger single binary pulse counter is connected with the second falling edge trigger single binary pulse counter; the delay reset time circuit is respectively connected with the first falling edge trigger single binary pulse counter and the second falling edge trigger single binary pulse counter.
Further, the first falling edge triggered single binary pulse counter and the second falling edge triggered single binary pulse counter are both low-power-consumption D-type flip-flops.
The invention also provides a mobile terminal, which comprises a shell, a battery cell and a battery cell protection circuit, wherein the battery cell is arranged in the shell; the cell protection circuit is as described in any of the above.
According to the battery cell protection circuit, the switch circuit and the trigger circuit are connected to the charge and discharge control circuit, the working state of the charge and discharge control circuit can be controlled through the level signal sent by the trigger circuit, and the circuit is simple and practical; according to the mobile terminal, the battery core and the battery core protection circuit corresponding to the battery core are embedded in the shell, when the battery core cannot be detached conventionally, the battery core is halted, the battery is overheated and the like, the battery core can be controlled to stop discharging through the trigger circuit, the shell does not need to be detached, the battery is detached, and the operation of safety protection of a user on the mobile terminal is facilitated.
Drawings
Fig. 1 is a schematic block diagram of a structure of a cell protection circuit according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a charge/discharge control circuit and a switch circuit according to an embodiment of the invention;
FIG. 3 is a circuit diagram of a trigger circuit according to an embodiment of the present invention;
fig. 4 is a block diagram illustrating a structure of a mobile terminal according to an embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, an embodiment of the present invention provides a battery cell protection circuit 200 (as shown in fig. 4), which includes a charge and discharge control circuit 20, a switch circuit 30, and a trigger circuit 40; the charge and discharge control circuit 20 comprises a control chip 21 and a first control switch 22; one end of the first control switch 22 is connected to the negative end of the battery cell 100, and the other end is connected to the negative output end P-; the control chip 21 is connected in parallel with the battery cell 100, collects the working condition of the battery cell 100, and controls the working state of the first control switch 22 according to the working condition; the switch circuit 30 receives the level signal and controls the working state of the first control switch 22 according to the level signal; the trigger circuit 40 is connected to the switch circuit 30 and generates a level signal to be transmitted to the switch circuit 30.
The charge/discharge protection circuit is a circuit for protecting the battery cell 100, and can automatically prevent the battery cell 100 from being overcharged or overdischarged. The control chip 21 of the charge and discharge protection circuit is a commonly used lithium battery protection IC, and has a plurality of interfaces for connecting the battery cell 100 and other peripheral circuits. The first control switch 22 of the charge and discharge protection circuit is mainly configured to receive a control signal sent by the control chip 21, so as to control the charging and discharging of the battery cell 100, and also receive the control of the switch circuit 30, and generally only needs to control the discharging state of the battery cell 100.
The switch circuit 30 is mainly turned on or off according to the level signal sent by the trigger circuit 40, so as to generate a signal for controlling the first control switch 22 and control the operating state of the first control switch 22.
The trigger circuit 40 is mainly used for generating a level signal, and generally needs to receive a control of a user, such as pressing, toggling some switches, buttons, etc., to generate a high level signal.
Referring to fig. 2, in the present embodiment, the first control switch 22 includes a first NMOS transistor M1, a second NMOS transistor M2, a first parasitic diode D1, and a second parasitic diode D2; the drain electrode of the first NMOS tube M1 is connected with the drain electrode of the second NMOS tube M2; the gate of the first NMOS transistor M1 is connected to the discharge control interface D0 of the control chip 21, and the gate of the second NMOS transistor M2 is connected to the charge control interface C0 of the control chip 21; the source electrode of the first NMOS tube M1 is connected with the negative electrode end of the battery cell 100, and the source electrode of the second NMOS tube M2 is connected with the negative electrode output end P-; the anode of the first parasitic diode D1 is connected to the source of the first NMOS transistor M1, and the cathode is connected to the drain of the first NMOS transistor M1; the anode of the second parasitic diode D2 is connected to the source of the second NMOS transistor M2, and the cathode is connected to the drain of the second NMOS transistor M2.
When the voltage of the battery cell 100 is in the normal working range, the discharge control interface D0 and the charge control interface C0 of the control chip 21 output a high level, the first NMOS transistor M1 and the second NMOS transistor M2 are turned on, and the output voltage between the two electrodes of the battery cell 100 is normal; when the voltage is overcharged in the charging process of the battery cell 100, the charging control interface C0 of the control chip 21 outputs a low level, and turns off the corresponding second NMOS transistor M2, thereby stopping charging the battery cell 100; when the battery cell 100 discharges to make the voltage of the battery cell 100 lower than the over-discharge threshold, the discharge control interface D0 of the control chip 21 outputs a low level, and turns off the corresponding first NMOS transistor M1, so that the battery cell 100 stops discharging externally. The control process of the control chip 21 is completed by the inside of the control chip 21, and the outside cannot be controlled. For example, when the battery cell 100 is overcharged, the second NMOS transistor M2 is turned off, and after the current passes through the battery cell 100 from the first NMOS transistor M1 in the direction of P +, the current is in the opposite direction to the second parasitic diode D2, so that when the second NMOS transistor M2 is turned off, the battery cell 100 cannot be charged. Similarly, when the battery cell 100 discharges, the current flows from P "to P + through the second NMOS transistor M2, the first NMOS transistor M1, and the battery cell 100, and the on direction of the first parasitic diode D1 is opposite to that of the first NMOS transistor M1, so that the battery cell 100 cannot discharge when the first NMOS transistor M1 is turned off.
In this embodiment, the switch circuit 30 includes a third NMOS transistor M3, an electrode K, a first voltage-dividing resistor R1, and a second voltage-dividing resistor R2; the gate of the third NMOS transistor M3 is connected to the electrode K, the source is connected to the negative terminal of the battery cell 100, and the drain is connected to the gate of the first NMOS transistor M1; the gate of the first NMOS transistor M1 is connected to the discharge control interface D0 of the control chip 21 through a first voltage dividing resistor R1; the electrode K is connected with the trigger circuit 40 to receive a level signal; the electrode K is connected with the negative electrode output end P-through a second voltage-dividing resistor R2.
When the electrode K receives the high level signal and sends the high level signal to the third NMOS transistor M3, the third NMOS transistor M3 is turned on, the first voltage dividing resistor R1 divides the high level output by the control chip 21 through the discharge control interface D0, and then pulls down the gate voltage of the first NMOS transistor M1, so as to close the first NMOS transistor M1, and stop discharging the battery cell 100. Under the condition of lithium power outage, if a load is indirectly provided for P + and P-, the level of P-is close to P +, the conduction of the third NMOS tube M3 is controlled through the second voltage-dividing resistor R2, so that the first NMOS tube M1 is closed and locked, a charging loop is formed between P + and P-through the battery cell 100 only when the charger is plugged, the P-voltage is lower than VSS, the third NMOS tube M3 is closed, and the first NMOS tube M1 is conducted to enter a normal charging state. In this embodiment, the maximum voltage division on the electrode K should be lower than the turn-on threshold voltage VGS of the third NMOS transistor M3. The electrode K may also serve as an electrode K of a temperature detection terminal.
In this embodiment, the second voltage dividing resistor R2 is a thermistor. The temperature value of the battery cell 100 can be acquired through an external voltage-dividing resistor and an ADC (analog-to-digital conversion) port of the mobile terminal microprocessor, so that the action of the external charging circuit can be controlled.
In this embodiment, the battery cell protection circuit 200 further includes a charging diode D3, where a positive electrode of the charging diode D3 is connected to the negative electrode terminal of the battery cell 100, and a negative electrode thereof is connected to the electrode K. When the voltage of the battery cell 100 is over-discharged to 0V and cannot be activated (the electric quantity of the battery cell 100 is discharged, so that the first NMOS transistor M1 and the second NMOS transistor M2 cannot be turned on), the K electrode is connected to P under external control, i.e., a loop for charging the battery cell 100 is formed through the diode D1, and when the voltage of the battery cell 100 is charged to a certain extent, so that the control chip 21 can normally operate, the battery can be normally activated.
In this embodiment, a first capacitor C1 is connected between the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2, and mainly plays a role of filtering, so as to smooth abrupt pulses.
In this embodiment, the cell protection circuit 200 further includes a sampling resistor R3, one end of the sampling resistor R3 is connected to the source of the second NMOS transistor M2, and the other end is connected to the sampling interface VM of the control chip 21. The sampling resistor R3 may be built into the control chip 21.
In this embodiment, a filter circuit is further connected to a line connecting the control chip 21 and the positive terminal of the battery cell 100, where the filter circuit includes a second resistor R4 and a second capacitor C2, the second resistor R4 is connected in series with the second capacitor C2, the second resistor R4 is connected to the positive terminal of the battery cell 100, the second capacitor C2 is grounded, and a lead of a VDD interface of the control chip 21 is connected between the second resistor R4 and the second capacitor C2. The second resistor R4 may be built in the control chip 21.
Referring to fig. 3, the trigger circuit 40 includes a key 41 (typically, a power key of a common mobile terminal), a first falling edge triggered single binary pulse counter 42, a second falling edge triggered single binary pulse counter 43, and a delay reset time circuit 44; the positive output end of the battery cell 100 is respectively connected to the first falling edge trigger single binary pulse counter 42 and the second falling edge trigger single binary pulse counter 43; the key 41 is respectively connected with a first falling edge trigger single binary pulse counter 42 and a second falling edge trigger single binary pulse counter 43; the first falling edge triggered single binary pulse counter 42 is connected with the second falling edge triggered single binary pulse counter 43; the delay reset time circuit 44 is respectively connected to the first falling edge triggered single binary pulse counter 42 and the second falling edge triggered single binary pulse counter 43.
The trigger circuit 40 is powered by the P + and P-output terminals of the battery cell 100, and the delay reset time circuit 44 limits the time interval of the two times of pressing the key 41, so as to avoid false triggering, and is recommended to be set to be about 0.6 second. When the battery is powered on, the first falling edge triggers the single binary pulse counter 42 and the second falling edge triggers the single binary pulse counter 43 to output a 0 level, when the key 41 is pressed once, the first falling edge triggers the single binary pulse counter 42 to output a high level, the second falling edge triggers the single binary pulse counter 43 to output a low level, and the delay reset time circuit 44 starts timing, when the timing set time is not reached, if the key 41 is pressed again, the first falling edge triggers the single binary pulse counter 42 to output a 0 level, the second falling edge triggers the single binary pulse counter 43 to output a high level, so that the third NMOS transistor M3 in fig. 2 is controlled to be turned on through the electrode K, the first NMOS transistor M1 is turned off, the voltage difference between P + and P-is rapidly reduced (i.e., the P-potential is raised), when P-is raised to be higher than the negative terminal VSS of the battery cell 100 by a certain voltage VGS (VGS is the conduction threshold voltage of the third NMOS transistor M3), the third NMOS transistor M3 is turned on, and the battery cell 100 is in a disconnected state, which is similar to the state where the battery cell 100 is pulled out. At this time, only when the charger is inserted to apply a voltage to the P + and P-terminals, the battery cell 100 enters a charging state, that is, the VSS of the battery cell 100 is higher than the P-voltage, the third NMOS transistor M3 can be turned off, so that the battery protection board works normally.
In this embodiment, the first falling edge triggered single binary pulse counter 42 and the second falling edge triggered single binary pulse counter 43 are both low power D-type flip-flops.
In the battery cell protection circuit 200 of the embodiment of the present invention, the switch circuit 30 and the trigger circuit 40 are connected to the charge and discharge control circuit 20, and the operating state of the charge and discharge control circuit 20 can be controlled by the level signal sent by the trigger circuit 40, so that the circuit is simple and practical.
Referring to fig. 4, an embodiment of the present invention further provides a mobile terminal, which includes a casing 300, a battery cell 100 embedded in the casing 300, and a battery cell protection circuit 200 for protecting the battery cell 100.
Referring to fig. 1, the cell protection circuit 200 includes a charge/discharge control circuit 20, a switch circuit 30, and a trigger circuit 40; the charge and discharge control circuit 20 comprises a control chip 21 and a first control switch 22; one end of the first control switch 22 is connected to the negative end of the battery cell 100, and the other end is connected to the negative output end P-; the control chip 21 is connected in parallel with the battery cell 100, collects the working condition of the battery cell 100, and controls the working state of the first control switch 22 according to the working condition; the switch circuit 30 receives the level signal and controls the working state of the first control switch 22 according to the level signal; the trigger circuit 40 is connected to the switch circuit 30 and generates a level signal to be transmitted to the switch circuit 30.
The charge/discharge protection circuit is a circuit for protecting the battery cell 100, and can automatically prevent the battery cell 100 from being overcharged or overdischarged. The control chip 21 of the charge and discharge protection circuit is a commonly used lithium battery protection IC, and has a plurality of interfaces for connecting the battery cell 100 and other peripheral circuits. The first control switch 22 of the charge and discharge protection circuit is mainly configured to receive a control signal sent by the control chip 21, so as to control the charging and discharging of the battery cell 100, and also receive the control of the switch circuit 30, and generally only needs to control the discharging state of the battery cell 100.
The switch circuit 30 is mainly turned on or off according to the level signal sent by the trigger circuit 40, so as to generate a signal for controlling the first control switch 22 and control the operating state of the first control switch 22.
The trigger circuit 40 is mainly used for generating a level signal, and generally needs to receive a control of a user, such as pressing, toggling some switches, buttons, etc., to generate a high level signal.
Referring to fig. 2, in the present embodiment, the first control switch 22 includes a first NMOS transistor M1, a second NMOS transistor M2, a first parasitic diode D1, and a second parasitic diode D2; the drain electrode of the first NMOS tube M1 is connected with the drain electrode of the second NMOS tube M2; the gate of the first NMOS transistor M1 is connected to the discharge control interface D0 of the control chip 21, and the gate of the second NMOS transistor M2 is connected to the charge control interface C0 of the control chip 21; the source electrode of the first NMOS tube M1 is connected with the negative electrode end of the battery cell 100, and the source electrode of the second NMOS tube M2 is connected with the negative electrode output end P-; the anode of the first parasitic diode D1 is connected to the source of the first NMOS transistor M1, and the cathode is connected to the drain of the first NMOS transistor M1; the anode of the second parasitic diode D2 is connected to the source of the second NMOS transistor M2, and the cathode is connected to the drain of the second NMOS transistor M2.
When the voltage of the battery cell 100 is in the normal working range, the discharge control interface D0 and the charge control interface C0 of the control chip 21 output a high level, the first NMOS transistor M1 and the second NMOS transistor M2 are turned on, and the output voltage between the two electrodes of the battery cell 100 is normal; when the voltage is overcharged in the charging process of the battery cell 100, the charging control interface C0 of the control chip 21 outputs a low level, and turns off the corresponding second NMOS transistor M2, thereby stopping charging the battery cell 100; when the battery cell 100 discharges to make the voltage of the battery cell 100 lower than the over-discharge threshold, the discharge control interface D0 of the control chip 21 outputs a low level, and turns off the corresponding first NMOS transistor M1, so that the battery cell 100 stops discharging externally. The control process of the control chip 21 is completed by the inside of the control chip 21, and the outside cannot be controlled. For example, when the battery cell 100 is overcharged, the second NMOS transistor M2 is turned off, and after the current passes through the battery cell 100 from the first NMOS transistor M1 in the direction of P +, the current is in the opposite direction to the second parasitic diode D2, so that when the second NMOS transistor M2 is turned off, the battery cell 100 cannot be charged. Similarly, when the battery cell 100 discharges, the current flows from P "to P + through the second NMOS transistor M2, the first NMOS transistor M1, and the battery cell 100, and the on direction of the first parasitic diode D1 is opposite to that of the first NMOS transistor M1, so that the battery cell 100 cannot discharge when the first NMOS transistor M1 is turned off.
In this embodiment, the switch circuit 30 includes a third NMOS transistor M3, an electrode K, a first voltage-dividing resistor R1, and a second voltage-dividing resistor R2; the gate of the third NMOS transistor M3 is connected to the electrode K, the source is connected to the negative terminal of the battery cell 100, and the drain is connected to the gate of the first NMOS transistor M1; the gate of the first NMOS transistor M1 is connected to the discharge control interface D0 of the control chip 21 through a first voltage dividing resistor R1; the electrode K is connected with the trigger circuit 40 to receive a level signal; the electrode K is connected with the negative electrode output end P-through a second voltage-dividing resistor R2.
When the electrode K receives the high level signal and sends the high level signal to the third NMOS transistor M3, the third NMOS transistor M3 is turned on, the first voltage dividing resistor R1 divides the high level output by the control chip 21 through the discharge control interface D0, and then pulls down the gate voltage of the first NMOS transistor M1, so as to close the first NMOS transistor M1, and stop discharging the battery cell 100. Under the condition of lithium power outage, if a load is indirectly provided for P + and P-, the level of P-is close to P +, the conduction of the third NMOS tube M3 is controlled through the second voltage-dividing resistor R2, so that the first NMOS tube M1 is closed and locked, a charging loop is formed between P + and P-through the battery cell 100 only when the charger is plugged, the P-voltage is lower than VSS, the third NMOS tube M3 is closed, and the first NMOS tube M1 is conducted to enter a normal charging state. In this embodiment, the maximum voltage division on the electrode K should be lower than the turn-on threshold voltage VGS of the third NMOS transistor M3. The electrode K may also serve as an electrode K of a temperature detection terminal.
In this embodiment, the second voltage dividing resistor R2 is a thermistor. The temperature value of the battery cell 100 can be acquired through an external voltage-dividing resistor and an ADC (analog-to-digital conversion) port of the mobile terminal microprocessor, so that the action of the external charging circuit can be controlled.
In this embodiment, the battery cell protection circuit 200 further includes a charging diode D3, where a positive electrode of the charging diode D3 is connected to the negative electrode terminal of the battery cell 100, and a negative electrode thereof is connected to the electrode K. When the voltage of the battery cell 100 is over-discharged to 0V and cannot be activated (the electric quantity of the battery cell 100 is discharged, so that the first NMOS transistor M1 and the second NMOS transistor M2 cannot be turned on), the K electrode is connected to P under external control, i.e., a loop for charging the battery cell 100 is formed through the diode D1, and when the voltage of the battery cell 100 is charged to a certain extent, so that the control chip 21 can normally operate, the battery can be normally activated.
In this embodiment, a first capacitor C1 is connected between the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2, and mainly plays a role of filtering, so as to smooth abrupt pulses.
In this embodiment, the cell protection circuit 200 further includes a sampling resistor R3, one end of the sampling resistor R3 is connected to the source of the second NMOS transistor M2, and the other end is connected to the sampling interface VM of the control chip 21. The sampling resistor R3 may be built into the control chip 21.
In this embodiment, a filter circuit is further connected to a line connecting the control chip 21 and the positive terminal of the battery cell 100, where the filter circuit includes a second resistor R4 and a second capacitor C2, the second resistor R4 is connected in series with the second capacitor C2, the second resistor R4 is connected to the positive terminal of the battery cell 100, the second capacitor C2 is grounded, and a lead of a VDD interface of the control chip 21 is connected between the second resistor R4 and the second capacitor C2. The second resistor R4 may be built in the control chip 21.
Referring to fig. 3, the triggering circuit 40 includes a key 41, a first falling edge triggered single binary pulse counter 42, a second falling edge triggered single binary pulse counter 43, and a delay reset time circuit 44; the positive output end of the battery cell 100 is respectively connected to the first falling edge trigger single binary pulse counter 42 and the second falling edge trigger single binary pulse counter 43; the key 41 is respectively connected with a first falling edge trigger single binary pulse counter 42 and a second falling edge trigger single binary pulse counter 43; the first falling edge triggered single binary pulse counter 42 is connected with the second falling edge triggered single binary pulse counter 43; the delay reset time circuit 44 is respectively connected to the first falling edge triggered single binary pulse counter 42 and the second falling edge triggered single binary pulse counter 43.
The trigger circuit 40 is powered by the P + and P-output terminals of the battery cell 100, and the delay reset time circuit 44 limits the time interval of the two times of pressing the key 41, so as to avoid false triggering, and is recommended to be set to be about 0.6 second. When the battery is powered on, the first falling edge triggers the single binary pulse counter 42 and the second falling edge triggers the single binary pulse counter 43 to output a 0 level, when the key 41 is pressed once, the first falling edge triggers the single binary pulse counter 42 to output a high level, the second falling edge triggers the single binary pulse counter 43 to output a low level, and the delay reset time circuit 44 starts timing, when the timing set time is not reached, if the key 41 is pressed again, the first falling edge triggers the single binary pulse counter 42 to output a 0 level, the second falling edge triggers the single binary pulse counter 43 to output a high level, so that the third NMOS transistor M3 in fig. 2 is controlled to be turned on through the electrode K, the first NMOS transistor M1 is turned off, the voltage difference between P + and P-is rapidly reduced (i.e., the P-potential is raised), when P-is raised to be higher than the negative terminal VSS of the battery cell 100 by a certain voltage VGS (VGS is the conduction threshold voltage of the third NMOS transistor M3), the third NMOS transistor M3 is turned on, and the battery cell 100 is in a disconnected state, which is similar to the state where the battery cell 100 is pulled out. At this time, only when the charger is inserted to apply a voltage to the P + and P-terminals, the battery cell 100 enters a charging state, that is, the VSS of the battery cell 100 is higher than the P-voltage, the third NMOS transistor M3 can be turned off, so that the battery protection board works normally.
The key 41 is a switch key 41 of the mobile terminal, and when the mobile terminal is turned off after a specified time is pressed for a long time, and when the mobile terminal is turned off or generates heat abnormally and cannot be turned off by pressing the key 41 for a long time, the switch key 41 can be continuously pressed twice, so that the battery cell 100 stops discharging, and the battery does not need to be detached from the mobile terminal. For example, a mobile phone without a battery cover, such as an apple phone, a hua shi mobile phone, etc., cannot be plugged into or unplugged from a battery quickly, and when the mobile terminal is in a dead halt and the battery generates heat abnormally, the discharge loop of the battery core 100 can be cut off quickly through the battery core protection circuit 200, so as to achieve the requirement of quick shutdown by unplugging the battery.
In this embodiment, the first falling edge triggered single binary pulse counter 42 and the second falling edge triggered single binary pulse counter 43 are both low power D-type flip-flops.
In the mobile terminal according to the embodiment of the present invention, the battery cell 100 and the battery cell protection circuit 200 corresponding to the battery cell 100 are embedded in the casing 300, and when the battery cell 100 cannot be conventionally removed and is halted, and the battery is overheated, the battery cell 100 may be controlled to stop discharging through the trigger circuit 40, and the battery does not need to be detached without detaching the casing 300, so that a user can conveniently operate the mobile terminal for safety protection.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (7)
1. A battery cell protection circuit is characterized by comprising a charge-discharge control circuit, a switch circuit and a trigger circuit;
the charging and discharging control circuit comprises a control chip and a first control switch; one end of the first control switch is connected with the negative end of the battery cell, and the other end of the first control switch is connected with the negative output end P-; the control chip is connected with the battery cell in parallel, collects the working condition of the battery cell and controls the working state of the first control switch according to the working condition;
the switch circuit receives a level signal and controls the working state of the first control switch according to the level signal;
the trigger circuit is connected with the switch circuit, generates the level signal and sends the level signal to the switch circuit;
the first control switch comprises a first NMOS tube and a second NMOS tube;
the drain electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube; the grid electrode of the first NMOS tube is connected with the discharge control interface of the control chip, and the grid electrode of the second NMOS tube is connected with the charge control interface of the control chip; the source electrode of the first NMOS tube is connected with the negative electrode end of the battery cell, and the source electrode of the second NMOS tube is connected with the negative electrode output end P-;
the switch circuit comprises a third NMOS tube, an electrode K, a first voltage-dividing resistor and a second voltage-dividing resistor;
the grid electrode of the third NMOS tube is connected with the electrode K, the source electrode of the third NMOS tube is connected with the negative electrode end of the battery cell, and the drain electrode of the third NMOS tube is connected with the grid electrode of the first NMOS tube;
the grid electrode of the first NMOS tube is connected with a discharge control interface of the control chip through the first divider resistor;
the electrode K is connected with the trigger circuit to receive the level signal;
the electrode K is connected with the negative electrode output end P < - > through the second voltage-dividing resistor;
the trigger circuit comprises a key, a first falling edge trigger single binary pulse counter, a second falling edge trigger single binary pulse counter and a delay reset time circuit; the key is a power key of the mobile terminal comprising the battery cell protection circuit;
the positive output end of the battery cell is respectively connected with the first falling edge trigger single binary pulse counter and the second falling edge trigger single binary pulse counter; the key is respectively connected with the first falling edge trigger single binary pulse counter and the second falling edge trigger single binary pulse counter; the first falling edge trigger single binary pulse counter is connected with the second falling edge trigger single binary pulse counter; the delay reset time circuit is respectively connected with the first falling edge trigger single binary pulse counter and the second falling edge trigger single binary pulse counter.
2. The cell protection circuit of claim 1, wherein the second voltage-dividing resistor is a thermistor.
3. The cell protection circuit of claim 1, further comprising a charging diode, wherein an anode of the charging diode is connected to the negative terminal of the cell, and a cathode of the charging diode is connected to the electrode K.
4. The cell protection circuit of claim 1, wherein a first capacitor is connected between the source electrode of the first NMOS transistor and the source electrode of the second NMOS transistor.
5. The battery cell protection circuit of claim 1, further comprising a sampling resistor, wherein one end of the sampling resistor is connected to the source of the second NMOS transistor, and the other end of the sampling resistor is connected to the sampling interface of the control chip.
6. The cell protection circuit of claim 1, wherein the first falling edge triggered single binary pulse counter and the second falling edge triggered single binary pulse counter are both low-power D-type flip-flops.
7. The mobile terminal is characterized by comprising a shell, a battery cell and a battery cell protection circuit, wherein the battery cell is arranged in the shell;
the cell protection circuit of any of claims 1-6.
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| CN109672249A (en) * | 2019-01-22 | 2019-04-23 | 深圳流量链科技有限公司 | A kind of battery management protective device |
| CN112751384B (en) * | 2020-12-30 | 2024-03-26 | 珠海冠宇电源有限公司 | Electronic equipment control method and electronic equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201478415U (en) * | 2009-07-30 | 2010-05-19 | 贝林杰 | Waterproof mobile phone battery |
| CN206076997U (en) * | 2016-08-31 | 2017-04-05 | 深圳市华美兴泰科技股份有限公司 | The battery protection active circuit of portable power source and portable power source |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201478415U (en) * | 2009-07-30 | 2010-05-19 | 贝林杰 | Waterproof mobile phone battery |
| CN206076997U (en) * | 2016-08-31 | 2017-04-05 | 深圳市华美兴泰科技股份有限公司 | The battery protection active circuit of portable power source and portable power source |
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