CN110825551A - Hardware watchdog circuit and embedded system thereof - Google Patents
Hardware watchdog circuit and embedded system thereof Download PDFInfo
- Publication number
- CN110825551A CN110825551A CN201911344221.XA CN201911344221A CN110825551A CN 110825551 A CN110825551 A CN 110825551A CN 201911344221 A CN201911344221 A CN 201911344221A CN 110825551 A CN110825551 A CN 110825551A
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- circuit
- signal
- watchdog
- discrete device
- microcontroller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
Abstract
The invention provides a hardware watchdog circuit and an embedded system thereof, wherein the hardware watchdog circuit comprises a discrete device combined circuit and a watchdog chip; the discrete device combination circuit is connected with the microcontroller and used for outputting a high-resistance state during the power-on period of the system and transmitting a dog feeding signal generated by the microcontroller to the watchdog chip during the working period of the system; the watchdog chip is connected with the discrete device combination circuit and used for receiving the dog feeding signal and sending a reset signal to the microcontroller when the dog feeding signal is abnormal. The technical problem of high cost in the prior art that a watchdog circuit needs to be matched with a tri-state gate buffer for use is solved. The effect of using the discrete device combination circuit with low cost to realize the tri-state gate buffer is achieved, the characteristics of the switch tube of the discrete device combination circuit are ingeniously utilized, the reset phenomenon caused by signal lag in the system just powered on is avoided, the normal use of the watchdog circuit is ensured, and the cost of the watchdog circuit is greatly reduced.
Description
Technical Field
The invention relates to the technical field of embedded application systems, in particular to a hardware watchdog circuit and an embedded system thereof.
Background
In the application process of the embedded system, the system has a certain probability of program runaway and card death due to self-reason faults or external interference, so that the system crashes and generates unpredictable loss, the system is required to be capable of automatically correcting errors and restarting the system, and the watchdog circuit is generated based on the requirement.
The main working principle of the watchdog circuit is that a WDI pin of a watchdog chip is connected with an I/O of a system microcontroller, when the system is in a normal working period, the I/O port outputs a periodic system signal to the watchdog chip, once the system is abnormal, the periodic signal is abnormal or disappears, at the moment, the watchdog chip can not detect the normal input of the signal, a reset signal is output to the system microcontroller, so that the system is restarted and finally returns to normal, the system microcontroller outputs a periodic dog feeding signal WDI from the moment of being started to the moment of finishing, a certain time is needed in the process, in order to avoid resetting the system of the watchdog chip, the WDI of the watchdog chip needs to be in a high-resistance state, in order to realize the behavior, a three-state buffer is generally used in a peripheral matching circuit of the traditional watchdog chip, for example, 74LVC1G126GW, but the cost of one tri-state gate buffer is relatively high, and how to reduce the cost will certainly improve the product competitiveness.
The applicant of the present invention finds that the prior art has at least the following technical problems:
the watchdog circuit in the prior art needs to be matched with a tri-state gate buffer for use, and the technical problem of high cost exists.
Disclosure of Invention
The embodiment of the invention provides a hardware watchdog circuit, which solves the technical problem of high cost in the prior art that the watchdog circuit needs to be matched with a tri-state gate buffer for use.
In view of the foregoing problems, in a first aspect, embodiments of the present invention provide a hardware watchdog circuit, which includes a discrete device combination circuit and a watchdog chip; the discrete device combination circuit is connected with the microcontroller and used for outputting a high-resistance state during the power-on period of the system and transmitting a dog feeding signal generated by the microcontroller to the watchdog chip during the working period of the system; the watchdog chip is connected with the discrete device combination circuit and used for receiving the dog feeding signal and sending a reset signal to the microcontroller when the dog feeding signal is abnormal.
Discrete device combination circuit
Preferably, the discrete device combination circuit includes: a first resistor and an NPN triode;
one end of the first resistor is used for receiving an enabling signal of the dog feeding signal, the other end of the first resistor is connected with a base electrode of the NPN triode, an emitter of the NPN triode is used for receiving the dog feeding signal, and a collector of the NPN triode is used as an output end of the discrete device combination circuit.
Preferably, the discrete device combination circuit further includes a second resistor; one end of the second resistor is connected with one end of the first resistor, and the other end of the second resistor is grounded.
Preferably, the first resistance is not more than 10k Ω.
Preferably, the dog feeding signal is a periodic square wave signal.
Preferably, the watchdog chip comprises a WDI pin and a reset terminal; the WDI pin is connected with the output end of the discrete device combination circuit and used for receiving the dog feeding signal; the reset end is connected with the microcontroller and used for sending the reset signal.
In a second aspect, an embodiment of the present invention provides an embedded system, which includes a microcontroller and the hardware watchdog circuit.
One or more technical solutions in the embodiments of the present application have at least one or more of the following technical effects:
the hardware watchdog circuit provided by the embodiment of the invention comprises a discrete device combined circuit and a watchdog chip, wherein the discrete device combined circuit is connected with a microcontroller, when a system is powered on, namely before an enable signal is not generated, a high-resistance state is output to block the watchdog function, after the enable signal is generated, the connection with the watchdog chip is switched on, a dog feeding signal generated by the microcontroller is transmitted to the watchdog chip through the discrete device combined circuit, the watchdog chip determines whether a reset signal needs to be generated according to the received dog feeding signal, when the watchdog chip does not receive the system signal, the reset signal is transmitted to the system microcontroller to forcibly reset and restart the system, so as to avoid system crash caused by system faults, ensure normal operation of the system, and through the switching tube characteristic of the discrete device combined circuit, the reset condition that causes because of system microcontroller signal lags behind when just starting up is effectively avoided, guarantee the normal operating of system, utilize discrete device composite circuit low cost's characteristics simultaneously, reduce the cost of watchdog circuit by a wide margin, replace the higher tristate gate buffer of cost in the traditional watchdog circuit, effective reduce cost under the prerequisite of guaranteeing the function realization to the watchdog circuit need cooperate the tristate gate buffer to use among the prior art has been solved, has with high costs technical problem.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a hardware watchdog circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a conventional watchdog circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a dog feed signal from a system microcontroller according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a dog feeding signal received by the watchdog chip according to the embodiment of the present invention.
Description of reference numerals: the circuit comprises a watchdog chip U1, a first resistor R6, an NPN triode C3, a dog feeding signal WDI, a second resistor R5 and a tri-state gate buffer U2.
Detailed Description
The embodiment of the invention provides a hardware watchdog circuit, which is used for solving the technical problem of high cost in the prior art that the watchdog circuit needs to be matched with a tri-state gate buffer for use.
The technical scheme provided by the invention has the following general idea:
the hardware watchdog circuit comprises a discrete device combined circuit and a watchdog chip; the discrete device combination circuit is connected with the microcontroller and used for outputting a high-resistance state during the power-on period of the system and transmitting a dog feeding signal generated by the microcontroller to the watchdog chip during the working period of the system; the watchdog chip is connected with the discrete device combination circuit and used for receiving the dog feeding signal and sending a reset signal to the microcontroller when the dog feeding signal is abnormal. The effect of using the discrete device combination circuit with low cost to realize the tri-state gate buffer is achieved, the characteristics of the switch tube of the discrete device combination circuit are ingeniously utilized, the discrete device combination circuit is in a high-impedance state when the low level is reached, the reset phenomenon caused by signal lag in the system just powered on is avoided, the normal use of the watchdog circuit is ensured, and the cost of the watchdog circuit is greatly reduced.
It should be understood that in the embodiment of the present invention, the tri-state gate buffer (also called tri-state gate, tri-state driver) has a tri-state output controlled by the enable output, when the enable output is active, the device implements a normal logic state output (logic 0, logic 1), and when the enable input is inactive, the output is in a high impedance state, i.e. equivalent to being disconnected from the connected circuit.
It should be understood that in the embodiments of the present invention, the NPN transistor is formed of three semiconductors, two N-type and one P-type semiconductors, the P-type semiconductor being in the middle and the two N-type semiconductors being on both sides, the transistor being the most important device in the electronic circuit and having the most important functions of current amplification and switching, the transistor also being referred to as a transistor, which can be said to be the most important device in the electronic circuit, the most important functions of current amplification and switching, the transistor having three electrodes as the name implies, the diode being formed of a PN junction, and the transistor being formed of two PN junctions, the common one of the electrodes being the Base (indicated by the letter B-B from english Base, Base), and Emitter (indicated by the letter C-C from Collector, emission), the other two electrodes being the Collector (indicated by the letter E-E from english Emitter, emission), the most essential function of the transistor being the amplification, which can change the electrical signal energy of a certain intensity, which is still converted into a signal energy, which is a small change in the Base of the current, which is a small current amplification factor, i.e. a change in the Base of the transistor, which is observed in the Base of a small current, which is added to the Base of the transistor, which is a small current β.
It should be understood that, in the embodiments of the present invention, the square wave signal refers to the quality of a signal in a circuit system, and if the signal can be transmitted from a source end to a receiving end without distortion within a required time, the signal is referred to as a square wave signal.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
Fig. 1 is a schematic structural diagram of a hardware watchdog circuit according to an embodiment of the present invention, and referring to fig. 1, the hardware watchdog circuit according to the embodiment of the present invention includes: discrete device combination circuit, watchdog chip U1.
The discrete device combination circuit is connected with the microcontroller and used for outputting a high-resistance state during the power-on period of the system and transmitting a dog feeding signal WDI generated by the microcontroller to the watchdog chip during the working period of the system;
the watchdog chip U1 is connected to the discrete device combinational circuit, and is configured to receive the dog feeding signal WDI and send a reset signal to the microcontroller when the dog feeding signal WDI is abnormal. Specifically, after the system microcontroller is powered on and started, the enable signal is transmitted after a certain time interval, before the enable signal is not transmitted, the discrete device combination circuit has the characteristic of keeping a high impedance state, at the moment, the watchdog function is stopped, the reset condition caused by no signal is avoided, until the system microcontroller transmits the enable signal, the discrete device combination circuit is connected with the system microcontroller, after the enable signal is received, the watchdog function is started, the dog feeding signal WDI transmitted by the system is transmitted to the watchdog chip U1, the watchdog chip U1 judges whether the reset is needed according to the condition of the received dog feeding signal WDI, namely, the watchdog chip U1 continuously receives the dog feeding signal WDI, the system keeps normal work, and once the system is abnormal, the dog feeding signal WDI is abnormal or disappears, the watchdog chip U1 outputs a reset signal to the system microcontroller due to the fact that the normal input of the dog feeding signal WDI cannot be detected, the embodiment of the invention replaces a tristate gate buffer U2 in the traditional circuit by using a discrete device combination circuit, please refer to a schematic structural diagram of the traditional watchdog circuit in fig. 2, wherein discrete devices refer to independent and independent elements with independent functions such as a resistor, a capacitor, a diode, a triode and the like, and can be effectively matched with the watchdog circuit to ensure the normal use of the watchdog circuit, thereby avoiding the influence of error reset operation caused by signal lag on the normal work of the system when the system is just powered on.
Further, the discrete device combination circuit comprises a first resistor R6 and an NPN triode C3; one end of the first resistor R6 is used for receiving an enable signal of the dog feeding signal WDI, the other end of the first resistor R6 is connected to the base of the NPN triode C3, the emitter of the NPN triode C3 is used for receiving the dog feeding signal WDI, and the collector of the NPN triode C3 is used as the output end of the discrete device combination circuit.
Specifically, the discrete device combination circuit is composed of a resistor and a conventional NPN triode, the characteristic of a switching tube of the NPN triode is utilized, the resistor is matched with the resistor to realize the purpose, one end of a first resistor R6 is connected with the microcontroller to receive an enabling signal sent by the microcontroller, the other end of the first resistor R6 is connected with a base electrode of an NPN triode C3 to transmit the enabling signal, and an emitting electrode of the NPN triode receives a dog feeding signal sent by the microcontroller; the collector of the NPN triode is connected with a watchdog chip U1 at the output end, when the NPN receives an enabling signal, a dog feeding signal WDI is sent to the watchdog chip U1, when the enabling signal of the system does not pass through, the NPN triode C3 is in a high-resistance position, so that the watchdog function is blocked, when the enabling signal of the system is normally sent, the system microcontroller sends the signal to a first resistor R6 to have normal waveform input, and the NPN triode C3 transmits the signal to start the watchdog function. The specific process is that a system microcontroller is connected with a first resistor R6, when no system enable signal WDI _ enable is output, a collector PIN2 of an NPN triode C3 is in a high-impedance position to block a watchdog function, when the system microcontroller generates a system dog feeding signal WDI to be sent out, the NPN triode C3 receives a normal pulse signal and sends the received dog feeding signal WDI to a watchdog chip U1, the watchdog chip U1 receives the dog feeding signal WDI to enable the watchdog chip to normally run, when the system is abnormal or failed, the dog feeding signal WDI is abnormal, and the watchdog chip U1 generates a reset signal to be sent to the system microcontroller to forcibly reset the system due to the fact that the system is not normally received, and therefore the normal running of the system is guaranteed.
Further, the discrete device combination circuit further comprises a second resistor R5; one end of the second resistor R5 is connected to one end of the first resistor R6, and the other end of the second resistor R5 is grounded.
Specifically, a second resistor R5 is arranged between the first resistor R6 and the system microcontroller, and is connected with the ground wire through a second resistor R5, so that a pull-down complete cut-off state is realized, and a low level is maintained, so that the pin3 of the NPN triode C3 is always in a high-resistance state before the system microcontroller does not send an enable signal.
Further, the first resistor R6 is not greater than 10k Ω.
Specifically, the first resistor R6 is preferably not greater than 10k Ω, and is usually a resistor of 1k Ω, so as to ensure normal transmission of current signals of the NPN transistor.
Further, the dog feeding signal is a periodic square wave signal.
Specifically, referring to fig. 1, WDI _ enable is an enable signal from the system microcontroller, WDI is a dog feeding signal from the system microcontroller, Reset _ output is a Reset signal of the watchdog chip U1 (which can Reset the system microcontroller), when the system microcontroller starts to power on, the NPN transistor 2 (pin3 of Q1) keeps high impedance state, so as to block the watchdog function, and prevent the system from being Reset at this moment until the system microcontroller starts to output a high level enable signal WDI _ enable and a periodic dog feeding signal WDI, as shown in fig. 3-4, which are a dog feeding signal (pin2, i.e., an emitter) from the system microcontroller and a dog feeding signal (pin3) received by the watchdog chip, respectively. In the embodiment of the invention, the dog feeding signals are square wave signals with high and low levels lasting for 1s, the specific duration can be set according to the system, once the system has faults such as crash and the like, the microcontroller stops outputting the WDI dog feeding signals, so that the watchdog chip U1 is triggered to output the Reset signal Reset _ output with low level, and the microcontroller system is forcibly Reset, so that the faults are relieved.
Further, the watchdog chip U1 includes a WDI pin and a RESET terminal RESET; the WDI pin is connected with the output end of the discrete device combination circuit and used for receiving the dog feeding signal WDI; the RESET end RESET is connected with the microcontroller and used for sending the RESET signal.
Specifically, a WDI pin of the watchdog chip U1 is connected to an I/O of the system microcontroller, and when the system is in a normal operation period, the I/O port outputs a periodic square wave signal, i.e., a dog feeding signal, to the watchdog chip U1 through the NPN transistor C3, and once the system is abnormal, the periodic signal is abnormal or disappears, and at this time, the watchdog chip U1 outputs a RESET signal to the system microcontroller through the RESET terminal RESET because the normal input of the signal cannot be detected, so as to forcibly restart the system, and finally recover the normal operation of the system.
Example two
The embedded system of the embodiment of the present invention includes a microcontroller and a hardware watchdog circuit in the first embodiment, and various variations and specific embodiments in the first embodiment are also applicable to the embedded system of the present embodiment.
One or more technical solutions in the embodiments of the present application have at least one or more of the following technical effects:
the hardware watchdog circuit provided by the embodiment of the invention comprises a discrete device combined circuit and a watchdog chip, wherein the discrete device combined circuit is connected with a microcontroller, when a system is powered on, namely before an enabling signal is not generated, a high-resistance state is output to block the watchdog function, after the enabling signal is generated, the connection with the watchdog chip is switched on, a dog feeding signal generated by the microcontroller is transmitted to the watchdog chip through the discrete device combined circuit, the watchdog chip determines whether a reset signal needs to be generated according to the received dog feeding signal, when the watchdog chip does not receive the system signal, the reset signal is transmitted to the system microcontroller to forcibly reset and restart the system so as to avoid system crash caused by system faults, ensure the normal operation of the system, and through the switching tube characteristic of the discrete device combined circuit, the reset condition that causes because of system microcontroller signal lags behind when just starting up is effectively avoided, guarantee the normal operating of system, utilize discrete device composite circuit low cost's characteristics simultaneously, reduce the cost of watchdog circuit by a wide margin, replace the higher tristate gate buffer of cost in the traditional watchdog circuit, effective reduce cost under the prerequisite of guaranteeing the function realization to the watchdog circuit need cooperate the tristate gate buffer to use among the prior art has been solved, has with high costs technical problem.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made in the embodiments of the present invention without departing from the spirit or scope of the embodiments of the invention. Thus, if such modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to encompass such modifications and variations.
Claims (7)
1. A hardware watchdog circuit, wherein the hardware watchdog circuit comprises a discrete device combination circuit and a watchdog chip;
the discrete device combination circuit is connected with the microcontroller and used for outputting a high-resistance state during the power-on period of the system and transmitting a dog feeding signal generated by the microcontroller to the watchdog chip during the working period of the system;
the watchdog chip is connected with the discrete device combination circuit and used for receiving the dog feeding signal and sending a reset signal to the microcontroller when the dog feeding signal is abnormal.
2. The hardware watchdog circuit of claim 1, wherein the discrete device combinational circuit comprises a first resistor and an NPN triode;
one end of the first resistor is used for receiving an enabling signal of the dog feeding signal, the other end of the first resistor is connected with a base electrode of the NPN triode, an emitter of the NPN triode is used for receiving the dog feeding signal, and a collector of the NPN triode is used as an output end of the discrete device combination circuit.
3. The hardware watchdog circuit of claim 2, wherein the discrete device combination circuit further comprises a second resistor;
one end of the second resistor is connected with one end of the first resistor, and the other end of the second resistor is grounded.
4. The hardware watchdog circuit of claim 2, wherein the first resistor has a resistance of no greater than 10k Ω.
5. The hardware watchdog circuit of claim 1, wherein the feed dog signal is a periodic square wave signal.
6. The hardware watchdog circuit of claim 1, wherein the watchdog chip comprises a WDI pin and a reset terminal;
the WDI pin is connected with the output end of the discrete device combination circuit and used for receiving the dog feeding signal;
the reset end is connected with the microcontroller and used for sending the reset signal.
7. An embedded system comprising a microcontroller and the hardware watchdog circuit of any one of claims 1 to 6.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911344221.XA CN110825551A (en) | 2019-12-24 | 2019-12-24 | Hardware watchdog circuit and embedded system thereof |
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| CN201911344221.XA CN110825551A (en) | 2019-12-24 | 2019-12-24 | Hardware watchdog circuit and embedded system thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111516497A (en) * | 2020-04-29 | 2020-08-11 | 宁德时代新能源科技股份有限公司 | Load control method and circuit, battery management system and vehicle |
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2019
- 2019-12-24 CN CN201911344221.XA patent/CN110825551A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111516497A (en) * | 2020-04-29 | 2020-08-11 | 宁德时代新能源科技股份有限公司 | Load control method and circuit, battery management system and vehicle |
| CN111516497B (en) * | 2020-04-29 | 2024-04-19 | 宁德时代新能源科技股份有限公司 | Load control method and circuit, battery management system and vehicle |
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